From d4804be800a38763a3386d6476d9ba8b7a7305dc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 19 May 2023 11:34:49 -0700 Subject: [PATCH 1/2] [ci skip] Move xcelium.mk out of top-level --- sims/xcelium/Makefile | 2 +- xcelium.mk => sims/xcelium/xcelium.mk | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename xcelium.mk => sims/xcelium/xcelium.mk (100%) diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile index 12b31087..2ca75d91 100644 --- a/sims/xcelium/Makefile +++ b/sims/xcelium/Makefile @@ -39,7 +39,7 @@ sim_workdir = $(build_dir)/xcelium.d sim_run_tcl = $(build_dir)/xcelium_run.tcl sim_debug_run_tcl = $(build_dir)/xcelium_debug_run.tcl -include $(base_dir)/xcelium.mk +include $(base_dir)/sims/xcelium/xcelium.mk .PHONY: default debug default: $(sim) diff --git a/xcelium.mk b/sims/xcelium/xcelium.mk similarity index 100% rename from xcelium.mk rename to sims/xcelium/xcelium.mk From 333df95a4228d5b203c5c209dbcaf51f2ed61b0a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 23 May 2023 12:07:28 -0700 Subject: [PATCH 2/2] Set default config back to 1-channel --- .github/scripts/defaults.sh | 2 +- .github/scripts/run-tests.sh | 3 +++ .../chipyard/src/main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/PeripheralDeviceConfigs.scala | 5 +++++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index d2362dbd..d9dd5f96 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -38,7 +38,7 @@ grouping["group-fpga"]="arty vcu118 vc707" # key value store to get the build strings declare -A mapping -mapping["chipyard-rocket"]="" +mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig" mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig" mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig" mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig" diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh index 8173486e..5ed6aab4 100755 --- a/.github/scripts/run-tests.sh +++ b/.github/scripts/run-tests.sh @@ -31,6 +31,9 @@ run_tracegen () { case $1 in chipyard-rocket) run_bmark ${mapping[$1]} + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADMEM=1 BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv + make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv ;; chipyard-dmirocket) $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000 diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 3b3ea7d4..545f78d5 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -59,7 +59,7 @@ class AbstractConfig extends Config( new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // Unspecified frequencies with match the pbus frequency (which is always set) new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus - new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ // Default 2 memory channels + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 029dd2bd..8da229b4 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -75,3 +75,8 @@ class ManyPeripheralsRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) + +class QuadChannelRocketConfig extends Config( + new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new chipyard.config.AbstractConfig)