diff --git a/common.mk b/common.mk
index e2603be7..d7703f7e 100644
--- a/common.mk
+++ b/common.mk
@@ -53,7 +53,7 @@ $(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FI
 	cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
 
 $(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
-	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(FIRRTL_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) -td $(build_dir)"
 	grep -v "SimSerial.cc\|SimDTM.cc\|SimJTAG.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
diff --git a/sims/verisim/Makefile b/sims/verisim/Makefile
index 89d9c6e8..93f45d5a 100644
--- a/sims/verisim/Makefile
+++ b/sims/verisim/Makefile
@@ -41,11 +41,11 @@ include $(sim_dir)/verilator.mk
 model_dir = $(build_dir)/$(long_name)
 model_dir_debug = $(build_dir)/$(long_name).debug
 
-model_header = $(model_dir)/V$(MODEL).h
-model_header_debug = $(model_dir_debug)/V$(MODEL).h
+model_header = $(model_dir)/V$(VLOG_MODEL).h
+model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
 
-model_mk = $(model_dir)/V$(MODEL).mk
-model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
+model_mk = $(model_dir)/V$(VLOG_MODEL).mk
+model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 
 #########################################################################################
 # build makefile fragment that builds the verilator sim rules
@@ -72,10 +72,10 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
 # invoke make to make verilator sim rules
 #########################################################################################
 $(sim): $(model_mk)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk
 
 $(sim_debug): $(model_mk_debug)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk
 
 #########################################################################################
 # create a vcs vpd rule
diff --git a/sims/verisim/verilator.mk b/sims/verisim/verilator.mk
index 3af9b335..b0aaae62 100644
--- a/sims/verisim/verilator.mk
+++ b/sims/verisim/verilator.mk
@@ -39,9 +39,9 @@ verilator/verilator-$(VERILATOR_VERSION).tar.gz:
 #########################################################################################
 VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
 CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
-VERILATOR_FLAGS := --top-module $(MODEL) \
+VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \
 	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
 	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
 	--output-split 20000 \
 	-Wno-STMTDLY --x-assign unique \
-	-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR"
+	-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR"
diff --git a/variables.mk b/variables.mk
index baf18d6a..34d829fe 100644
--- a/variables.mk
+++ b/variables.mk
@@ -7,7 +7,7 @@
 # descriptions:
 #   PROJECT = the scala package to find the MODEL/Generator in
 #   MODEL = the top level module of the project in Chisel (normally the harness)
-#   FIRRTL_MODEL = the top level module of the project in Firrtl (normally the harness)
+#   VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness)
 #   CONFIG = the configuration class to give the parameters for the project
 #   CFG_PROJECT = the scala package to find the CONFIG class
 #   SBT_PROJECT = the SBT project that you should find the Generator class in
@@ -17,14 +17,14 @@
 # project specific:
 # 	SUB_PROJECT = use the specific subproject default variables
 #########################################################################################
-PROJECT      ?= example
-MODEL        ?= RocketTestHarness
-FIRRTL_MODEL ?= TestHarness
-CONFIG       ?= DefaultRocketConfig
-CFG_PROJECT  ?= $(PROJECT)
-SBT_PROJECT  ?= $(PROJECT)
-TB           ?= TestDriver
-TOP          ?= RocketTop
+PROJECT     ?= example
+MODEL       ?= RocketTestHarness
+VLOG_MODEL  ?= TestHarness
+CONFIG      ?= DefaultRocketConfig
+CFG_PROJECT ?= $(PROJECT)
+SBT_PROJECT ?= $(PROJECT)
+TB          ?= TestDriver
+TOP         ?= RocketTop
 
 # make it so that you only change 1 param to change most or all of them!
 SUB_PROJECT ?= example