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Merge branch 'main' into fix-vcu118

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This commit is contained in:
-T.K.-
2023-12-20 22:40:45 -08:00
committed by GitHub
parent c32de04b5d 32f79a82bb
commit 2be3d3d880
51 changed files with 1137 additions and 1029 deletions
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6
fpga/Makefile
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@@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo)
FPGA_BRAND ?= xilinx
endif
ifeq ($(SUB_PROJECT),arty)
ifeq ($(SUB_PROJECT),arty35t)
# TODO: Fix with Arty
SBT_PROJECT ?= fpga_platforms
MODEL ?= ArtyFPGATestHarness
VLOG_MODEL ?= ArtyFPGATestHarness
MODEL ?= Arty35THarness
VLOG_MODEL ?= Arty35THarness
MODEL_PACKAGE ?= chipyard.fpga.arty
CONFIG ?= TinyRocketArtyConfig
CONFIG_PACKAGE ?= chipyard.fpga.arty

2
fpga/fpga-shells

Submodule fpga/fpga-shells updated: 2ce3e6f3df...a6cfb6f363

2
fpga/src/main/scala/arty/Configs.scala
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@@ -27,6 +27,8 @@ class WithArtyTweaks extends Config(
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32000) ++
new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new testchipip.WithNoSerialTL
)

8
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder}
import chipyard.iobinders._
class WithArtyDebugResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: DebugResetPort) => {
case (th: Arty35THarness, port: DebugResetPort) => {
th.dut_ndreset := port.io // Debug module reset
}
})
class WithArtyJTAGResetHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGResetPort) => {
case (th: Arty35THarness, port: JTAGResetPort) => {
port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset
}
})
class WithArtyJTAGHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: JTAGPort) => {
case (th: Arty35THarness, port: JTAGPort) => {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := port.io.TDO
jtag_wire.TDO.driven := true.B
@@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({
})
class WithArtyUARTHarnessBinder extends HarnessBinder({
case (th: ArtyFPGATestHarness, port: UARTPort) => {
case (th: Arty35THarness, port: UARTPort) => {
withClockAndReset(th.clock_32MHz, th.ck_rst) {
IOBUF(th.uart_rxd_out, port.io.txd)
port.io.rxd := IOBUF(th.uart_txd_in)

2
fpga/src/main/scala/arty/TestHarness.scala
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@@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell}
import chipyard.harness.{HasHarnessInstantiators}
class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators {
// Convert harness resets from Bool to Reset type.
val hReset = Wire(Reset())
hReset := ~ck_rst

3
fpga/src/main/scala/nexysvideo/Configs.scala
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@@ -33,6 +33,7 @@ class WithNexysVideoTweaks extends Config(
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
@@ -69,4 +70,4 @@ class TinyRocketNexysVideoConfig extends Config(
new WithTinyNexysVideoTweaks ++
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.TinyRocketConfig)
// DOC include end: WithTinyNexysVideoTweaks and Rocket
// DOC include end: WithTinyNexysVideoTweaks and Rocket

11
fpga/src/main/scala/vc707/Configs.scala
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@@ -35,7 +35,7 @@ class WithSystemModifications extends Config((site, here, up) => {
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vc707/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VC7074GDDRSize)))) // set extmem to DDR size (note the size)
case SerialTLKey => None // remove serialized tl port
case SerialTLKey => Nil // remove serialized tl port
})
class WithVC707Tweaks extends Config (
@@ -45,6 +45,8 @@ class WithVC707Tweaks extends Config (
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq
@@ -74,8 +76,11 @@ class BoomVC707Config extends Config (
)
class WithFPGAFrequency(fMHz: Double) extends Config (
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
new chipyard.config.WithMemoryBusFrequency(fMHz)
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
new chipyard.config.WithControlBusFrequency(fMHz) ++
new chipyard.config.WithFrontBusFrequency(fMHz)
)
class WithFPGAFreq25MHz extends WithFPGAFrequency(25)

7
fpga/src/main/scala/vcu118/Configs.scala
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@@ -36,7 +36,7 @@ class WithSystemModifications extends Config((site, here, up) => {
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
}
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
case SerialTLKey => None // remove serialized tl port
case SerialTLKey => Nil // remove serialized tl port
})
// DOC include start: AbstractVCU118 and Rocket
@@ -46,6 +46,7 @@ class WithVCU118Tweaks extends Config(
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(100) ++
new chipyard.config.WithSystemBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
// harness binders
@@ -76,7 +77,9 @@ class BoomVCU118Config extends Config(
class WithFPGAFrequency(fMHz: Double) extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++ // assumes using PBUS as default freq.
new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
new chipyard.config.WithControlBusFrequency(fMHz) ++
new chipyard.config.WithFrontBusFrequency(fMHz) ++
new chipyard.config.WithMemoryBusFrequency(fMHz)
)