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[skip ci] abandon sv2v, Genus happy with patched firtool

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Harrison Liew
2023-02-08 19:00:26 -08:00
parent 61d094e887
commit 2bfc6e1347
4 changed files with 3 additions and 15 deletions
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2
common.mk
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@@ -194,7 +194,7 @@ endif
--disable-annotation-classless \ --disable-annotation-classless \
--disable-annotation-unknown \ --disable-annotation-unknown \
--mlir-timing \ --mlir-timing \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowPackedArrays,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \
--repl-seq-mem \ --repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--repl-seq-mem-circuit=$(MODEL) \ --repl-seq-mem-circuit=$(MODEL) \

3
conda-reqs/chipyard.yaml
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@@ -123,14 +123,13 @@ dependencies:
- botocore-stubs==1.24.7 - botocore-stubs==1.24.7
- mypy-boto3-s3==1.21.0 - mypy-boto3-s3==1.21.0
- sty==1.0.0 - sty==1.0.0
- sv2v
- pip - pip
- pip: - pip:
- fab-classic==1.19.1 - fab-classic==1.19.1
- mypy-boto3-ec2==1.21.9 - mypy-boto3-ec2==1.21.9
- sure==2.0.0 - sure==2.0.0
- pylddwrap==1.2.1 - pylddwrap==1.2.1
- hammer-vlsi - hammer-vlsi[asap7]
# doc requirements # doc requirements
- sphinx - sphinx

11
vlsi/Makefile
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@@ -80,17 +80,8 @@ $(VLSI_RTL): $(RTL_DEPS)
ifneq ($(CUSTOM_VLOG), ) ifneq ($(CUSTOM_VLOG), )
> $(VLSI_RTL) > $(VLSI_RTL)
$(foreach file,$^,echo $(file) >> $(VLSI_RTL)) $(foreach file,$^,echo $(file) >> $(VLSI_RTL))
else ifneq ($(CONVERT_SV2V), )
# Convert System Verilog to Verilog, uniquify, remove incompatible tasks
sv2v -w=adjacent --oversized-numbers \
-D=ASSERT_VERBOSE_COND=0 -D=STOP_COND=0 -D=PRINTF_COND=0 \
$(filter-out %.v,$(shell cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST)))
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u | sed 's/.sv/.v/g' > $(VLSI_RTL)
cat $(VLSI_RTL) | xargs sed -i 's/\$$fwrite.*/;/g'
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
else else
cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u | > $(VLSI_RTL) cat $(TOP_MODS_FILELIST) $(TOP_BB_MODS_FILELIST) | sort -u > $(VLSI_RTL)
echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL) echo $(TOP_SMEMS_FILE) >> $(VLSI_RTL)
echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL) echo $(build_dir)/EICG_wrapper.v >> $(VLSI_RTL)
endif endif

2
vlsi/tutorial.mk
View File

@@ -35,6 +35,4 @@ ifeq ($(tutorial),sky130-openroad)
VLSI_OBJ_DIR ?= build-sky130-openroad VLSI_OBJ_DIR ?= build-sky130-openroad
# This prevents multidimensional arrays (unsupported by Yosys) at the expense of elaboration time. # This prevents multidimensional arrays (unsupported by Yosys) at the expense of elaboration time.
#ENABLE_CUSTOM_FIRRTL_PASS = 1 #ENABLE_CUSTOM_FIRRTL_PASS = 1
# This runs sv2v for Yosys compatibility
CONVERT_SV2V = 1
endif endif