diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml index 0ed26ea6..d3088f4b 100644 --- a/.github/workflows/chipyard-run-tests.yml +++ b/.github/workflows/chipyard-run-tests.yml @@ -588,10 +588,10 @@ jobs: steps: - name: Delete old checkout run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . - name: Checkout uses: actions/checkout@v3 - name: Git workaround @@ -611,10 +611,10 @@ jobs: steps: - name: Delete old checkout run: | - ls -alh . - rm -rf ${{ github.workspace }}/* || true - rm -rf ${{ github.workspace }}/.* || true - ls -alh . + ls -alh . + rm -rf ${{ github.workspace }}/* || true + rm -rf ${{ github.workspace }}/.* || true + ls -alh . - name: Checkout uses: actions/checkout@v3 - name: Git workaround @@ -1043,9 +1043,9 @@ jobs: chipyard-ibex-run-tests, chipyard-sodor-run-tests, chipyard-dmirocket-run-tests, - chipyard-spiflashwrite-run-tests, chipyard-fftgenerator-run-tests, chipyard-spiflashread-run-tests, + chipyard-spiflashwrite-run-tests, chipyard-lbwif-run-tests, chipyard-sha3-run-tests, chipyard-streaming-fir-run-tests, diff --git a/common.mk b/common.mk index fe2d7e7b..701fdd38 100644 --- a/common.mk +++ b/common.mk @@ -1,7 +1,5 @@ -######################################################################################### -# set default shell for make -######################################################################################### SHELL=/bin/bash +SED ?= sed ifndef RISCV $(error RISCV is unset. Did you source the Chipyard auto-generated env file (which activates the default conda environment)?) @@ -13,14 +11,15 @@ endif # specify user-interface variables ######################################################################################### HELP_COMPILATION_VARIABLES += \ -" EXTRA_GENERATOR_REQS = additional make requirements needed for the main generator" \ -" EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ -" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ -" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ -" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ -" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ -" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ -" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" +" EXTRA_GENERATOR_REQS = additional make requirements needed for the main generator" \ +" EXTRA_SIM_CXXFLAGS = additional CXXFLAGS for building simulators" \ +" EXTRA_SIM_LDFLAGS = additional LDFLAGS for building simulators" \ +" EXTRA_SIM_SOURCES = additional simulation sources needed for simulator" \ +" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ +" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ +" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog) \ +" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ +" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS) EXTRA_SIM_CXXFLAGS ?= @@ -92,7 +91,7 @@ endif ######################################################################################### # copy over bootrom files ######################################################################################### -$(build_dir): +$(build_dir) $(OUT_DIR): mkdir -p $@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir) @@ -111,62 +110,145 @@ $(FIRRTL_FILE) $(ANNO_FILE) &: $(SCALA_SOURCES) $(sim_files) $(SCALA_BUILDTOOL_D --legacy-configs $(CONFIG_PACKAGE):$(CONFIG) \ $(EXTRA_CHISEL_OPTIONS)) +define mfc_extra_anno_contents +[ + { + "class":"sifive.enterprise.firrtl.MarkDUTAnnotation", + "target":"~$(MODEL)|$(TOP)" + }, + { + "class": "sifive.enterprise.firrtl.TestHarnessHierarchyAnnotation", + "filename": "$(MFC_MODEL_HRCHY_JSON)" + }, + { + "class": "sifive.enterprise.firrtl.ModuleHierarchyAnnotation", + "filename": "$(MFC_TOP_HRCHY_JSON)" + } +] +endef +export mfc_extra_anno_contents +$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE): $(ANNO_FILE) + echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE) + jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE) + .PHONY: firrtl -firrtl: $(FIRRTL_FILE) +firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) ######################################################################################### # create verilog files rules and variables ######################################################################################### -REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF) -HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF) +SFC_MFC_TARGETS = \ + $(MFC_SMEMS_CONF) \ + $(MFC_TOP_SMEMS_JSON) \ + $(MFC_TOP_HRCHY_JSON) \ + $(MFC_MODEL_HRCHY_JSON) \ + $(MFC_MODEL_SMEMS_JSON) \ + $(MFC_FILELIST) \ + $(MFC_BB_MODS_FILELIST) + +SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) -TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes) -HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes) # DOC include start: FirrtlCompiler -$(TOP_TARGETS) $(HARNESS_TARGETS) &: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) - $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,\ - --allow-unrecognized-annotations \ - --output-file $(TOP_FILE) \ - --harness-o $(HARNESS_FILE) \ +# There are two possible cases for this step. In the first case, SFC +# compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise, +# when custom FIRRTL transforms are included or if a Fixed type is used within +# the dut, SFC compiles Chisel to LowFIRRTL and MFC compiles it to Verilog. +# Users can indicate to the Makefile of custom FIRRTL transforms by setting the +# "ENABLE_CUSTOM_FIRRTL_PASS" variable. +# +# hack: lower to low firrtl if Fixed types are found +# hack: when using dontTouch, io.cpu annotations are not removed by SFC, +# hence we remove them manually by using jq before passing them to firtool +$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) +ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) + $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) + $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) +else + $(eval SFC_LEVEL := low) + $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) +endif + $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\ + --no-dedup \ + --output-file $(SFC_FIRRTL_BASENAME) \ + --output-annotation-file $(SFC_ANNO_FILE) \ + --target-dir $(OUT_DIR) \ --input-file $(FIRRTL_FILE) \ - --syn-top $(TOP) \ - --harness-top $(VLOG_MODEL) \ - --annotation-file $(ANNO_FILE) \ - --top-anno-out $(TOP_ANNO) \ - --top-dotf-out $(sim_top_blackboxes) \ - --top-fir $(TOP_FIR) \ - --harness-anno-out $(HARNESS_ANNO) \ - --harness-dotf-out $(sim_harness_blackboxes) \ - --harness-fir $(HARNESS_FIR) \ - $(REPL_SEQ_MEM) \ - $(HARNESS_CONF_FLAGS) \ - --target-dir $(build_dir) \ + --annotation-file $(FINAL_ANNO_FILE) \ --log-level $(FIRRTL_LOGLEVEL) \ + --allow-unrecognized-annotations \ + -X $(SFC_LEVEL) \ $(EXTRA_FIRRTL_OPTIONS)) - touch $(sim_top_blackboxes) $(sim_harness_blackboxes) + -mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL + @if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi + @if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json; fi + firtool \ + --format=fir \ + --dedup \ + --export-module-hierarchy \ + --emit-metadata \ + --verify-each=true \ + --warn-on-unprocessed-annotations \ + --disable-annotation-classless \ + --disable-annotation-unknown \ + --mlir-timing \ + --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,explicitBitcast,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ + --repl-seq-mem \ + --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ + --repl-seq-mem-circuit=$(MODEL) \ + --annotation-file=$(SFC_ANNO_FILE) \ + --split-verilog \ + -o $(OUT_DIR) \ + $(SFC_FIRRTL_FILE) + -mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF) + $(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler # DOC include end: FirrtlCompiler -# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs -MACROCOMPILER_MODE ?= --mode synflops -$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF) - $(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)) +$(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILELIST) &: $(MFC_MODEL_HRCHY_JSON) $(MFC_FILELIST) $(MFC_BB_MODS_FILELIST) + $(base_dir)/scripts/split-module-files.py \ + --model-hier-json $(MFC_MODEL_HRCHY_JSON) \ + --dut $(TOP) \ + --out-dut-filelist $(TOP_MODS_FILELIST) \ + --out-model-filelist $(MODEL_MODS_FILELIST) \ + --in-all-filelist $(MFC_FILELIST) \ + --target-dir $(OUT_DIR) + $(SED) -e 's;^;$(OUT_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST) + $(SED) -i 's/\.\///' $(TOP_MODS_FILELIST) + $(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST) + $(SED) -i 's/\.\///' $(BB_MODS_FILELIST) + sort -u $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(BB_MODS_FILELIST) > $(ALL_MODS_FILELIST) -HARNESS_MACROCOMPILER_MODE = --mode synflops -$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR) &: $(HARNESS_SMEMS_CONF) | $(TOP_SMEMS_FILE) - $(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)) +$(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &: $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JSON) + $(base_dir)/scripts/split-mems-conf.py \ + --in-smems-conf $(MFC_SMEMS_CONF) \ + --in-model-hrchy-json $(MFC_MODEL_HRCHY_JSON) \ + --dut-module-name $(TOP) \ + --model-module-name $(MODEL) \ + --out-dut-smems-conf $(TOP_SMEMS_CONF) \ + --out-model-smems-conf $(MODEL_SMEMS_CONF) + +# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs +TOP_MACROCOMPILER_MODE ?= --mode synflops +$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE)) + +MODEL_MACROCOMPILER_MODE = --mode synflops +$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE) + $(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE)) ######################################################################################## # remove duplicate files and headers in list of simulation file inputs ######################################################################################## -$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes) - sort -u $^ | grep -v '.*\.\(svh\|h\)$$' > $@ +$(sim_common_files): $(sim_files) $(ALL_MODS_FILELIST) $(TOP_SMEMS_FILE) $(MODEL_SMEMS_FILE) + sort -u $(sim_files) $(ALL_MODS_FILELIST) | grep -v '.*\.\(svh\|h\)$$' > $@ + echo "$(TOP_SMEMS_FILE)" >> $@ + echo "$(MODEL_SMEMS_FILE)" >> $@ ######################################################################################### # helper rule to just make verilog files ######################################################################################### .PHONY: verilog -verilog: $(sim_vsrcs) +verilog: $(sim_common_files) ######################################################################################### # helper rules to run simulations diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml index f750a966..87c2bf99 100644 --- a/conda-reqs/chipyard.yaml +++ b/conda-reqs/chipyard.yaml @@ -29,6 +29,7 @@ dependencies: - binutils - dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo + - firtool>=1.25 # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock # firemarshal deps - python>=3.8 @@ -61,6 +62,7 @@ dependencies: - lzop - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock + - jq - bash-completion - sbt - ca-certificates diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml index 512f5aa3..e4488fcf 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/buildbot/firesim/target-design/chipyard/conda-requirements-esp-tools.yaml -f /scratch/abejgonza/cy-fix/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-fix/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml +# conda-lock -f /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-circt/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -19,13 +19,12 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: 5075908599b7f10581bbf1452b4be082245ad6ac58a589e4d111d2ecd0f96b42 + linux-64: 46faccb4f0f152fc79912dbcd442a9cd0d3378720908f86cd06f3496fd584e06 platforms: - linux-64 sources: - - /scratch/buildbot/firesim/target-design/chipyard/conda-requirements-esp-tools.yaml - - /scratch/abejgonza/cy-fix/conda-reqs/chipyard.yaml - - /scratch/abejgonza/cy-fix/conda-reqs/esp-tools.yaml + - /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml + - /scratch/abejgonza/cy-circt/conda-reqs/esp-tools.yaml package: - category: main dependencies: {} @@ -821,6 +820,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/nettle-3.8.1-hc379101_1.tar.bz2 version: 3.8.1 +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 5be58359dbbf568c1ec0be87e0c6cb1b + sha256: f6c470ba56c43e5f6c75fd28b05256fd8f5d54d76df29c0652496bf3b104ae2b + manager: conda + name: oniguruma + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/oniguruma-6.9.8-h166bdaf_0.tar.bz2 + version: 6.9.8 - category: main dependencies: ca-certificates: '' @@ -846,19 +857,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/patch-2.7.6-h7f98852_1002.tar.bz2 version: 2.7.6 -- category: main - dependencies: - libgcc-ng: '>=9.3.0' - libstdcxx-ng: '>=9.3.0' - hash: - md5: c05d1820a6d34ff07aaaab7a9b7eddaa - sha256: 8f35c244b1631a4f31fb1d66ab6e1d9bfac0ca9b679deced1112c7225b3ad138 - manager: conda - name: pcre - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pcre-8.45-h9c3ff4c_0.tar.bz2 - version: '8.45' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1115,6 +1113,20 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/findutils-4.6.0-h7f98852_1001.tar.bz2 version: 4.6.0 +- category: main + dependencies: + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' + ncurses: '>=6.3,<7.0a0' + hash: + md5: f3530f0cfbc7b4e243cb6b8f19cd077d + sha256: null + manager: conda + name: firtool + optional: false + platform: linux-64 + url: https://anaconda.org/ucb-bar/firtool/1.25.0/download/linux-64/firtool-1.25.0-0_h1234567_gd0462e7ec.conda + version: 1.25.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1147,6 +1159,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/gcc_impl_linux-64-12.1.0-hea43390_16.tar.bz2 version: 12.1.0 +- category: main + dependencies: + libgcc-ng: '>=7.5.0' + oniguruma: '>=6.9.3,<6.10.0a0' + hash: + md5: 8578ae83310b8c9f5717f1aa65054f36 + sha256: 00e69aec19174e61c70b652bb62c77c0947a27d6720bda0cb8d5be654020804a + manager: conda + name: jq + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/jq-1.6-h36c2ea0_1000.tar.bz2 + version: '1.6' - category: main dependencies: libopenblas: '>=0.3.21,<1.0a0' @@ -1186,20 +1211,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libidn2-2.3.3-h166bdaf_0.tar.bz2 version: 2.3.3 -- category: main - dependencies: - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - hash: - md5: f5759f0c80708fbf9c4836c0cb46d0fe - sha256: af0f505053153cd2e8ad08a8559fb3df73b22ce8f635dbcaf7818a7bf916437f - manager: conda - name: libllvm14 - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm14-14.0.6-he0ac6c6_0.tar.bz2 - version: 14.0.6 - category: main dependencies: libgcc-ng: '>=12' @@ -1686,21 +1697,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libcblas-3.9.0-16_linux64_openblas.tar.bz2 version: 3.9.0 -- category: main - dependencies: - libgcc-ng: '>=12' - libllvm14: '>=14.0.6,<14.1.0a0' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - hash: - md5: 0e63ac182e381cd351c397f8e44a4b71 - sha256: 4e17513579284329f89f36b1e02ec9b7df01ec67f66f02c8b07ac15354477b1b - manager: conda - name: libclang-cpp14 - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp14-14.0.6-default_h2e3cab8_0.tar.bz2 - version: 14.0.6 - category: main dependencies: gettext: '>=0.19.8.1,<1.0a0' @@ -1879,22 +1875,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/atk-1.0-2.36.0-h3371d22_4.tar.bz2 version: 2.36.0 -- category: main - dependencies: - libclang-cpp14: '>=14.0.6,<14.1.0a0' - libgcc-ng: '>=12' - libllvm14: '>=14.0.6,<14.1.0a0' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - hash: - md5: ef9669b9847ce3c8a304e9eb08bf446d - sha256: 0c07d3ada12b27b0df8ea07faf4fa8c3b45cc791752a724ac86302af6378b4bb - manager: conda - name: clang-format-14 - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-14-14.0.6-default_h2e3cab8_0.tar.bz2 - version: 14.0.6 - category: main dependencies: expat: '>=2.4.2,<3.0a0' @@ -3045,14 +3025,14 @@ package: dependencies: python: '>=3.7' hash: - md5: a3508a0c850745b875de88aea4c40cc5 - sha256: bb6920451dad059ca31581ca6e36c5f1534fad8a8efe869c7eb9c9e3846b4f53 + md5: 6f3fd8c9e0ab504010fb4216d5919c24 + sha256: 7740d6fcd4fffb895a93c765388382b58ea78e005180cee88078eb18e59f7f06 manager: conda name: zipp optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.8.1-pyhd8ed1ab_0.tar.bz2 - version: 3.8.1 + url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.9.0-pyhd8ed1ab_0.tar.bz2 + version: 3.9.0 - category: main dependencies: python: '>=3.6' @@ -3249,22 +3229,22 @@ package: version: 3.2.3 - category: main dependencies: - cairo: '>=1.16.0,<2.0.0a0' + cairo: '>=1.16.0,<2.0a0' freetype: '>=2.12.1,<3.0a0' graphite2: '' icu: '>=70.1,<71.0a0' libgcc-ng: '>=12' - libglib: '>=2.72.1,<3.0a0' + libglib: '>=2.74.0,<3.0a0' libstdcxx-ng: '>=12' hash: - md5: 3c5f4fbd64c7254fbe246ca9d87863b6 - sha256: 4def14eb862e0b05ffce33edbfc2cfc4d0e1720f134d52e378c4b661467069cf + md5: 888056bd4b12e110b10d4d1f29161c5e + sha256: 57c6ae03c3e70fe7cd28b9e5f27ee470181aef5426f6796a52bc591cfe473183 manager: conda name: harfbuzz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-5.2.0-hf9f4e7c_0.tar.bz2 - version: 5.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-5.3.0-h418a68e_0.tar.bz2 + version: 5.3.0 - category: main dependencies: python: '' @@ -4308,17 +4288,17 @@ package: version: 5.10.0 - category: main dependencies: - cryptography: '>=35.0' + cryptography: '>=38.0.0,<39' python: '>=3.6' hash: - md5: 2e7e3630919d29c8216bfa2cd643d79e - sha256: 72af60a6164a380730c00ee996bda265267b53a99662d7ceb2ec6ed47dd74a0b + md5: fbfa0a180d48c800f922a10a114a8632 + sha256: 42f04dded77ac2597108378d62b121697d0e982aba7b20a462a7239030563628 manager: conda name: pyopenssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-22.0.0-pyhd8ed1ab_1.tar.bz2 - version: 22.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-22.1.0-pyhd8ed1ab_0.tar.bz2 + version: 22.1.0 - category: main dependencies: pytest: '>=3.6.0' @@ -4879,18 +4859,18 @@ package: pyyaml: '>=5.1' requests: '>=2' ruamel.yaml: '' - setuptools: '' - toml: '' + tomli: '' + toolz: <1.0.0,>=0.12.0 typing-extensions: '' hash: - md5: 2d1c6d733a45b168eef7acc6212109ed - sha256: 023ffdae76edde9f2d3fc6a8696cc8d8a60d61b2b8ae6d951f4e4802e47ef606 + md5: 496c81a0d226177dbabb5fa495fadda9 + sha256: 39b181da4620222ba831dc9570f600753c52bb8f649bfef036d2c79245a4c145 manager: conda name: conda-lock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/conda-lock-1.1.1-pyhd8ed1ab_0.tar.bz2 - version: 1.1.1 + url: https://conda.anaconda.org/conda-forge/noarch/conda-lock-1.1.3-pyhd8ed1ab_0.tar.bz2 + version: 1.1.3 - category: main dependencies: boto3: '' @@ -4919,14 +4899,14 @@ package: sarif-om: ~=1.0.4 six: '>=1.11' hash: - md5: 5f029952a7ac4f8e086219054e0d870b - sha256: 2f2e0d5aa9cc4c1e1939b7299ea922bd84290eb069c42eba29d7c134c7dde72e + md5: c0194acb049810fc8eba88a3184e570f + sha256: 7920575550b0a9bd75f2007c00ff53164f35e7aebe887117d7c24c626af05371 manager: conda name: cfn-lint optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.66.1-pyhd8ed1ab_0.tar.bz2 - version: 0.66.1 + url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.67.0-pyhd8ed1ab_0.tar.bz2 + version: 0.67.0 - category: main dependencies: aws-xray-sdk: '!=0.96,>=0.93' @@ -4965,14 +4945,14 @@ package: - category: main dependencies: {} hash: - sha256: bfb67f6a6c72dfb0a02f3df51550aa1862708e55128b22543e2b42c74f3620d7 + sha256: ae88eca3024bb34bb3430f964beab71226e761f51b912de5133470b649d82344 manager: pip name: bcrypt optional: false platform: linux-64 source: null - url: https://files.pythonhosted.org/packages/c5/77/14bbcd08ad265577ad6ea8e8980b9c0ad668cecfd241ae169b6747c4491b/bcrypt-4.0.0-cp36-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl - version: 4.0.0 + url: https://files.pythonhosted.org/packages/aa/48/fd2b197a9741fa790ba0b88a9b10b5e88e62ff5cf3e1bc96d8354d7ce613/bcrypt-4.0.1-cp36-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl + version: 4.0.1 - category: main dependencies: {} hash: diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml index 2caaf372..421d43a7 100644 --- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml +++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml @@ -9,7 +9,7 @@ # To update a single package to the latest version compatible with the version constraints in the source: # conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE # To re-solve the entire environment, e.g. after changing a version constraint in the source file: -# conda-lock -f /scratch/buildbot/firesim/target-design/chipyard/conda-requirements-riscv-tools.yaml -f /scratch/abejgonza/cy-fix/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-fix/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml +# conda-lock -f /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-circt/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml metadata: channels: - url: ucb-bar @@ -19,13 +19,12 @@ metadata: - url: nodefaults used_env_vars: [] content_hash: - linux-64: e0eaa8e6d532cfd33d97846ae17a35f71e62c135ff3edb6236f6d8d592b10e7a + linux-64: 18e98e3b7d2dbc99136ae91e74c8b58b0bab4248cd1e10da4626231a40700eb0 platforms: - linux-64 sources: - - /scratch/buildbot/firesim/target-design/chipyard/conda-requirements-riscv-tools.yaml - - /scratch/abejgonza/cy-fix/conda-reqs/chipyard.yaml - - /scratch/abejgonza/cy-fix/conda-reqs/riscv-tools.yaml + - /scratch/abejgonza/cy-circt/conda-reqs/chipyard.yaml + - /scratch/abejgonza/cy-circt/conda-reqs/riscv-tools.yaml package: - category: main dependencies: {} @@ -821,6 +820,18 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/nettle-3.8.1-hc379101_1.tar.bz2 version: 3.8.1 +- category: main + dependencies: + libgcc-ng: '>=12' + hash: + md5: 5be58359dbbf568c1ec0be87e0c6cb1b + sha256: f6c470ba56c43e5f6c75fd28b05256fd8f5d54d76df29c0652496bf3b104ae2b + manager: conda + name: oniguruma + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/oniguruma-6.9.8-h166bdaf_0.tar.bz2 + version: 6.9.8 - category: main dependencies: ca-certificates: '' @@ -846,19 +857,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/patch-2.7.6-h7f98852_1002.tar.bz2 version: 2.7.6 -- category: main - dependencies: - libgcc-ng: '>=9.3.0' - libstdcxx-ng: '>=9.3.0' - hash: - md5: c05d1820a6d34ff07aaaab7a9b7eddaa - sha256: 8f35c244b1631a4f31fb1d66ab6e1d9bfac0ca9b679deced1112c7225b3ad138 - manager: conda - name: pcre - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/pcre-8.45-h9c3ff4c_0.tar.bz2 - version: '8.45' - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1115,6 +1113,20 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/findutils-4.6.0-h7f98852_1001.tar.bz2 version: 4.6.0 +- category: main + dependencies: + libgcc-ng: '>=12' + libstdcxx-ng: '>=12' + ncurses: '>=6.3,<7.0a0' + hash: + md5: f3530f0cfbc7b4e243cb6b8f19cd077d + sha256: null + manager: conda + name: firtool + optional: false + platform: linux-64 + url: https://anaconda.org/ucb-bar/firtool/1.25.0/download/linux-64/firtool-1.25.0-0_h1234567_gd0462e7ec.conda + version: 1.25.0 - category: main dependencies: libgcc-ng: '>=7.5.0' @@ -1147,6 +1159,19 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/gcc_impl_linux-64-12.1.0-hea43390_16.tar.bz2 version: 12.1.0 +- category: main + dependencies: + libgcc-ng: '>=7.5.0' + oniguruma: '>=6.9.3,<6.10.0a0' + hash: + md5: 8578ae83310b8c9f5717f1aa65054f36 + sha256: 00e69aec19174e61c70b652bb62c77c0947a27d6720bda0cb8d5be654020804a + manager: conda + name: jq + optional: false + platform: linux-64 + url: https://conda.anaconda.org/conda-forge/linux-64/jq-1.6-h36c2ea0_1000.tar.bz2 + version: '1.6' - category: main dependencies: libopenblas: '>=0.3.21,<1.0a0' @@ -1186,20 +1211,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libidn2-2.3.3-h166bdaf_0.tar.bz2 version: 2.3.3 -- category: main - dependencies: - libgcc-ng: '>=12' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - hash: - md5: f5759f0c80708fbf9c4836c0cb46d0fe - sha256: af0f505053153cd2e8ad08a8559fb3df73b22ce8f635dbcaf7818a7bf916437f - manager: conda - name: libllvm14 - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libllvm14-14.0.6-he0ac6c6_0.tar.bz2 - version: 14.0.6 - category: main dependencies: libgcc-ng: '>=12' @@ -1686,21 +1697,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/libcblas-3.9.0-16_linux64_openblas.tar.bz2 version: 3.9.0 -- category: main - dependencies: - libgcc-ng: '>=12' - libllvm14: '>=14.0.6,<14.1.0a0' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - hash: - md5: 0e63ac182e381cd351c397f8e44a4b71 - sha256: 4e17513579284329f89f36b1e02ec9b7df01ec67f66f02c8b07ac15354477b1b - manager: conda - name: libclang-cpp14 - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/libclang-cpp14-14.0.6-default_h2e3cab8_0.tar.bz2 - version: 14.0.6 - category: main dependencies: gettext: '>=0.19.8.1,<1.0a0' @@ -1879,22 +1875,6 @@ package: platform: linux-64 url: https://conda.anaconda.org/conda-forge/linux-64/atk-1.0-2.36.0-h3371d22_4.tar.bz2 version: 2.36.0 -- category: main - dependencies: - libclang-cpp14: '>=14.0.6,<14.1.0a0' - libgcc-ng: '>=12' - libllvm14: '>=14.0.6,<14.1.0a0' - libstdcxx-ng: '>=12' - libzlib: '>=1.2.12,<1.3.0a0' - hash: - md5: ef9669b9847ce3c8a304e9eb08bf446d - sha256: 0c07d3ada12b27b0df8ea07faf4fa8c3b45cc791752a724ac86302af6378b4bb - manager: conda - name: clang-format-14 - optional: false - platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/clang-format-14-14.0.6-default_h2e3cab8_0.tar.bz2 - version: 14.0.6 - category: main dependencies: expat: '>=2.4.2,<3.0a0' @@ -3045,14 +3025,14 @@ package: dependencies: python: '>=3.7' hash: - md5: a3508a0c850745b875de88aea4c40cc5 - sha256: bb6920451dad059ca31581ca6e36c5f1534fad8a8efe869c7eb9c9e3846b4f53 + md5: 6f3fd8c9e0ab504010fb4216d5919c24 + sha256: 7740d6fcd4fffb895a93c765388382b58ea78e005180cee88078eb18e59f7f06 manager: conda name: zipp optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.8.1-pyhd8ed1ab_0.tar.bz2 - version: 3.8.1 + url: https://conda.anaconda.org/conda-forge/noarch/zipp-3.9.0-pyhd8ed1ab_0.tar.bz2 + version: 3.9.0 - category: main dependencies: python: '>=3.6' @@ -3231,22 +3211,22 @@ package: version: 3.2.3 - category: main dependencies: - cairo: '>=1.16.0,<2.0.0a0' + cairo: '>=1.16.0,<2.0a0' freetype: '>=2.12.1,<3.0a0' graphite2: '' icu: '>=70.1,<71.0a0' libgcc-ng: '>=12' - libglib: '>=2.72.1,<3.0a0' + libglib: '>=2.74.0,<3.0a0' libstdcxx-ng: '>=12' hash: - md5: 3c5f4fbd64c7254fbe246ca9d87863b6 - sha256: 4def14eb862e0b05ffce33edbfc2cfc4d0e1720f134d52e378c4b661467069cf + md5: 888056bd4b12e110b10d4d1f29161c5e + sha256: 57c6ae03c3e70fe7cd28b9e5f27ee470181aef5426f6796a52bc591cfe473183 manager: conda name: harfbuzz optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-5.2.0-hf9f4e7c_0.tar.bz2 - version: 5.2.0 + url: https://conda.anaconda.org/conda-forge/linux-64/harfbuzz-5.3.0-h418a68e_0.tar.bz2 + version: 5.3.0 - category: main dependencies: python: '' @@ -4308,17 +4288,17 @@ package: version: 5.10.0 - category: main dependencies: - cryptography: '>=35.0' + cryptography: '>=38.0.0,<39' python: '>=3.6' hash: - md5: 2e7e3630919d29c8216bfa2cd643d79e - sha256: 72af60a6164a380730c00ee996bda265267b53a99662d7ceb2ec6ed47dd74a0b + md5: fbfa0a180d48c800f922a10a114a8632 + sha256: 42f04dded77ac2597108378d62b121697d0e982aba7b20a462a7239030563628 manager: conda name: pyopenssl optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-22.0.0-pyhd8ed1ab_1.tar.bz2 - version: 22.0.0 + url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-22.1.0-pyhd8ed1ab_0.tar.bz2 + version: 22.1.0 - category: main dependencies: pytest: '>=3.6.0' @@ -4879,18 +4859,18 @@ package: pyyaml: '>=5.1' requests: '>=2' ruamel.yaml: '' - setuptools: '' - toml: '' + tomli: '' + toolz: <1.0.0,>=0.12.0 typing-extensions: '' hash: - md5: 2d1c6d733a45b168eef7acc6212109ed - sha256: 023ffdae76edde9f2d3fc6a8696cc8d8a60d61b2b8ae6d951f4e4802e47ef606 + md5: 496c81a0d226177dbabb5fa495fadda9 + sha256: 39b181da4620222ba831dc9570f600753c52bb8f649bfef036d2c79245a4c145 manager: conda name: conda-lock optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/conda-lock-1.1.1-pyhd8ed1ab_0.tar.bz2 - version: 1.1.1 + url: https://conda.anaconda.org/conda-forge/noarch/conda-lock-1.1.3-pyhd8ed1ab_0.tar.bz2 + version: 1.1.3 - category: main dependencies: boto3: '' @@ -4919,14 +4899,14 @@ package: sarif-om: ~=1.0.4 six: '>=1.11' hash: - md5: 5f029952a7ac4f8e086219054e0d870b - sha256: 2f2e0d5aa9cc4c1e1939b7299ea922bd84290eb069c42eba29d7c134c7dde72e + md5: c0194acb049810fc8eba88a3184e570f + sha256: 7920575550b0a9bd75f2007c00ff53164f35e7aebe887117d7c24c626af05371 manager: conda name: cfn-lint optional: false platform: linux-64 - url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.66.1-pyhd8ed1ab_0.tar.bz2 - version: 0.66.1 + url: https://conda.anaconda.org/conda-forge/noarch/cfn-lint-0.67.0-pyhd8ed1ab_0.tar.bz2 + version: 0.67.0 - category: main dependencies: aws-xray-sdk: '!=0.96,>=0.93' @@ -4965,14 +4945,14 @@ package: - category: main dependencies: {} hash: - sha256: bfb67f6a6c72dfb0a02f3df51550aa1862708e55128b22543e2b42c74f3620d7 + sha256: ae88eca3024bb34bb3430f964beab71226e761f51b912de5133470b649d82344 manager: pip name: bcrypt optional: false platform: linux-64 source: null - url: https://files.pythonhosted.org/packages/c5/77/14bbcd08ad265577ad6ea8e8980b9c0ad668cecfd241ae169b6747c4491b/bcrypt-4.0.0-cp36-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl - version: 4.0.0 + url: https://files.pythonhosted.org/packages/aa/48/fd2b197a9741fa790ba0b88a9b10b5e88e62ff5cf3e1bc96d8354d7ce613/bcrypt-4.0.1-cp36-abi3-manylinux_2_17_x86_64.manylinux2014_x86_64.whl + version: 4.0.1 - category: main dependencies: {} hash: diff --git a/conda-requirements-riscv-tools.yaml b/conda-requirements-riscv-tools.yaml new file mode 100644 index 00000000..bbc06729 --- /dev/null +++ b/conda-requirements-riscv-tools.yaml @@ -0,0 +1,134 @@ +channels: + - ucb-bar + - conda-forge + - nodefaults + +dependencies: + # https://conda-forge.org/feedstock-outputs/ + # filterable list of all conda-forge packages + # https://conda-forge.org/#contribute + # instructions on adding a recipe + # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications + # documentation on package_spec syntax for constraining versions + + + # handy tool for introspecting package relationships and file ownership + # see https://github.com/rvalieris/conda-tree + - conda-tree + + # bundle FireSim driver with deps into installer shell-script + - constructor + + - gcc + - gxx + - sysroot_linux-64>=2.17 # needed to match pre-built CI XRT glibc version + - conda-gcc-specs + - binutils + + - dromajo # from ucb-bar channel - https://github.com/riscv-boom/dromajo + - riscv-tools # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock + - firtool # from ucb-bar channel - https://github.com/ucb-bar/firtool-feedstock + + # firemarshal deps + - python>=3.8 + - bc + - patch + - which + - diffutils + - bash + - gzip + - bzip2 + - perl + - tar + - file + - findutils + - rsync + - psutil + - doit=0.35.0 + - gitpython + - humanfriendly + - e2fsprogs + - ctags + - bison + - flex + - expat + - make + - pyyaml + - unzip + - readline + - coreutils + - lzop + - qemu # from ucb-bar channel - https://github.com/ucb-bar/qemu-feedstock + + - jq + - bash-completion + - sbt + - ca-certificates + - mosh + - gmp + - mpfr + - mpc + - zlib + - vim + - git + - openjdk + - gengetopt + - libffi + - expat + - libusb1 + - ncurses + - cmake + - graphviz + - expect + - dtc + - verilator==4.226 + - screen + - elfutils + - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock + - conda-lock>=1 + - wget + - sed + - autoconf + + # clang-format for driver coding style enforcement. + - clang-format + - clang-tools + + # python packages + # While it is possible to install using pip after creating the + # conda environment, pip's dependency resolution can conflict with + # conda and create broken environments. It's best to use the conda + # packages so that the environment is consistent + - boto3==1.20.21 + - colorama==0.4.3 + - argcomplete==1.12.3 + - python-graphviz==0.19 + - pyparsing==3.0.6 + - numpy==1.19.5 + - kiwisolver==1.3.1 + - matplotlib-base==3.3.4 + - pandas==1.1.5 + - awscli==1.22.21 + - pytest==6.2.5 + - pytest-dependency==0.5.1 + - pytest-mock==3.7.0 + - moto==3.1.0 + - pyyaml==5.4.1 + - mypy==0.931 + - types-pyyaml==6.0.4 + - boto3-stubs==1.21.6 + - botocore-stubs==1.24.7 + - mypy-boto3-s3==1.21.0 + - pip + - pip: + - fab-classic==1.19.1 + - mypy-boto3-ec2==1.21.9 + - sure==2.0.0 + - pylddwrap==1.2.1 + + # doc requirements + - sphinx + - pygments + - sphinx-autobuild + - sphinx_rtd_theme + - docutils diff --git a/docs/VLSI/Basic-Flow.rst b/docs/VLSI/Basic-Flow.rst index 610f6958..6f7c456b 100644 --- a/docs/VLSI/Basic-Flow.rst +++ b/docs/VLSI/Basic-Flow.rst @@ -64,7 +64,7 @@ As in the rest of the Chipyard flows, we specify our SoC configuration using the However, unlike the rest of the Chipyard flows, in the case of physical design we might be interested in working in a hierarchical fashion and therefore we would like to work on a single module. Therefore, we can also specify a ``VLSI_TOP`` make variable with the same of a specific Verilog module (which should also match the name of the equivalent Chisel module) which we would like to work on. The makefile will automatically call tools such as Barstools and the MacroCompiler (:ref:`Tools/Barstools:barstools`) in order to make the generated Verilog more VLSI friendly. -By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). +By default, the MacroCompiler will attempt to map memories into the SRAM options within the Hammer technology plugin. However, if you are working with a new process technology and prefer to work with flip-flop arrays, you can configure the MacroCompiler using the ``TOP_MACROCOMPILER_MODE`` make variable. For example, if your technology plugin does not have an SRAM compiler ready, you can use the ``MACROCOMPILER_MODE='--mode synflops'`` option (Note that synthesizing a design with only flipflops is very slow and will often may not meet constraints). We call the ``make buildfile`` command while also specifying the name of the process technology we are working with (same ``tech_name`` for the configuration files and plugin name) and the configuration files we created. Note, in the ASAP7 tutorial ((:ref:`tutorial`)) these configuration files are merged into a single file called ``example-asap7.yml``. diff --git a/fpga/Makefile b/fpga/Makefile index be059e65..d037833b 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -94,13 +94,13 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v # copy files but ignore *.h files in *.f (match vcs) -$(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) +$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) + cp -f $^ $(OUT_DIR) $(foreach file,\ $^,\ $(if $(filter %.h,$(file)),\ ,\ - echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) ######################################################################################### # import other necessary rules and variables @@ -111,8 +111,8 @@ include $(base_dir)/common.mk # copy from other directory ######################################################################################### all_vsrcs := \ - $(sim_vsrcs) \ - $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v + $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \ + $(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v ######################################################################################### # vivado rules diff --git a/generators/gemmini b/generators/gemmini index b6bdad59..6f57972d 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit b6bdad59cbd6313f1ea4c93d3493db3d59b9e418 +Subproject commit 6f57972db9b0815462cc0569f922792f83e35c5d diff --git a/generators/ibex b/generators/ibex index 0eac465e..a5214d0a 160000 --- a/generators/ibex +++ b/generators/ibex @@ -1 +1 @@ -Subproject commit 0eac465e3e9e06eceba111b4b43d5178ede817c2 +Subproject commit a5214d0a0a6351dc2e03930750f831b0f28df8bf diff --git a/generators/riscv-sodor b/generators/riscv-sodor index fc56b712..510dea74 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit fc56b7128f8d5fd3d9022e19ee53c93e0ecfad05 +Subproject commit 510dea7407d8bca5eef18175530ffffa8e0774ce diff --git a/generators/testchipip b/generators/testchipip index c298a281..70cdc3f0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c298a2814816d85a29c48e7a5d85b810bdcb2b2b +Subproject commit 70cdc3f0206453aa9cbb76ba9619b87d7e10266a diff --git a/scripts/split-mems-conf.py b/scripts/split-mems-conf.py new file mode 100755 index 00000000..f772060e --- /dev/null +++ b/scripts/split-mems-conf.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 + +import os +import json +import argparse +import sys +from typing import List, Optional + +# Schema of json emitted by circt +""" +{ + "module_name": "mem_ext", + "depth": 512, + "width": 64, + "masked": true, + "read": false, + "write": false, + "readwrite": true, + "mask_granularity": 8, + "extra_ports": [], + "hierarchy": [ + "TestHarness.ram.srams.mem.mem_ext" + ] +} +""" + +sys.setrecursionlimit(100) + +def bfs_find_root(tree, module_name): + q = [tree] + + while len(q) != 0: + front = q[0] + q.pop(0) + + if front['module_name'] == module_name: + return front + for c in front['instances']: + q.append(c) + return None + + +def bfs_collect_submodules(tree): + output = set() + q = [(tree['instance_name'], tree['module_name'], tree['instances'])] + + while len(q) != 0: + front = q[0] + q.pop(0) + + (inst, mod, child) = front + output.add(mod) + for c in child: + q.append((c['instance_name'], c['module_name'], c['instances'])) + return output + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='Use MFC(FIRTOOL) generated model-hrchy JSONs to create smems confs for the DUT and TestHarness') + parser.add_argument('--in-smems-conf', type=str, required=True, help='Overall smems conf file that contains all memory definitions') + parser.add_argument('--in-model-hrchy-json', type=str, required=True, help='JSON indicating which mem modules are in the DUT') + parser.add_argument('--dut-module-name', type=str, required=True, help='Module name of the DUT') + parser.add_argument('--model-module-name', type=str, required=True, help='Module name of the model') + parser.add_argument('--out-dut-smems-conf', type=str, required=True, help='Smems conf with only DUT mem module definitions') + parser.add_argument('--out-model-smems-conf', type=str, required=True, help='Smems conf with only top-most level mem module definitions (not including DUT modules)') + args = parser.parse_args() + + with open(args.in_smems_conf) as isc, \ + open(args.in_model_hrchy_json) as imhj: + imhj_data = json.load(imhj) + + dut_root = bfs_find_root(imhj_data, args.dut_module_name) + dut_submodules = bfs_collect_submodules(dut_root) + + model_root = bfs_find_root(imhj_data, args.model_module_name) + model_submodules = bfs_collect_submodules(model_root) + + with open(args.out_dut_smems_conf, "w") as odsc, \ + open(args.out_model_smems_conf, "w") as otsc: + for l in isc: + sl = l.split() + + # the line can't be split then stop immediately (normally an empty file) + if len(sl) > 2: + name = sl[1] + + if name in dut_submodules: + odsc.write(l) + elif name in model_submodules: + otsc.write(l) + else: + assert False, "Unable to find smem CONF module in MFC(FIRTOOL) emitted JSON files." + else: + exit(0) diff --git a/scripts/split-module-files.py b/scripts/split-module-files.py new file mode 100755 index 00000000..64fe5707 --- /dev/null +++ b/scripts/split-module-files.py @@ -0,0 +1,111 @@ +#!/usr/bin/env python3 + +import json +import argparse +from typing import List, Optional + +# Schema of json emitted by circt +""" +{ + "instance_name": "TestHarness", + "module_name": "TestHarness", + "instances": [ + { + "instance_name": "chiptop", + "module_name": "ChipTop", + "instances": [ + { + "instance_name": "system", + "module_name": "DigitalTop", + "instances": [ ] + }, ... + ] + }, + { + "instance_name": "simdram", + "module_name": "SimDRAM", + "instances": [] + }, + ] +} +""" + +def get_modules(js: dict) -> List[str]: + if 'instances' not in js: + return js['module_name'] + else: + mods = [] + for mod in js['instances']: + mods.extend(get_modules(mod)) + return [js['module_name']] + mods + +def find_mod_by_name(js: dict, name: str) -> Optional[List[dict]]: + if 'instances' not in js: + return None + else: + mods = [] + for mod in js['instances']: + if mod['module_name'] == name: + mods.append(mod) + other_mods = find_mod_by_name(mod, name) + if other_mods is not None: + mods.extend(other_mods) + return mods + +if __name__ == "__main__": + parser = argparse.ArgumentParser(description='Convert CIRCT (firtool) hierarchy JSON into DUT and test harness filelists') + parser.add_argument('--model-hier-json', type=str, required=True, help='Path to hierarchy JSON emitted by firtool. Must include DUT as a module.') + parser.add_argument('--dut', type=str, required=True, help='Name of the DUT module.') + parser.add_argument('--out-dut-filelist', type=str, required=True, help='Path to output filelist including all modules under the DUT.') + parser.add_argument('--out-model-filelist', type=str, required=True, help='Path to output filelist including all modules under the top-most module but not modules under the DUT.') + parser.add_argument('--in-all-filelist', type=str, required=True, help='Path to input filelist that has all modules (relative paths).') + parser.add_argument('--target-dir', type=str, required=True, help='Path to where module sources are located (combined with --in-all-filelist gives the absolute path to module sources).') + args = parser.parse_args() + + with open(args.model_hier_json) as f: + j = json.load(f) + + dut_tops = find_mod_by_name(j, args.dut) + assert dut_tops is not None + assert len(dut_tops) == 1 + dut_top = dut_tops[0] + + dut_mods = set(get_modules(dut_top)) + model_mods = set(get_modules(j)) - dut_mods + both_mods = dut_mods.intersection(model_mods) + + assert len(both_mods) == 0 + + with open(args.out_dut_filelist, 'w') as df, \ + open(args.in_all_filelist) as fl: + # add paths that correspond to modules to output file + for path in fl: + writeOut = False + for dm in dut_mods: + if dm in path: + writeOut = True + break + + # prepend the target directory to get filelist with absolute paths + if writeOut: + if not args.target_dir in path: + df.write(f"{args.target_dir}/{path}") + else: + df.write(f"{path}") + + with open(args.out_model_filelist, 'w') as df, \ + open(args.in_all_filelist) as fl: + # add paths that correspond to modules to output file + for path in fl: + writeOut = False + for dm in model_mods: + if dm in path: + writeOut = True + break + + # prepend the target directory to get filelist with absolute paths + if writeOut: + if not args.target_dir in path: + df.write(f"{args.target_dir}/{path}") + else: + df.write(f"{path}") diff --git a/sims/common-sim-flags.mk b/sims/common-sim-flags.mk index 6cf3c761..cf974f92 100644 --- a/sims/common-sim-flags.mk +++ b/sims/common-sim-flags.mk @@ -9,7 +9,7 @@ SIM_CXXFLAGS = \ -std=c++17 \ -I$(RISCV)/include \ -I$(dramsim_dir) \ - -I$(build_dir) \ + -I$(OUT_DIR) \ $(EXTRA_SIM_CXXFLAGS) SIM_LDFLAGS = \ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 550be3c2..d407fe4f 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -32,19 +32,19 @@ default: $(sim) debug: $(sim_debug) ######################################################################################### -# simulaton requirements +# simulation requirements ######################################################################################### SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) +$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) + cp -f $^ $(OUT_DIR) $(foreach file,\ $^,\ $(if $(filter %.h,$(file)),\ ,\ - echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) ######################################################################################### # import other necessary rules and variables @@ -67,11 +67,11 @@ model_dir_debug = $(build_dir)/$(long_name).debug ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) +$(sim): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf $(model_dir) $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir) -$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) +$(sim_debug): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) $(VCS) $(VCS_OPTS) $(EXTRA_SIM_SOURCES) -o $@ -Mdir=$(model_dir_debug) \ +define+DEBUG -debug_access+all -kdb -lca diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index a1186acc..5c15973a 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -50,7 +50,7 @@ SIM_FILE_REQS += \ $(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \ $(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \ -# the following files are needed for emulator.cc to compile +# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build) SIM_FILE_REQS += \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \ $(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \ @@ -66,13 +66,13 @@ SIM_FILE_REQS += \ $(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc # copy files and add -FI for *.h files in *.f -$(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) +$(sim_files): $(SIM_FILE_REQS) | $(OUT_DIR) + cp -f $^ $(OUT_DIR) $(foreach file,\ $^,\ $(if $(filter %.h,$(file)),\ - echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\ - echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + echo "-FI $(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;,\ + echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;)) ######################################################################################### # import other necessary rules and variables @@ -143,7 +143,7 @@ CHIPYARD_VERILATOR_FLAGS := \ # options dependent on whether external IP (cva6/NVDLA) or just chipyard is used # NOTE: defer the evaluation of this until it is used! PLATFORM_OPTS = $(shell \ - if grep -qiP "module\s+(CVA6|NVDLA)" $(build_dir)/*.*v; \ + if grep -qiP "module\s+(CVA6|NVDLA)" $(OUT_DIR)/*.*v; \ then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \ else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi) @@ -168,8 +168,7 @@ VERILATOR_NONCC_OPTS = \ $(PREPROC_DEFINES) \ --top-module $(VLOG_MODEL) \ --vpi \ - -f $(sim_common_files) \ - $(sim_vsrcs) + -f $(sim_common_files) #---------------------------------------------------------------------------------------- # gcc configuration/optimization @@ -182,7 +181,7 @@ VERILATOR_CXXFLAGS = \ -DTEST_HARNESS=V$(VLOG_MODEL) \ -DVERILATOR \ -include $(build_dir)/$(long_name).plusArgs \ - -include $(build_dir)/verilator.h + -include $(OUT_DIR)/verilator.h VERILATOR_LDFLAGS = $(SIM_LDFLAGS) @@ -210,13 +209,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### -$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) +$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir) mkdir -p $(model_dir) $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) +$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(model_dir_debug) mkdir -p $(model_dir_debug) $(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" diff --git a/tools/barstools b/tools/barstools index 064c8be7..06db6059 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 064c8be7bb3d86eccfd603c614f74de6de1c3f4a +Subproject commit 06db6059022c55df8e6943702653798c43ead3d8 diff --git a/variables.mk b/variables.mk index 22848145..fab54a6a 100644 --- a/variables.mk +++ b/variables.mk @@ -143,22 +143,47 @@ ifeq ($(GENERATOR_PACKAGE),hwacha) long_name=$(MODEL_PACKAGE).$(CONFIG) endif +# chisel generated outputs FIRRTL_FILE ?= $(build_dir)/$(long_name).fir ANNO_FILE ?= $(build_dir)/$(long_name).anno.json -TOP_FILE ?= $(build_dir)/$(long_name).top.v -TOP_FIR ?= $(build_dir)/$(long_name).top.fir -TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json -TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).top.mems.v -TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf -TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir +# chisel anno modification output +MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json +FINAL_ANNO_FILE ?= $(build_dir)/$(long_name).appended.anno.json -HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v -HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir -HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json -HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v -HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf -HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir +# scala firrtl compiler (sfc) outputs +SFC_FIRRTL_BASENAME ?= $(build_dir)/$(long_name).sfc +SFC_FIRRTL_FILE ?= $(SFC_FIRRTL_BASENAME).fir +SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json + +# firtool compiler outputs +MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json +MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json +MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf +# hardcoded firtool outputs +MFC_FILELIST = $(OUT_DIR)/filelist.f +MFC_BB_MODS_FILELIST = $(OUT_DIR)/firrtl_black_box_resource_files.f +MFC_TOP_SMEMS_JSON = $(OUT_DIR)/metadata/seq_mems.json +MFC_MODEL_SMEMS_JSON = $(OUT_DIR)/metadata/tb_seq_mems.json + +# macrocompiler smems in/output +SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf +TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf +TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v +TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir +MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf +MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v +MODEL_SMEMS_FIR ?= $(build_dir)/$(long_name).model.mems.fir + +# top module files to include +TOP_MODS_FILELIST ?= $(build_dir)/$(long_name).top.f +# model module files to include (not including top modules) +MODEL_MODS_FILELIST ?= $(build_dir)/$(long_name).model.f +# list of all blackbox files (may be included in the top/model.f files) +# this has the build_dir appended +BB_MODS_FILELIST ?= $(build_dir)/$(long_name).bb.f +# all module files to include (top, model, bb included) +ALL_MODS_FILELIST ?= $(build_dir)/$(long_name).all.f BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) @@ -166,8 +191,6 @@ BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES)) # files that contain lists of files needed for VCS or Verilator simulation SIM_FILE_REQS = sim_files ?= $(build_dir)/sim_files.f -sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f -sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's) sim_common_files ?= $(build_dir)/sim_files.common.f @@ -192,8 +215,6 @@ SBT_CLIENT_FLAG = --client endif # passes $(JAVA_TOOL_OPTIONS) from env to java -# Use java -jar approach by default so that SBT thin-client sees the JAVA flags -# Workaround for behavior reported here: https://github.com/sbt/sbt/issues/6468 SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG) SBT_NON_THIN = $(subst $(SBT_CLIENT_FLAG),,$(SBT)) @@ -228,22 +249,12 @@ binary_hex= $(sim_out_name).loadmem_hex ######################################################################################### # build output directory for compilation ######################################################################################### +# output for all project builds gen_dir=$(sim_dir)/generated-src +# per-project output directory build_dir=$(gen_dir)/$(long_name) - -######################################################################################### -# vsrcs needed to run projects -######################################################################################### -rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc - -######################################################################################### -# sources needed to run simulators -######################################################################################### -sim_vsrcs = \ - $(TOP_FILE) \ - $(HARNESS_FILE) \ - $(TOP_SMEMS_FILE) \ - $(HARNESS_SMEMS_FILE) +# final generated collateral per-project +OUT_DIR ?= $(build_dir)/gen-collateral ######################################################################################### # assembly/benchmark variables diff --git a/vcs.mk b/vcs.mk index 6b5eb80b..002fd09a 100644 --- a/vcs.mk +++ b/vcs.mk @@ -51,8 +51,7 @@ VCS_NONCC_OPTS = \ -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ -debug_pp \ - +incdir+$(build_dir) \ - $(sim_vsrcs) + +incdir+$(OUT_DIR) PREPROC_DEFINES = \ +define+VCS \ diff --git a/vlsi/Makefile b/vlsi/Makefile index 0df1f7f9..228401b2 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -28,9 +28,9 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json ifdef USE_SRAM_COMPILER - MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict + TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict + TOP_MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict endif ENV_YML ?= $(vlsi_dir)/env.yml @@ -121,12 +121,12 @@ SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk -$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) +$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ @@ -163,7 +163,7 @@ ifneq ($(BINARY), ) endif echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ -$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) mkdir -p $(output_dir) echo "sim.inputs:" > $@ @@ -186,7 +186,7 @@ else echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ endif -$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " defines: ['NTC']" >> $@ @@ -195,7 +195,7 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_comm POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk -$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) +$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) mkdir -p $(dir $@) echo "power.inputs:" > $@ echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@