From 2de5f7dd7e245ad3f47cbfa69a68b925c38df3af Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 15:48:50 -0800 Subject: [PATCH] [ci skip] Note that CVA6 was called Ariane in the past --- README.md | 2 +- docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- docs/Generators/CVA6.rst | 2 +- sims/firesim | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 11f1b8d5..0283da58 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 4ad39d51..398b537d 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -21,7 +21,7 @@ Processor Cores See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. **CVA6 Core** - An in-order RISC-V core written in System Verilog. + An in-order RISC-V core written in System Verilog. Previously called Ariane. See :ref:`CVA6 Core` for more information. Accelerators diff --git a/docs/Generators/CVA6.rst b/docs/Generators/CVA6.rst index 6250c614..bfca746a 100644 --- a/docs/Generators/CVA6.rst +++ b/docs/Generators/CVA6.rst @@ -1,7 +1,7 @@ CVA6 Core ==================================== -`CVA6 `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +`CVA6 `__ (previously called Ariane) is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. The `CVA6 core` is wrapped in an `CVA6 tile` so it can be used as a component within the `Rocket Chip SoC generator`. The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. diff --git a/sims/firesim b/sims/firesim index 57efb2ec..37fe89a6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 57efb2ec032a8c7afa2f458761cc79b2614180b5 +Subproject commit 37fe89a65f1c1ccd8d2cc0d1efd0c06308d0224d