change dir structure

2019-03-07 14:18:24 -08:00
parent 17c38a502a
commit 2def0dfea7
11 changed files with 17 additions and 17 deletions
--- a/sims/verisim/.gitignore
+++ b/sims/verisim/.gitignore
@@ -0,0 +1,3 @@
+!.gitignore
+!Makefile
+!Makefrag-verilator
--- a/sims/verisim/Makefile
+++ b/sims/verisim/Makefile
@@ -0,0 +1,89 @@
+base_dir=$(abspath ../..)
+sim_dir=$(abspath .)
+
+PROJECT ?= example
+MODEL ?= TestHarness
+CONFIG ?= DefaultExampleConfig
+CFG_PROJECT ?= $(PROJECT)
+TB ?= TestDriver
+TOP ?= ExampleTop
+
+sim_name = verilator
+
+sim = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)
+sim_debug = $(sim_dir)/simulator-$(PROJECT)-$(CONFIG)-debug
+
+default: $(sim)
+
+debug: $(sim_debug)
+
+CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
+LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
+
+include $(base_dir)/Makefrag
+include $(sim_dir)/Makefrag-verilator
+ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
+-include $(build_dir)/$(long_name).d
+endif
+
+sim_blackboxes = \
+  $(build_dir)/firrtl_black_box_resource_files.f
+
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+
+sim_vsrcs = \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE)
+
+model_dir = $(build_dir)/$(long_name)
+model_dir_debug = $(build_dir)/$(long_name).debug
+
+model_header = $(model_dir)/V$(MODEL).h
+model_header_debug = $(model_dir_debug)/V$(MODEL).h
+
+model_mk = $(model_dir)/V$(MODEL).mk
+model_mk_debug = $(model_dir_debug)/V$(MODEL).mk
+
+$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
+	rm -rf $(build_dir)/$(long_name)
+	mkdir -p $(build_dir)/$(long_name)
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
+	-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
+	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
+	touch $@
+
+$(sim): $(model_mk)
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
+
+
+$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
+	rm -rf $(build_dir)/$(long_name)
+	mkdir -p $(build_dir)/$(long_name).debug
+	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
+	-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_blackboxes) -LDFLAGS "$(LDFLAGS)" \
+	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
+	touch $@
+
+$(sim_debug): $(model_mk_debug)
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk
+
+$(output_dir)/%.out: $(output_dir)/% $(sim)
+	$(sim) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
+
+$(output_dir)/%.run: $(output_dir)/% $(sim)
+	$(sim) +max-cycles=1000000 $< && touch $@
+
+$(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
+	rm -f $@.vcd && mkfifo $@.vcd
+	vcd2vpd $@.vcd $@ > /dev/null &
+	$(sim_debug) -v$@.vcd +max-cycles=1000000 $<
+
+run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
+
+run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
+
+run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
+
+clean: clean-scala
+	rm -rf generated-src ./simulator-*
--- a/sims/verisim/Makefrag-verilator
+++ b/sims/verisim/Makefrag-verilator
@@ -0,0 +1,34 @@
+# Build and install our own Verilator, to work around versionining issues.
+VERILATOR_VERSION=3.920
+VERILATOR_SRCDIR=verilator/src/verilator-$(VERILATOR_VERSION)
+INSTALLED_VERILATOR=$(abspath verilator/install/bin/verilator)
+$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator
+	$(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata
+	touch $@
+
+$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile
+	$(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin
+	touch $@
+
+$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure
+	mkdir -p $(dir $@)
+	cd $(dir $@) && ./configure --prefix=$(abspath verilator/install)
+
+$(VERILATOR_SRCDIR)/configure: verilator/verilator-$(VERILATOR_VERSION).tar.gz
+	rm -rf $(dir $@)
+	mkdir -p $(dir $@)
+	cat $^ | tar -xz --strip-components=1 -C $(dir $@)
+	touch $@
+
+verilator/verilator-$(VERILATOR_VERSION).tar.gz:
+	mkdir -p $(dir $@)
+	wget http://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
+
+# Run Verilator to produce a fast binary to emulate this circuit.
+VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
+VERILATOR_FLAGS := --top-module $(MODEL) \
+	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
+	--output-split 20000 \
+	-Wno-STMTDLY --x-assign unique \
+	-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(MODEL) -DVERILATOR"
--- a/sims/vsim/.gitignore
+++ b/sims/vsim/.gitignore
@@ -0,0 +1,2 @@
+!Makefile
+!.gitignore
--- a/sims/vsim/Makefile
+++ b/sims/vsim/Makefile
@@ -0,0 +1,84 @@
+base_dir=$(abspath ../..)
+sim_dir=$(abspath .)
+
+PROJECT ?= example
+MODEL ?= TestHarness
+CONFIG ?= DefaultExampleConfig
+CFG_PROJECT ?= $(PROJECT)
+TB ?= TestDriver
+TOP ?= ExampleTop
+
+sim_name = vcs
+
+simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
+simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
+
+default: $(simv)
+
+debug: $(simv_debug)
+
+include $(base_dir)/Makefrag
+ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
+-include $(build_dir)/$(long_name).d
+endif
+
+sim_blackboxes = \
+  $(build_dir)/firrtl_black_box_resource_files.f
+
+rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
+
+sim_vsrcs = \
+	$(VERILOG_FILE) \
+	$(HARNESS_FILE) \
+	$(SMEMS_FILE)
+
+VCS = vcs -full64
+
+VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
+	+rad +v2k +vcs+lic+wait \
+	+vc+list -CC "-I$(VCS_HOME)/include" \
+	-CC "-I$(RISCV)/include" \
+	-CC "-std=c++11" \
+	-CC "-Wl,-rpath,$(RISCV)/lib" \
+	-f $(sim_blackboxes) -f $(sim_dotf) \
+	$(RISCV)/lib/libfesvr.so \
+	-sverilog \
+	+incdir+$(generated_dir) \
+	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) \
+	+define+PRINTF_COND=$(TB).printf_cond \
+	+define+STOP_COND=!$(TB).reset \
+	+define+RANDOMIZE_MEM_INIT \
+	+define+RANDOMIZE_REG_INIT \
+	+define+RANDOMIZE_GARBAGE_ASSIGN \
+	+define+RANDOMIZE_INVALID_ASSIGN \
+	+libext+.v \
+
+verilog: $(sim_vsrcs)
+
+$(simv): $(sim_vsrcs) $(sim_dotf)
+	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	-debug_pp
+
+$(simv_debug) : $(sim_vsrcs) $(sim_dotf)
+	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
+	+define+DEBUG -debug_pp
+
+$(output_dir)/%.out: $(output_dir)/% $(simv)
+	$(simv) +verbose +max-cycles=1000000 $< 3>&1 1>&2 2>&3 | spike-dasm > $@
+
+$(output_dir)/%.run: $(output_dir)/% $(simv)
+	$(simv) +max-cycles=1000000 $< && touch $@
+
+$(output_dir)/%.vpd: $(output_dir)/% $(simv_debug)
+	$(simv_debug) +vcdplusfile=$@ +max-cycles=1000000 $<
+
+run-regression-tests: $(addprefix $(output_dir)/,$(addsuffix .out,$(regression-tests)))
+
+run-regression-tests-fast: $(addprefix $(output_dir)/,$(addsuffix .run,$(regression-tests)))
+
+run-regression-tests-debug: $(addprefix $(output_dir)/,$(addsuffix .vpd,$(regression-tests)))
+
+clean:
+	rm -rf generated-src csrc simv-* ucli.key vc_hdrs.h
+
+.PHONY: clean