diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index be016e6a..c20abca1 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -38,16 +38,22 @@ class FireSimClockBridgeInstantiator extends HarnessClockInstantiator {
 
     var instantiatedClocks = LinkedHashMap[Int, (Clock, Seq[String])]()
     // connect wires to clock source
-    for ((name, (freq, clock)) <- clockMap) {
-      val freqMHz = (freq / (1000 * 1000)).toInt
+    def findOrInstantiate(freqMHz: Int, name: String): Clock = {
       if (!instantiatedClocks.contains(freqMHz)) {
         val clock = Wire(Clock())
         instantiatedClocks(freqMHz) = (clock, Seq(name))
       } else {
         instantiatedClocks(freqMHz) = (instantiatedClocks(freqMHz)._1, instantiatedClocks(freqMHz)._2 :+ name)
       }
-      clock := instantiatedClocks(freqMHz)._1
+      instantiatedClocks(freqMHz)._1
     }
+    for ((name, (freq, clock)) <- clockMap) {
+      val freqMHz = (freq / (1000 * 1000)).toInt
+      clock := findOrInstantiate(freqMHz, name)
+    }
+
+    // The undivided reference clock as calculated by pllConfig must be instantiated
+    findOrInstantiate(pllConfig.referenceFreqMHz.toInt, "reference")
 
     val ratClocks = instantiatedClocks.map { case (freqMHz, (clock, names)) =>
       (RationalClock(names.mkString(","), 1, pllConfig.referenceFreqMHz.toInt / freqMHz), clock)
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index b6d6766e..c27abd50 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -103,11 +103,15 @@ class WithFireSimDesignTweaks extends Config(
 
 // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
 class WithFireSimHighPerfClocking extends Config(
+  // Create clock group for uncore that does not include mbus
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Nil)) ++
   // Optional: This sets the default frequency for all buses in the system to 3.2 GHz
   // (since unspecified bus frequencies will use the pbus frequency)
   // This frequency selection matches FireSim's legacy selection and is required
   // to support 200Gb NIC performance. You may select a smaller value.
   new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
+  new chipyard.config.WithSystemBusFrequency(3200.0) ++
+  new chipyard.config.WithFrontBusFrequency(3200.0) ++
   // Optional: These three configs put the DRAM memory system in it's own clock domain.
   // Removing the first config will result in the FASED timing model running
   // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.