From 309bfde21e98b12e6ca5d07cdec6c0dc6082829d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Jun 2023 15:27:59 -0700 Subject: [PATCH] [ci skip] add more comments to ShuttleConfigs --- .../src/main/scala/config/ShuttleConfigs.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala index 6e86e020..10220bdb 100644 --- a/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ShuttleConfigs.scala @@ -7,13 +7,13 @@ import org.chipsalliance.cde.config.{Config} //----------------- class ShuttleConfig extends Config( - new shuttle.common.WithNShuttleCores ++ + new shuttle.common.WithNShuttleCores ++ // 1x dual-issue shuttle core new chipyard.config.AbstractConfig) class ShuttleCosimConfig extends Config( new chipyard.harness.WithCospike ++ // attach spike-cosim - new chipyard.config.WithTraceIO ++ - new shuttle.common.WithShuttleDebugROB ++ + new chipyard.config.WithTraceIO ++ // enable trace-io for cosim + new shuttle.common.WithShuttleDebugROB ++ // enable shuttle debug ROB for cosim new shuttle.common.WithNShuttleCores ++ new chipyard.config.AbstractConfig) @@ -21,8 +21,8 @@ class dmiShuttleCosimConfig extends Config( new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl new chipyard.harness.WithCospike ++ // attach spike-cosim new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port - new chipyard.config.WithTraceIO ++ - new shuttle.common.WithShuttleDebugROB ++ + new chipyard.config.WithTraceIO ++ // enable traceio for cosim + new shuttle.common.WithShuttleDebugROB ++ // enable shuttle debug ROB for cosim new shuttle.common.WithNShuttleCores ++ new chipyard.config.AbstractConfig)