From 9a5b67bf8c3a65e67cacd24616730f3c406c2ba1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 20:30:49 -0800 Subject: [PATCH 1/2] Use Chipyard configs as a base (VCU118) --- fpga/src/main/scala/vcu118/Configs.scala | 28 ++++++++----------- .../main/scala/vcu118/bringup/Configs.scala | 13 +++++---- .../scala/vcu118/bringup/TestHarness.scala | 2 +- .../main/scala/config/AbstractConfig.scala | 2 +- 4 files changed, 21 insertions(+), 24 deletions(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f55c9520..aee3c489 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -15,6 +15,8 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.fpgashells.shell.{DesignKey} import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} +import testchipip.{SerialTLKey} + import chipyard.{BuildSystem} class WithDefaultPeripherals extends Config((site, here, up) => { @@ -45,10 +47,11 @@ class WithSystemModifications extends Config((site, here, up) => { require (make.! == 0, "Failed to build bootrom") p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin") } - case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size + case SerialTLKey => None // remove serialized tl port }) -class AbstractVCU118Config extends Config( +class WithVCU118Tweaks extends Config( new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ @@ -56,27 +59,18 @@ class AbstractVCU118Config extends Config( new WithSPIIOPassthrough ++ new WithTLIOPassthrough ++ new WithDefaultPeripherals ++ - new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size + new WithSystemModifications ++ // remove debug module, setup busses, use sdboot bootrom, setup ext. mem. size, use new dig. top new freechips.rocketchip.subsystem.WithoutTLMonitors ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new chipyard.WithMulticlockCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(1)) class RocketVCU118Config extends Config( - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new AbstractVCU118Config) + new WithVCU118Tweaks ++ + new chipyard.RocketConfig) class BoomVCU118Config extends Config( new WithFPGAFrequency(75) ++ - new boom.common.WithNLargeBooms(1) ++ - new AbstractVCU118Config) + new WithVCU118Tweaks ++ + new chipyard.MegaBoomConfig) class WithFPGAFrequency(MHz: Double) extends Config((site, here, up) => { case FPGAFrequencyKey => MHz diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index fc5df5a1..133d2ae2 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -15,7 +15,7 @@ import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import chipyard.{BuildSystem} -import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config} +import chipyard.fpga.vcu118.{WithVCU118Tweaks, WithFPGAFrequency} class WithBringupPeripherals extends Config((site, here, up) => { case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L))) @@ -51,9 +51,12 @@ class WithBringupAdditions extends Config( new WithBringupVCU118System) class RocketBringupConfig extends Config( - new WithBringupPeripherals ++ - new RocketVCU118Config) + new WithBringupAdditions ++ + new WithVCU118Tweaks ++ + new chipyard.RocketConfig) class BoomBringupConfig extends Config( - new WithBringupPeripherals ++ - new BoomVCU118Config) + new WithFPGAFrequency(75) ++ + new WithBringupAdditions ++ + new WithVCU118Tweaks ++ + new chipyard.MegaBoomConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 080f6189..8a4ae8fc 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -68,5 +68,5 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends } class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) { - val bringupOuter = _outer + lazy val bringupOuter = _outer } diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 301c03d7..b1e873d1 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -49,6 +49,6 @@ class AbstractConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system From b0fc0457aa63073b10b86d4cccb21e45d428fc8c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 20:44:48 -0800 Subject: [PATCH 2/2] Use Chipyard configs as base (Arty) --- fpga/src/main/scala/arty/Configs.scala | 29 +++++++------------ fpga/src/main/scala/arty/HarnessBinders.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 4 +++ 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index 11cf0260..bc62bcf9 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -11,6 +11,8 @@ import freechips.rocketchip.tile._ import sifive.blocks.devices.uart._ +import testchipip.{SerialTLKey} + import chipyard.{BuildSystem} class WithDefaultPeripherals extends Config((site, here, up) => { @@ -22,29 +24,20 @@ class WithDefaultPeripherals extends Config((site, here, up) => { idcodePartNum = 0x000, idcodeManufId = 0x489, debugIdleCycles = 5) + case SerialTLKey => None // remove serialized tl port }) -class TinyRocketArtyConfig extends Config( +class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ new WithArtyResetHarnessBinder ++ - new chipyard.iobinders.WithDebugIOCells ++ - new chipyard.iobinders.WithUARTIOCells ++ new WithResetPassthrough ++ new WithDefaultPeripherals ++ - new chipyard.config.WithNoSubsystemDrivenClocks ++ - new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.With1TinyCore ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ + new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithIncoherentBusTopology) + +class TinyRocketArtyConfig extends Config( + new WithArtyTweaks ++ + new chipyard.TinyRocketConfig) diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 408d2b7d..464d054a 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -59,7 +59,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({ } }) -class WithArtyUARTHarnessBinder extends chipyard.harness.OverrideHarnessBinder({ +class WithArtyUARTHarnessBinder extends OverrideHarnessBinder({ (system: HasPeripheryUARTModuleImp, th: ArtyFPGATestHarness, ports: Seq[UARTPortIO]) => { withClockAndReset(th.clock_32MHz, th.ck_rst) { IOBUF(th.uart_txd_in, ports.head.txd) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index d413cc12..626700a5 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -10,6 +10,10 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new chipyard.config.AbstractConfig) +class TinyRocketConfig extends Config( + new freechips.rocketchip.subsystem.With1TinyCore ++ // single tiny rocket-core + new chipyard.config.AbstractConfig) + class HwachaRocketConfig extends Config( new chipyard.config.WithHwachaTest ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator