From 0225ab7b5159bfe0b7d9487c6919c316f98cb5a6 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 28 Jan 2020 15:35:18 -0800 Subject: [PATCH 01/50] bump sifive-cache for updated gitignore (#411) --- generators/sifive-cache | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sifive-cache b/generators/sifive-cache index f5a09e28..d3d95ece 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit f5a09e289b92e53039d74114140d0380032ad8b4 +Subproject commit d3d95ece5a570b423892bede4fed6cb0030c7701 From 14c4c62eeae6d65c2f3c1a6304994dbaa0527a70 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Tue, 28 Jan 2020 16:38:44 -0800 Subject: [PATCH 02/50] [ci-skip] Gitignore generated env-riscv-tools.sh (#414) * Gitignore generated {env,esp}-riscv-tools.sh [ci-skip] --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 7c1463a4..e2c66082 100644 --- a/.gitignore +++ b/.gitignore @@ -15,3 +15,5 @@ riscv-tools-install esp-tools-install tags *~ +env-riscv-tools.sh +env-esp-tools.sh From b8104904210af0e65ff6ec456f24a5c8711c3836 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 28 Jan 2020 16:39:39 -0800 Subject: [PATCH 03/50] [example] fix multi-rocc boom+rocket+hwacha config (#413) --- generators/example/src/main/scala/HeteroConfigs.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/example/src/main/scala/HeteroConfigs.scala index d68532ad..ff3bf338 100644 --- a/generators/example/src/main/scala/HeteroConfigs.scala +++ b/generators/example/src/main/scala/HeteroConfigs.scala @@ -92,7 +92,8 @@ class DualLargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new WithMultiRoCC ++ // support heterogeneous rocc - new WithMultiRoCCHwacha(2) ++ // put hwacha on hart-2 (rocket) + new WithMultiRoCCHwacha(2) ++ // override: put hwacha on hart-2 (rocket) + new hwacha.DefaultHwachaConfig ++ // setup hwacha on all harts new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(2) ++ From 5d27ac5bbc12047ab379fa16f4e27015d24f7dfa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 30 Jan 2020 10:08:53 -0800 Subject: [PATCH 04/50] [sim] Pipe /dev/null to simulators to fix VCS messing up stdout (#417) --- common.mk | 12 ++++++------ sims/vcs/Makefile | 2 +- sims/verilator/Makefile | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/common.mk b/common.mk index 2259bb40..1fd7a193 100644 --- a/common.mk +++ b/common.mk @@ -102,19 +102,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -126,10 +126,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< | tee $<.log) && touch $@ + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator @@ -149,7 +149,7 @@ $(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh cd $(AXE_DIR) && ./make.sh $(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none 2> $@ + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) $(base_dir)/scripts/check-tracegen.sh $< > $@ diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index f9bb8ca9..86c28f23 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -91,7 +91,7 @@ $(sim_debug) : $(sim_vsrcs) $(sim_common_files) ######################################################################################### .PRECIOUS: $(output_dir)/%.vpd %.vpd $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< 2> >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 364d68fd..caaba672 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -110,7 +110,7 @@ $(sim_debug): $(model_mk_debug) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< 2> >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule From 59dd6a79ff00a25c681ef26953fb3c4ea589f5e1 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 30 Jan 2020 15:26:00 -0800 Subject: [PATCH 05/50] [firechip] Enable trace by default in BOOM-based targets (#412) * [firechip] Enable trace by default in BOOM-based targets * Bump boom for trace enchancements --- generators/boom | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 5 +++++ generators/firechip/src/main/scala/TargetMixins.scala | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index a88fe70c..1d4d0cda 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit a88fe70c81c33fb4773d52a529633029fa6eb9af +Subproject commit 1d4d0cda50969a0c46f1807cc7b2201bbf42a6f3 diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 17ac06e6..ed2a86c5 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -80,6 +80,10 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { )) }) +class WithBoomEnableTrace extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) +}) + // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -176,6 +180,7 @@ class FireSimBoomConfig extends Config( new WithNICKey ++ new WithSerial ++ new WithBlockDevice ++ + new WithBoomEnableTrace ++ new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index c3982d95..be93bb7a 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -45,7 +45,7 @@ trait HasTraceIOImp extends LazyModuleImp { // Enabled to test TracerV trace capture if (p(PrintTracePort)) { val traceprint = Wire(UInt(512.W)) - traceprint := Cat(traceIO.traces.map(_.asUInt)) + traceprint := Cat(traceIO.traces.map(_.reverse.asUInt)) printf("TRACEPORT: %x\n", traceprint) } } From 3e4c99e044cb548a7cc8db75d0a0437f182c2655 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 4 Feb 2020 18:33:08 -0800 Subject: [PATCH 06/50] [ci] use re-usable config. components (#421) --- .circleci/config.yml | 832 ++++++++++++------------------------------- 1 file changed, 221 insertions(+), 611 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 9fbb2958..8a1fdb48 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -1,16 +1,142 @@ # CircleCI Configuration File # version of circleci -version: 2 +version: 2.1 -# set of jobs to run -jobs: - commit-on-master-check: +parameters: + verilator-cache-version: + type: string + default: "v3" + tools-cache-version: + type: string + default: "v4" + +# default execution env.s +executors: + main-env: docker: - image: riscvboom/riscvboom-images:0.0.12 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + +# re-usable commands +commands: + toolchain-build: + description: "Build a toolchain" + parameters: + tools-version: + type: string + default: "riscv-tools" + steps: + - checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} + - run: + name: Building << parameters.tools-version >> + command: | + .circleci/build-toolchains.sh << parameters.tools-version >> + no_output_timeout: 120m + - save_cache: + key: << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} + paths: + - "/home/riscvuser/<< parameters.tools-version >>-install" + + ssh-checkout: + description: "Add SSH key and checkout code" + steps: + - add_ssh_keys: + fingerprints: + - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" + - checkout + + setup-tools-verilator: + description: "Get toolchain and verilator" + parameters: + tools-version: + type: string + default: "riscv-tools" + steps: + - ssh-checkout + - run: + name: Create hash of toolchains + command: | + .circleci/create-hash.sh + - restore_cache: + keys: + - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} + - restore_cache: + keys: + - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} + + prepare-rtl: + description: "Run the prepare step of RTL" + parameters: + tools-version: + type: string + default: "riscv-tools" + project-key: + type: string + timeout: + type: string + default: "120m" + build-script: + type: string + default: "do-rtl-build.sh" + steps: + - setup-tools-verilator: + tools-version: "<< parameters.tools-version >>" + - run: + name: Building << parameters.project-key >> subproject using Verilator + command: .circleci/<< parameters.build-script >> << parameters.project-key >> + no_output_timeout: << parameters.timeout >> + - save_cache: + key: << parameters.project-key >>-{{ .Branch }}-{{ .Revision }} + paths: + - "/home/riscvuser/project" + + run-tests: + description: "Run a set of tests" + parameters: + tools-version: + type: string + default: "riscv-tools" + project-key: + type: string + extra-cache-restore: + type: string + default: "" + run-script: + type: string + default: "run-tests.sh" + timeout: + type: string + default: "10m" + steps: + - setup-tools-verilator: + tools-version: "<< parameters.tools-version >>" + - restore_cache: + keys: + - << parameters.project-key >>-{{ .Branch }}-{{ .Revision }} + - when: + condition: << parameters.extra-cache-restore >> + steps: + - restore_cache: + keys: + - << parameters.extra-cache-restore >>-{{ .Branch }}-{{ .Revision }} + - run: + name: Run << parameters.project-key >> subproject tests + command: .circleci/<< parameters.run-script >> << parameters.project-key >> + no_output_timeout: << parameters.timeout >> + +# set of jobs to run +jobs: + commit-on-master-check: + executor: main-env steps: - checkout - run: @@ -18,94 +144,42 @@ jobs: command: | .circleci/check-commit.sh install-riscv-toolchain: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - run: - name: Building riscv-tools toolchain - command: | - .circleci/build-toolchains.sh riscv-tools - no_output_timeout: 120m - - save_cache: - key: riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - paths: - - "/home/riscvuser/riscv-tools-install" + - toolchain-build: + tools-version: "riscv-tools" install-esp-toolchain: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - esp-tools-installed-v4-{{ checksum "../esp-tools.hash" }} - - run: - name: Building esp-tools toolchain - command: | - .circleci/build-toolchains.sh esp-tools - no_output_timeout: 120m - - save_cache: - key: esp-tools-installed-v4-{{ checksum "../esp-tools.hash" }} - paths: - - "/home/riscvuser/esp-tools-install" + - toolchain-build: + tools-version: "esp-tools" install-verilator: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout + - ssh-checkout - restore_cache: keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} + - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} - run: name: Build Verilator command: | .circleci/build-verilator.sh no_output_timeout: 120m - save_cache: - key: verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} + key: verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} paths: - "/home/riscvuser/verilator" build-extra-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout + - ssh-checkout - run: name: Create hash of toolchains command: | .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../riscv-tools.hash" }} - run: name: Build extra tests command: .circleci/build-extra-tests.sh @@ -115,593 +189,129 @@ jobs: paths: - "/home/riscvuser/project/tests" prepare-example: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the example subproject using Verilator - command: .circleci/do-rtl-build.sh example - no_output_timeout: 120m - - save_cache: - key: example-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "example" prepare-boomrocketexample: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the boomrocketexample subproject using Verilator - command: .circleci/do-rtl-build.sh boomrocketexample - no_output_timeout: 240m - - save_cache: - key: boomrocketexample-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "boomrocketexample" + timeout: "240m" prepare-boom: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the boom subproject using Verilator - command: .circleci/do-rtl-build.sh boom - no_output_timeout: 120m - - save_cache: - key: boom-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "boom" prepare-rocketchip: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the rocketchip subproject using Verilator - command: .circleci/do-rtl-build.sh rocketchip - no_output_timeout: 120m - - save_cache: - key: rocketchip-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "rocketchip" prepare-blockdevrocketchip: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the blockdevrocketchip subproject using Verilator - command: .circleci/do-rtl-build.sh blockdevrocketchip - no_output_timeout: 120m - - save_cache: - key: blockdevrocketchip-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "blockdevrocketchip" prepare-hwacha: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - esp-tools-installed-v4-{{ checksum "../esp-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh hwacha - no_output_timeout: 120m - - save_cache: - key: hwacha-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + tools-version: "esp-tools" + project-key: "hwacha" prepare-gemmini: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - esp-tools-installed-v4-{{ checksum "../esp-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the gemmini subproject using Verilator - command: .circleci/do-rtl-build.sh gemmini - no_output_timeout: 120m - - save_cache: - key: gemmini-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + tools-version: "esp-tools" + project-key: "gemmini" prepare-tracegen: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the tracegen subproject using Verilator - command: .circleci/do-rtl-build.sh tracegen - no_output_timeout: 120m - - save_cache: - key: tracegen-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "tracegen" prepare-tracegen-boom: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building the tracegen-boom subproject using Verilator - command: .circleci/do-rtl-build.sh tracegen-boom - no_output_timeout: 120m - - save_cache: - key: tracegen-boom-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "tracegen-boom" prepare-firesim: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building FireSim MIDAS simulator using Verilator - command: .circleci/do-firesim-build.sh firesim - no_output_timeout: 120m - - save_cache: - key: firesim-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "firesim" + build-script: "do-firesim-build.sh" prepare-fireboom: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - add_ssh_keys: - fingerprints: - - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Building FireSim MIDAS simulator using Verilator - command: .circleci/do-firesim-build.sh fireboom - no_output_timeout: 120m - - save_cache: - key: fireboom-{{ .Branch }}-{{ .Revision }} - paths: - - "/home/riscvuser/project" + - prepare-rtl: + project-key: "fireboom" + build-script: "do-firesim-build.sh" midasexamples-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} + - setup-tools-verilator - run: name: Run midasexamples tests command: .circleci/run-midasexamples-tests.sh example-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - example-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run example tests - command: .circleci/run-tests.sh example + - run-tests: + project-key: "example" boomrocketexample-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - boomrocketexample-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run boomrocketexample tests - command: .circleci/run-tests.sh boomrocketexample + - run-tests: + project-key: "boomrocketexample" boom-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - boom-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run boom tests - command: .circleci/run-tests.sh boom + - run-tests: + project-key: "boom" rocketchip-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - rocketchip-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run rocketchip tests - command: .circleci/run-tests.sh rocketchip + - run-tests: + project-key: "rocketchip" hwacha-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - esp-tools-installed-v4-{{ checksum "../esp-tools.hash" }} - - restore_cache: - keys: - - hwacha-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run hwacha tests - command: .circleci/run-tests.sh hwacha + - run-tests: + tools-version: "esp-tools" + project-key: "hwacha" gemmini-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - esp-tools-installed-v4-{{ checksum "../esp-tools.hash" }} - - restore_cache: - keys: - - gemmini-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run gemmini tests - command: .circleci/run-tests.sh gemmini + - run-tests: + tools-version: "esp-tools" + project-key: "gemmini" tracegen-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - tracegen-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run tracegen tests - command: .circleci/run-tests.sh tracegen + - run-tests: + project-key: "tracegen" tracegen-boom-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - tracegen-boom-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run tracegen-boom tests - command: .circleci/run-tests.sh tracegen-boom + - run-tests: + project-key: "tracegen-boom" firesim-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - firesim-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - extra-tests-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run FireSim tests - command: .circleci/run-firesim-tests.sh firesim + - run-tests: + extra-cache-restore: "extra-tests" + project-key: "firesim" + run-script: "run-firesim-tests.sh" fireboom-run-tests: - docker: - - image: riscvboom/riscvboom-images:0.0.12 - environment: - JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit - TERM: dumb + executor: main-env steps: - - checkout - - run: - name: Create hash of toolchains - command: | - .circleci/create-hash.sh - - restore_cache: - keys: - - riscv-tools-installed-v4-{{ checksum "../riscv-tools.hash" }} - - restore_cache: - keys: - - fireboom-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - extra-tests-{{ .Branch }}-{{ .Revision }} - - restore_cache: - keys: - - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} - - run: - name: Run FireSim tests - command: .circleci/run-firesim-tests.sh fireboom - no_output_timeout: 20m - + - run-tests: + extra-cache-restore: "extra-tests" + project-key: "fireboom" + run-script: "run-firesim-tests.sh" + timeout: "20m" # Order and dependencies of jobs to run workflows: From aae93ad065bb26d7f2209f973ee4f6e40827fb2d Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 6 Feb 2020 10:08:58 -0800 Subject: [PATCH 07/50] bump boom with rocc/lsu exu fix (#425) * bump boom with rocc/lsu exu fix --- generators/boom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/boom b/generators/boom index 1d4d0cda..779c62c5 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 1d4d0cda50969a0c46f1807cc7b2201bbf42a6f3 +Subproject commit 779c62c5634847b517be64c554af66829de40067 From ccd6ecd41867ca11d262425a3606eeb5a31451bb Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 9 Feb 2020 17:58:56 -0800 Subject: [PATCH 08/50] Marhsal in chipyard (#415) * Move firemarshal into chipyard (was in firesim) --- .gitmodules | 3 +++ scripts/build-toolchains.sh | 2 +- scripts/init-submodules-no-riscv-tools.sh | 14 ++++++++++++-- sims/firesim | 2 +- software/firemarshal | 2 +- 5 files changed, 18 insertions(+), 5 deletions(-) mode change 120000 => 160000 software/firemarshal diff --git a/.gitmodules b/.gitmodules index d514a4e9..c4a9b2b9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -110,3 +110,6 @@ [submodule "generators/gemmini"] path = generators/gemmini url = https://github.com/ucb-bar/gemmini +[submodule "software/firemarshal"] + path = software/firemarshal + url = https://github.com/firesim/FireMarshal.git diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index d5d181e7..27c87417 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -141,5 +141,5 @@ cd "$RDIR" } > env-$TOOLCHAIN.sh # create general env.sh -ln -sf env-$TOOLCHAIN.sh env.sh +echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]}") )/env-$TOOLCHAIN.sh" >> env.sh echo "Toolchain Build Complete!" diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 67e74e99..ef77374e 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -23,6 +23,7 @@ git config submodule.sims/firesim.update none git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none +git config submodule.software/firemarshal.update none git submodule update --init --recursive #--jobs 8 # Un-ignore toolchain submodules @@ -37,6 +38,8 @@ git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update git config --unset submodule.generators/sha3.update +git config --unset submodule.software/firemarshal.update + # Non-recursive clone to exclude riscv-linux git submodule update --init generators/sha3 @@ -47,7 +50,14 @@ git submodule update --init sims/firesim cd sims/firesim # Initialize dependencies for MIDAS-level RTL simulation git submodule update --init sim/midas - # Exclude riscv-linux - git submodule update --init sw/firesim-software ) git config submodule.sims/firesim.update none + +# Only shallow clone needed for basic SW tests +git submodule update --init software/firemarshal + +# Configure firemarshal to know where our firesim installation is +if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then + echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml +fi +echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh diff --git a/sims/firesim b/sims/firesim index b4951f25..c377a5f4 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b4951f2589114e3849c77c798982afd10fc11b3e +Subproject commit c377a5f4a13f95c91a2d5e6ef6c1fc45f5041deb diff --git a/software/firemarshal b/software/firemarshal deleted file mode 120000 index c1e20e80..00000000 --- a/software/firemarshal +++ /dev/null @@ -1 +0,0 @@ -../sims/firesim/sw/firesim-software/ \ No newline at end of file diff --git a/software/firemarshal b/software/firemarshal new file mode 160000 index 00000000..ef2d467f --- /dev/null +++ b/software/firemarshal @@ -0,0 +1 @@ +Subproject commit ef2d467fe214d4d5294681ee8a3b25c3f470ea6b From cf9a52c052bcc7cec18193e57b3628f6ab738a9c Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Mon, 10 Feb 2020 02:14:32 +0000 Subject: [PATCH 09/50] bump firemarshal --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index ef2d467f..c614142f 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit ef2d467fe214d4d5294681ee8a3b25c3f470ea6b +Subproject commit c614142f85e29cfac93b251b761147a53d3a10ec From 7004bfdba35f23b86013e72bceda2486bd8bbabd Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Tue, 11 Feb 2020 00:55:05 +0000 Subject: [PATCH 10/50] bump to firemarshal dev --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index c614142f..ef69bde3 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit c614142f85e29cfac93b251b761147a53d3a10ec +Subproject commit ef69bde3b3fe7b233ac91e16aca3b955b6eff438 From 074add1d2c007951b0c96d617e39695aa0696416 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Wed, 12 Feb 2020 22:36:02 +0000 Subject: [PATCH 11/50] bump to firesim with support for TracerV + Stack unwinding + Flame Graphs --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index c377a5f4..52aee63b 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c377a5f4a13f95c91a2d5e6ef6c1fc45f5041deb +Subproject commit 52aee63bc04c3769695a41ba18319e316c2e78d5 From 49dbe8daba0c051b8e5dc82ed8758289bff116bb Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 22 Jan 2020 12:38:38 -0800 Subject: [PATCH 12/50] Rename top-level example package to chipyard * FireChip now directly uses the Chipyard Top --- .circleci/config.yml | 105 +++++++----------- .circleci/defaults.sh | 12 +- .circleci/do-rtl-build.sh | 2 +- .circleci/run-tests.sh | 19 ++-- build.sbt | 7 +- .../src/main/resources/vsrc/GCDMMIOBlackBox.v | 0 .../src/main/scala/BoomConfigs.scala | 2 +- .../src/main/scala/ConfigMixins.scala | 2 +- .../src/main/scala/GCD.scala | 2 +- .../src/main/scala/Generator.scala | 4 +- .../src/main/scala/HeteroConfigs.scala | 2 +- .../src/main/scala/InitZero.scala | 2 +- .../src/main/scala/NodeTypes.scala | 2 +- .../src/main/scala/RegisterNodeExample.scala | 0 .../src/main/scala/RocketConfigs.scala | 2 +- .../src/main/scala/Subsystem.scala | 2 +- .../src/main/scala/System.scala | 2 +- .../src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/TestSuites.scala | 2 +- .../src/main/scala/Top.scala | 4 +- .../src/main/scala/TopCakes.scala | 2 +- .../firechip/src/main/scala/Generator.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 2 + .../src/main/scala/TargetMixins.scala | 2 +- .../firechip/src/main/scala/Targets.scala | 44 +------- variables.mk | 6 +- 26 files changed, 82 insertions(+), 151 deletions(-) rename generators/{example => chipyard}/src/main/resources/vsrc/GCDMMIOBlackBox.v (100%) rename generators/{example => chipyard}/src/main/scala/BoomConfigs.scala (99%) rename generators/{example => chipyard}/src/main/scala/ConfigMixins.scala (99%) rename generators/{example => chipyard}/src/main/scala/GCD.scala (99%) rename generators/{example => chipyard}/src/main/scala/Generator.scala (95%) rename generators/{example => chipyard}/src/main/scala/HeteroConfigs.scala (99%) rename generators/{example => chipyard}/src/main/scala/InitZero.scala (99%) rename generators/{example => chipyard}/src/main/scala/NodeTypes.scala (99%) rename generators/{example => chipyard}/src/main/scala/RegisterNodeExample.scala (100%) rename generators/{example => chipyard}/src/main/scala/RocketConfigs.scala (99%) rename generators/{utilities => chipyard}/src/main/scala/Subsystem.scala (99%) rename generators/{utilities => chipyard}/src/main/scala/System.scala (98%) rename generators/{example => chipyard}/src/main/scala/TestHarness.scala (98%) rename generators/{utilities => chipyard}/src/main/scala/TestSuites.scala (99%) rename generators/{example => chipyard}/src/main/scala/Top.scala (96%) rename generators/{example => chipyard}/src/main/scala/TopCakes.scala (97%) diff --git a/.circleci/config.yml b/.circleci/config.yml index 8a1fdb48..ad5671b1 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -188,105 +188,76 @@ jobs: key: extra-tests-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project/tests" - prepare-example: + prepare-chipyard-rocket: executor: main-env steps: - prepare-rtl: - project-key: "example" - prepare-boomrocketexample: + project-key: "chipyard-rocket" + prepare-chipyard-hetero: executor: main-env steps: - prepare-rtl: - project-key: "boomrocketexample" + project-key: "chipyard-hetero" timeout: "240m" - prepare-boom: + prepare-chipyard-boom: executor: main-env steps: - prepare-rtl: - project-key: "boom" + project-key: "chipyard-boom" prepare-rocketchip: executor: main-env steps: - prepare-rtl: project-key: "rocketchip" - prepare-blockdevrocketchip: + prepare-chipyard-blkdev: executor: main-env steps: - prepare-rtl: - project-key: "blockdevrocketchip" - prepare-hwacha: + project-key: "chipyard-blkdev" + prepare-chipyard-hwacha: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "hwacha" - prepare-gemmini: + project-key: "chipyard-hwacha" + prepare-chipyard-gemmini: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "gemmini" - prepare-tracegen: - executor: main-env - steps: - - prepare-rtl: - project-key: "tracegen" - prepare-tracegen-boom: - executor: main-env - steps: - - prepare-rtl: - project-key: "tracegen-boom" - prepare-firesim: - executor: main-env - steps: - - prepare-rtl: - project-key: "firesim" - build-script: "do-firesim-build.sh" - prepare-fireboom: - executor: main-env - steps: - - prepare-rtl: - project-key: "fireboom" - build-script: "do-firesim-build.sh" - midasexamples-run-tests: - executor: main-env - steps: - - setup-tools-verilator - - run: - name: Run midasexamples tests - command: .circleci/run-midasexamples-tests.sh - example-run-tests: + project-key: "chipyard-gemmini" + chipyard-rocket-run-tests: executor: main-env steps: - run-tests: - project-key: "example" - boomrocketexample-run-tests: + project-key: "chipyard-rocket" + chipyard-hetero-run-tests: executor: main-env steps: - run-tests: - project-key: "boomrocketexample" - boom-run-tests: + project-key: "chipyard-hetero" + chipyard-boom-run-tests: executor: main-env steps: - run-tests: - project-key: "boom" + project-key: "chipyard-boom" rocketchip-run-tests: executor: main-env steps: - run-tests: project-key: "rocketchip" - hwacha-run-tests: + chipyard-hwacha-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" - project-key: "hwacha" - gemmini-run-tests: + project-key: "chipyard-hwacha" + chipyard-gemmini-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" - project-key: "gemmini" + project-key: "chipyard-gemmini" tracegen-run-tests: executor: main-env steps: @@ -346,17 +317,17 @@ workflows: - install-riscv-toolchain # Prepare the verilator builds - - prepare-example: + - prepare-chipyard-rocket: requires: - install-riscv-toolchain - install-verilator - - prepare-boomrocketexample: + - prepare-chipyard-hetero: requires: - install-riscv-toolchain - install-verilator - - prepare-boom: + - prepare-chipyard-boom: requires: - install-riscv-toolchain - install-verilator @@ -366,17 +337,17 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-blockdevrocketchip: + - prepare-chipyard-blkdev: requires: - install-riscv-toolchain - install-verilator - - prepare-hwacha: + - prepare-chipyard-hwacha: requires: - install-esp-toolchain - install-verilator - - prepare-gemmini: + - prepare-chipyard-gemmini: requires: - install-esp-toolchain - install-verilator @@ -410,29 +381,29 @@ workflows: - install-verilator # Run the example tests - - example-run-tests: + - chipyard-rocket-run-tests: requires: - - prepare-example + - prepare-chipyard-rocket - - boomrocketexample-run-tests: + - chipyard-hetero-run-tests: requires: - - prepare-boomrocketexample + - prepare-chipyard-hetero - - boom-run-tests: + - chipyard-boom-run-tests: requires: - - prepare-boom + - prepare-chipyard-boom - rocketchip-run-tests: requires: - prepare-rocketchip - - hwacha-run-tests: + - chipyard-hwacha-run-tests: requires: - - prepare-hwacha + - prepare-chipyard-hwacha - - gemmini-run-tests: + - chipyard-gemmini-run-tests: requires: - - prepare-gemmini + - prepare-chipyard-gemmini - tracegen-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 08c4222c..64ed3138 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -41,13 +41,13 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping -mapping["example"]="SUB_PROJECT=example" -mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=LargeBoomAndRocketConfig" -mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" +mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" +mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" +mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" -mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig" -mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig" -mapping["gemmini"]="SUB_PROJECT=example CONFIG=GemminiRocketConfig" +mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" +mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" +mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]="SUB_PROJECT=tracegen CONFIG=BoomTraceGenConfig" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index dd667dfb..2e6384a2 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -32,7 +32,7 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then +if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib run "mkdir -p $REMOTE_ESP_DIR" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 6d01d182..cc747756 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -29,28 +29,25 @@ run_tracegen () { } case $1 in - example) + chipyard-rocket) run_bmark ${mapping[$1]} ;; - boomexample) + chipyard-boom) run_bmark ${mapping[$1]} ;; - boomrocketexample) - run_bmark ${mapping[$1]} - ;; - boom) + chipyard-hetero) run_bmark ${mapping[$1]} ;; rocketchip) run_bmark ${mapping[$1]} ;; - hwacha) + chipyard-hwacha) export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; - gemmini) + chipyard-gemmini) export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH @@ -58,9 +55,9 @@ case $1 in cd $GEMMINI_SOFTWARE_DIR ./build.sh cd $LOCAL_SIM_DIR - $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; tracegen) run_tracegen ${mapping[$1]} diff --git a/build.sbt b/build.sbt index 2fd83c55..539f9307 100644 --- a/build.sbt +++ b/build.sbt @@ -122,7 +122,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) -lazy val example = conditionalDependsOn(project in file("generators/example")) +lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet) .settings(commonSettings) @@ -131,7 +131,6 @@ lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) .settings(commonSettings) lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) - .dependsOn(rocketchip, boom) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) @@ -155,7 +154,7 @@ lazy val gemmini = (project in file("generators/gemmini")) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, example) + .dependsOn(chisel_testers, chipyard) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) @@ -196,7 +195,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, example, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/example/src/main/resources/vsrc/GCDMMIOBlackBox.v b/generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v similarity index 100% rename from generators/example/src/main/resources/vsrc/GCDMMIOBlackBox.v rename to generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala similarity index 99% rename from generators/example/src/main/scala/BoomConfigs.scala rename to generators/chipyard/src/main/scala/BoomConfigs.scala index a6a0adb4..9eae1ea0 100644 --- a/generators/example/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigMixins.scala similarity index 99% rename from generators/example/src/main/scala/ConfigMixins.scala rename to generators/chipyard/src/main/scala/ConfigMixins.scala index acd1001e..f2dfcf2b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigMixins.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.util.{log2Up} diff --git a/generators/example/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala similarity index 99% rename from generators/example/src/main/scala/GCD.scala rename to generators/chipyard/src/main/scala/GCD.scala index f41e78db..1b66b76c 100644 --- a/generators/example/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.util._ diff --git a/generators/example/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala similarity index 95% rename from generators/example/src/main/scala/Generator.scala rename to generators/chipyard/src/main/scala/Generator.scala index 9beb094c..32619f29 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/chipyard/src/main/scala/Generator.scala @@ -1,4 +1,4 @@ -package example +package chipyard import scala.util.Try @@ -8,8 +8,6 @@ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.system.{TestGeneration} -import utilities.{TestSuiteHelper} - object Generator extends GeneratorApp { // add unique test suites override def addTestSuites { diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala similarity index 99% rename from generators/example/src/main/scala/HeteroConfigs.scala rename to generators/chipyard/src/main/scala/HeteroConfigs.scala index ff3bf338..4bfea32c 100644 --- a/generators/example/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/example/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/InitZero.scala similarity index 99% rename from generators/example/src/main/scala/InitZero.scala rename to generators/chipyard/src/main/scala/InitZero.scala index 4c7f3bbb..2861e0bb 100644 --- a/generators/example/src/main/scala/InitZero.scala +++ b/generators/chipyard/src/main/scala/InitZero.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.util._ diff --git a/generators/example/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/NodeTypes.scala similarity index 99% rename from generators/example/src/main/scala/NodeTypes.scala rename to generators/chipyard/src/main/scala/NodeTypes.scala index 577b9baf..ca55b2ac 100644 --- a/generators/example/src/main/scala/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/NodeTypes.scala @@ -1,4 +1,4 @@ -package example +package chipyard import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ diff --git a/generators/example/src/main/scala/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/RegisterNodeExample.scala similarity index 100% rename from generators/example/src/main/scala/RegisterNodeExample.scala rename to generators/chipyard/src/main/scala/RegisterNodeExample.scala diff --git a/generators/example/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala similarity index 99% rename from generators/example/src/main/scala/RocketConfigs.scala rename to generators/chipyard/src/main/scala/RocketConfigs.scala index 7cc43a4d..dfdadf03 100644 --- a/generators/example/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/utilities/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala similarity index 99% rename from generators/utilities/src/main/scala/Subsystem.scala rename to generators/chipyard/src/main/scala/Subsystem.scala index d5354946..d8635cd5 100644 --- a/generators/utilities/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -3,7 +3,7 @@ // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ -package utilities +package chipyard import chisel3._ import chisel3.internal.sourceinfo.{SourceInfo} diff --git a/generators/utilities/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala similarity index 98% rename from generators/utilities/src/main/scala/System.scala rename to generators/chipyard/src/main/scala/System.scala index 0eed6660..f18a2068 100644 --- a/generators/utilities/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -3,7 +3,7 @@ // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ -package utilities +package chipyard import chisel3._ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala similarity index 98% rename from generators/example/src/main/scala/TestHarness.scala rename to generators/chipyard/src/main/scala/TestHarness.scala index 50c872f2..6c01753f 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.experimental._ diff --git a/generators/utilities/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala similarity index 99% rename from generators/utilities/src/main/scala/TestSuites.scala rename to generators/chipyard/src/main/scala/TestSuites.scala index 725e1e69..05c4bf6e 100644 --- a/generators/utilities/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -1,4 +1,4 @@ -package utilities +package chipyard import scala.collection.mutable.{LinkedHashSet} diff --git a/generators/example/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala similarity index 96% rename from generators/example/src/main/scala/Top.scala rename to generators/chipyard/src/main/scala/Top.scala index 47ab1c28..d4382d86 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ @@ -10,8 +10,6 @@ import freechips.rocketchip.util.DontTouch import testchipip._ -import utilities.{System, SystemModule} - import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ diff --git a/generators/example/src/main/scala/TopCakes.scala b/generators/chipyard/src/main/scala/TopCakes.scala similarity index 97% rename from generators/example/src/main/scala/TopCakes.scala rename to generators/chipyard/src/main/scala/TopCakes.scala index 30f13e48..cd52ed55 100644 --- a/generators/example/src/main/scala/TopCakes.scala +++ b/generators/chipyard/src/main/scala/TopCakes.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index dd5b432d..11598719 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -20,7 +20,7 @@ import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGenerat import scala.util.Try -import utilities.TestSuiteHelper +import chipyard.TestSuiteHelper trait HasTestSuites { def addTestSuites(targetName: String, params: Parameters) { diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index ed2a86c5..b57fc305 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -114,6 +114,7 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * determine which driver to build. *******************************************************************************/ class FireSimRocketChipConfig extends Config( + new chipyard.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB @@ -172,6 +173,7 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config( new FireSimRocketChipConfig) class FireSimBoomConfig extends Config( + new chipyard.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index be93bb7a..126dee1f 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -51,7 +51,7 @@ trait HasTraceIOImp extends LazyModuleImp { } trait CanHaveMultiCycleRegfileImp { - val outer: utilities.HasBoomAndRocketTiles + val outer: chipyard.HasBoomAndRocketTiles outer.tiles.map { case r: RocketTile => { diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index b608e67b..ecb6665c 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -12,7 +12,6 @@ import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.amba.axi4.AXI4Bundle import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.LazyModule -import utilities.{Subsystem, SubsystemModuleImp} import icenet._ import firesim.util.DefaultFireSimHarness import testchipip._ @@ -38,53 +37,20 @@ import FireSimValName._ * determine which driver to build. *******************************************************************************/ -class FireSimDUT(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with CanHavePeripherySerial - with HasPeripheryUART - with CanHavePeripheryIceNIC - with CanHavePeripheryBlockDevice +class FireSimDUT(implicit p: Parameters) extends chipyard.Top with HasTraceIO { override lazy val module = new FireSimModuleImp(this) } -class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with CanHavePeripherySerialModuleImp - with HasPeripheryUARTModuleImp - with HasPeripheryIceNICModuleImpValidOnly - with CanHavePeripheryBlockDeviceModuleImp +class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) with HasTraceIOImp with CanHaveMultiCycleRegfileImp class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) -class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with CanHavePeripherySerial - with HasPeripheryUART - with CanHavePeripheryBlockDevice - with HasTraceIO -{ - override lazy val module = new FireSimNoNICModuleImp(this) -} - -class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with CanHavePeripherySerialModuleImp - with HasPeripheryUARTModuleImp - with CanHavePeripheryBlockDeviceModuleImp - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp +// Kept for legacy-reasons, this is equivalent to FireSimDUT +class FireSimNoNICDUT(implicit p: Parameters) extends FireSimDUT class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) @@ -107,7 +73,7 @@ class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() // Verilog blackbox integration demo class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT - with example.CanHavePeripheryGCD + with chipyard.CanHavePeripheryGCD { override lazy val module = new FireSimVerilogGCDModuleImp(this) } diff --git a/variables.mk b/variables.mk index a303eafe..1ddada7b 100644 --- a/variables.mk +++ b/variables.mk @@ -25,10 +25,10 @@ # - make it so that you only change 1 param to change most or all of them! # - mainly intended for quick developer setup for common flags ######################################################################################### -SUB_PROJECT ?= example +SUB_PROJECT ?= chipyard -ifeq ($(SUB_PROJECT),example) - SBT_PROJECT ?= example +ifeq ($(SUB_PROJECT),chipyard) + SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) From ebfa545344fcfea8bf17f598575b7a581c04d333 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Feb 2020 20:15:09 -0800 Subject: [PATCH 13/50] Generator unification --- .circleci/config.yml | 32 ++ .circleci/defaults.sh | 4 +- .circleci/do-rtl-build.sh | 12 + .circleci/run-tests.sh | 9 +- build.sbt | 4 +- .../chipyard/src/main/scala/BoomConfigs.scala | 162 +++++++--- .../src/main/scala/ConfigMixins.scala | 128 +------- generators/chipyard/src/main/scala/GCD.scala | 11 +- .../src/main/scala/HeteroConfigs.scala | 214 ++++++------ .../chipyard/src/main/scala/IOBinders.scala | 131 ++++++++ .../chipyard/src/main/scala/InitZero.scala | 11 +- .../chipyard/src/main/scala/NodeTypes.scala | 2 +- .../src/main/scala/RocketConfigs.scala | 304 ++++++++++++------ .../chipyard/src/main/scala/TestHarness.scala | 39 +-- generators/chipyard/src/main/scala/Top.scala | 40 +-- .../chipyard/src/main/scala/TopCakes.scala | 27 -- .../src/main/scala/TracegenConfigs.scala | 35 ++ .../src/main/scala/BridgeBinders.scala | 83 +++-- .../src/main/scala/TargetConfigs.scala | 147 ++------- ...{TargetMixins.scala => TargetTraits.scala} | 0 .../firechip/src/main/scala/Targets.scala | 45 +-- generators/icenet | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 17 - .../tracegen/src/main/scala/TestHarness.scala | 27 -- sims/firesim | 2 +- variables.mk | 11 - 27 files changed, 815 insertions(+), 686 deletions(-) create mode 100644 generators/chipyard/src/main/scala/IOBinders.scala delete mode 100644 generators/chipyard/src/main/scala/TopCakes.scala create mode 100644 generators/chipyard/src/main/scala/TracegenConfigs.scala rename generators/firechip/src/main/scala/{TargetMixins.scala => TargetTraits.scala} (100%) delete mode 100644 generators/tracegen/src/main/scala/TestHarness.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index ad5671b1..8758064e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -226,6 +226,31 @@ jobs: - prepare-rtl: tools-version: "esp-tools" project-key: "chipyard-gemmini" + prepare-tracegen: + executor: main-env + steps: + - prepare-rtl: + project-key: "tracegen" + prepare-tracegen-boom: + executor: main-env + steps: + - prepare-rtl: + project-key: "tracegen-boom" + prepare-firesim: + executor: main-env + steps: + - prepare-rtl: + project-key: "firesim" + build-script: "do-firesim-build.sh" + prepare-fireboom: + executor: main-env + steps: + - prepare-rtl: + project-key: "fireboom" + build-script: "do-firesim-build.sh" + + + chipyard-rocket-run-tests: executor: main-env steps: @@ -284,6 +309,13 @@ jobs: run-script: "run-firesim-tests.sh" timeout: "20m" + midasexamples-run-tests: + executor: main-env + steps: + - setup-tools-verilator + - run: + name: Run midasexamples tests + command: .circleci/run-midasexamples-tests.sh # Order and dependencies of jobs to run workflows: version: 2 diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 64ed3138..6c2fdd16 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -48,7 +48,7 @@ mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" -mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config" -mapping["tracegen-boom"]="SUB_PROJECT=tracegen CONFIG=BoomTraceGenConfig" +mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" +mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 2e6384a2..5276080f 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -32,6 +32,18 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib + +if [ $1 = "chipyard-gemmini" ]; then + export RISCV=$LOCAL_ESP_DIR + export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib + export PATH=$RISCV/bin:$PATH + GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests + cd $LOCAL_SIM_DIR/../../generators/gemmini/software + git submodule update --init --recursive gemmini-rocc-tests + cd gemmini-rocc-tests + ./build.sh +fi + if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index cc747756..100418aa 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -52,12 +52,11 @@ case $1 in export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests - cd $GEMMINI_SOFTWARE_DIR - ./build.sh + rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests cd $LOCAL_SIM_DIR - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; tracegen) run_tracegen ${mapping[$1]} diff --git a/build.sbt b/build.sbt index 539f9307..678fffb5 100644 --- a/build.sbt +++ b/build.sbt @@ -123,7 +123,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet, tracegen) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -195,7 +195,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala index 9eae1ea0..cd1e691b 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -8,74 +8,118 @@ import freechips.rocketchip.config.{Config} // BOOM Configs // --------------------- + class SmallBoomConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // use testchipip bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level mmio master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level mmio slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache - new boom.common.WithSmallBooms ++ // 1-wide BOOM - new boom.common.WithNBoomCores(1) ++ // single-core - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new boom.common.WithSmallBooms ++ // small boom config + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + class MediumBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithMediumBooms ++ // 2-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithLargeBooms ++ // 3-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithMegaBooms ++ // 4-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class DualSmallBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(2) ++ // dual-core + new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.system.BaseConfig) class SmallRV32BoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithoutBoomFPU ++ // no fp new boom.common.WithBoomRV32 ++ // rv32 (32bit) new boom.common.WithSmallBooms ++ @@ -83,28 +127,42 @@ class SmallRV32BoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class HwachaLargeBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new boom.common.WithLargeBooms ++ // 3-wide BOOM - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - -class LoopbackNICBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithLoopbackNIC ++ // loopback the NIC - new WithIceNIC ++ // add IceNIC - new WithBootROM ++ - new WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class LoopbackNICLargeBoomConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new testchipip.WithTSI ++ + new icenet.WithIceNIC ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigMixins.scala index f2dfcf2b..8234f0e3 100644 --- a/generators/chipyard/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigMixins.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.config import chisel3._ import chisel3.util.{log2Up} @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import icenet.{NICKey, NICConfig} +import chipyard.{BuildTop} /** * TODO: Why do we need this? @@ -35,117 +35,40 @@ import ConfigValName._ // Common Parameter Mixins // ----------------------- -/** - * Mixin to add the Chipyard bootrom - */ class WithBootROM extends Config((site, here, up) => { case BootROMParams => BootROMParams( contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") }) // DOC include start: gpio mixin -/** - * Mixin to add GPIOs and tie them off outside the DUT - */ class WithGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq( GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - // TODO: Currently FIRRTL will error if the GPIO input - // pins are unconnected, so tie them to 0. - // In future IO cell blackboxes will replace this with - // more correct functionality - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } }) // DOC include end: gpio mixin -/** - * Mixin to add in UART - */ class WithUART extends Config((site, here, up) => { case PeripheryUARTKey => Seq( UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) -/** - * Mixin to remove any GPIOs - */ class WithNoGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq() }) -// DOC include start: tsi mixin -/** - * Mixin to add an offchip TSI link (used for backing memory) - */ -class WithTSI extends Config((site, here, up) => { - case SerialKey => true - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - success := top.connectSimSerial() - top - } -}) -// DOC include end: tsi mixin - -/** - * Mixin to add an DTM (used for dmi or jtag bringup) - */ -class WithDTM extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.reset := reset.asBool | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) - Debug.connectDebug(top.debug, top.psd, clock, reset.asBool, success)(p) - top - } +class WithL2TLBs(entries: Int) extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) }) -// DOC include start: GCD mixin -/** - * Mixin to add a GCD peripheral - */ -class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { - case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) -}) -// DOC include end: GCD mixin - -/** - * Mixin to add a RTL block device model - */ -class WithBlockDeviceModel extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectBlockDeviceModel() - top - } +class WithTracegenTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) }) -/** - * Mixin to add a simulated block device model - */ -class WithSimBlockDevice extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -// DOC include start: WithInitZero -/** - * Mixin to add a peripheral that clears memory - */ -class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { - case InitZeroKey => Some(InitZeroConfig(base, size)) -}) -// DOC include end: WithInitZero // ------------------ // Multi-RoCC Support @@ -215,32 +138,3 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) - -/** - * Mixin to add an IceNIC - */ -class WithIceNIC(inBufFlits: Int = 1800, usePauser: Boolean = false) - extends Config((site, here, up) => { - case NICKey => Some(NICConfig( - inBufFlits = inBufFlits, - usePauser = usePauser, - checksumOffload = true)) -}) - -/** - * Mixin to loopback the IceNIC - */ -class WithLoopbackNIC extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectNicLoopback() - top - } -}) - -/** - * Mixin to add a backing scratchpad (default size 4MB) - */ -class WithBackingScratchpad(base: BigInt = 0x80000000L, mask: BigInt = ((4 << 20) - 1)) extends Config((site, here, up) => { - case BackingScratchpadKey => Some(BackingScratchpadParams(base, mask)) -}) diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala index 1b66b76c..802520f0 100644 --- a/generators/chipyard/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -1,11 +1,11 @@ -package chipyard +package chipyard.example import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper.{HasRegMap, RegField} import freechips.rocketchip.tilelink._ @@ -198,3 +198,10 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { } // DOC include end: GCD imp trait + + +// DOC include start: GCD mixin +class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { + case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) +}) +// DOC include end: GCD mixin diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala index 4bfea32c..b5cc6b8c 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -9,140 +9,164 @@ import freechips.rocketchip.config.{Config} // --------------------- class LargeBoomAndRocketConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // default bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2 - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new boom.common.WithRenumberHarts ++ // avoid hartid overlap - new boom.common.WithLargeBooms ++ // 3-wide boom - new boom.common.WithNBoomCores(1) ++ // single-core boom - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system - -class SmallBoomAndRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithSmallBooms ++ // 1-wide boom - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new boom.common.WithRenumberHarts ++ // avoid hartid overlap + new boom.common.WithLargeBooms ++ // 3-wide boom + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: BoomAndRocketWithHwacha class HwachaLargeBoomAndHwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha -class RoccLargeBoomAndRoccRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithRoccExample ++ // add example rocc accelerator to all harts - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - class DualLargeBoomAndRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2-boom cores + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: DualBoomAndRocketOneHwacha -class DualLargeBoomAndHwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithMultiRoCC ++ // support heterogeneous rocc - new WithMultiRoCCHwacha(2) ++ // override: put hwacha on hart-2 (rocket) - new hwacha.DefaultHwachaConfig ++ // setup hwacha on all harts + +class LargeBoomAndHwachaRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc + new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocketOneHwacha + + class LargeBoomAndRV32RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithRV32 ++ // use 32-bit rocket + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + // DOC include start: DualBoomAndRocket class DualLargeBoomAndDualRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocket -class MultiCoreWithControlCoreConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithControlCore ++ // add small control core (last hartid) +class LargeBoomAndRocketWithControlCoreConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithControlCore ++ // add small control core to last hartid + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 normal boom cores - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 normal rocket cores + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala new file mode 100644 index 00000000..969230b7 --- /dev/null +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -0,0 +1,131 @@ +package chipyard.iobinders + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.util._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ + +import testchipip._ +import icenet._ +import tracegen.{HasTraceGenTilesModuleImp} + +import scala.reflect.{ClassTag, classTag} + +case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) + +class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + t match { + case top: T => fn(clock, reset, success, top) + case _ => Nil + } + }) + ) +}) + +class WithGPIOTiedOff extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil +}) + +class WithSimBlockDevice extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil +}) + +class WithBlockDeviceModel extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil +}) + +class WithLoopbackNIC extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil +}) + +class WithUARTAdapter extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryUARTModuleImp) => { + val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate + top.uart.zipWithIndex.foreach{ case (dut_io, i) => + val uart_sim = Module(new UARTAdapter(i, defaultBaudRate)(top.p)) + uart_sim.io.uart.txd := dut_io.txd + dut_io.rxd := uart_sim.io.uart.rxd + } + Nil + } +}) + +class WithSimAXIMem extends RegisterIOBinder({ + (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil +}) + +class WithSimAXIMMIO extends RegisterIOBinder({ + (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil +}) + +class WithDontTouchPorts extends RegisterIOBinder({ + (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil +}) + +class WithTieOffInterrupts extends RegisterIOBinder({ + (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil +}) + +class WithTieOffL2FBusAXI extends RegisterIOBinder({ + (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { + top.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + Nil + } +}) + +class WithTiedOffDebug extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(top.debug, top.psd) + // tieoffDebug doesn't actually tie everything off :/ + top.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } +}) + +class WithSimSerial extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripherySerialModuleImp) => { + val ser_success = top.connectSimSerial() + when (ser_success) { s := true.B } + Nil + } +}) + +class WithTiedOffSerial extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil +}) + + +class WithSimDTM extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryDebugModuleImp) => { + val dtm_success = Wire(Bool()) + top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) + Debug.connectDebug(top.debug, top.psd, c, r, dtm_success)(top.p) + when (dtm_success) { s := true.B } + Nil + } +}) + + +class WithTraceGenSuccessBinder extends RegisterIOBinder({ + (c, r, s, top: HasTraceGenTilesModuleImp) => s := top.success; Nil +}) diff --git a/generators/chipyard/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/InitZero.scala index 2861e0bb..c351a4dd 100644 --- a/generators/chipyard/src/main/scala/InitZero.scala +++ b/generators/chipyard/src/main/scala/InitZero.scala @@ -1,9 +1,9 @@ -package chipyard +package chipyard.example import chisel3._ import chisel3.util._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import testchipip.TLHelper @@ -65,3 +65,10 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem => fbus.fromPort(Some("init-zero"))() := initZero.node } } + + +// DOC include start: WithInitZero +class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { + case InitZeroKey => Some(InitZeroConfig(base, size)) +}) +// DOC include end: WithInitZero diff --git a/generators/chipyard/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/NodeTypes.scala index ca55b2ac..0e2b6565 100644 --- a/generators/chipyard/src/main/scala/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/NodeTypes.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.example import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index dfdadf03..4acf7943 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -9,233 +9,357 @@ import freechips.rocketchip.config.{Config} // -------------- class RocketConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // use default bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class HwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GemminiRocketConfig class RoccRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: JtagRocket class jtagRocketConfig extends Config( - new WithDTM ++ // use top with dtm - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ // enable communicating with the DTM using jtag + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithSimDTM ++ // add SimJtag and SimSerial, use both to drive sim + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: JtagRocket // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new WithDTM ++ // use top with dtm - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffSerial ++ + new chipyard.iobinders.WithSimDTM ++ // add SimDTM and use it to drive simulation + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DmiRocket // DOC include start: GCDTLRocketConfig class GCDTLRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithUART ++ - new WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink - new WithBootROM ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDTLRocketConfig // DOC include start: GCDAXI4BlackBoxRocketConfig class GCDAXI4BlackBoxRocketConfig extends Config( - new WithTSI ++ - new WithUART ++ - new WithNoGPIO ++ - new WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink - new WithBootROM ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig class SimBlockDeviceRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new WithSimBlockDevice ++ // use top with block-device IOs and connect to simblockdevice - new WithBootROM ++ - new WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel + new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new WithBlockDeviceModel ++ // use top with block-device IOs and connect to a blockdevicemodel - new WithBootROM ++ - new WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( - new WithTSI ++ - new WithGPIO ++ // add GPIOs to the peripherybus - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top + new testchipip.WithTSI ++ + new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig class DualCoreRocketConfig extends Config( - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles) new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class GB1MemoryRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: Sha3Rocket class Sha3RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: Sha3Rocket // DOC include start: InitZeroRocketConfig class InitZeroRocketConfig extends Config( - new WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero - new WithNoGPIO ++ - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: InitZeroRocketConfig class LoopbackNICRocketConfig extends Config( - new WithTSI ++ - new WithIceNIC ++ // add an IceNIC - new WithNoGPIO ++ - new WithLoopbackNIC ++ // loopback the IceNIC - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new testchipip.WithTSI ++ + new icenet.WithIceNIC ++ // add an IceNIC + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class ScratchpadRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new WithBackingScratchpad ++ // add backing scratchpad + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new testchipip.WithBackingScratchpad ++ // add backing scratchpad + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 6c01753f..ca861288 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -10,48 +10,21 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp import freechips.rocketchip.devices.debug.{Debug} -/** - * TODO: Why do we need this? - */ -import ConfigValName._ +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders} // ------------------------------- // BOOM and/or Rocket Test Harness // ------------------------------- -case object BuildTop extends Field[(Clock, Bool, Parameters, Bool) => TopModule[Top]]( - (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = Module(LazyModule(new Top()(p)).suggestName("top").module) - top.debug.map { debug => debug := DontCare } - top - } -) +case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module)) -/** - * Test harness using TSI to bringup the system - */ class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) - val dut = p(BuildTop)(clock, reset.toBool, p, io.success) - dut.connectSimUARTs() - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - + val dut = p(BuildTop)(p) + io.success := false.B + p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut)) } diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala index d4382d86..b95794e5 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -6,14 +6,6 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util.DontTouch - -import testchipip._ - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ - -import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp} // ------------------------------------ // BOOM and/or Rocket Top Level Systems @@ -21,26 +13,24 @@ import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp} // DOC include start: Top class Top(implicit p: Parameters) extends System - with CanHavePeripheryUARTAdapter // Enables optionally adding the UART print adapter - with HasPeripheryUART // Enables optionally adding the sifive UART - with HasPeripheryGPIO // Enables optionally adding the sifive GPIOs - with CanHavePeripheryBlockDevice // Enables optionally adding the block device - with CanHavePeripheryInitZero // Enables optionally adding the initzero example widget - with CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port - with CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim - with CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device + with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port + with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART + with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim + with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget + with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget { override lazy val module = new TopModule(this) } class TopModule[+L <: Top](l: L) extends SystemModule(l) - with HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with CanHavePeripheryBlockDeviceModuleImp - with CanHavePeripheryGCDModuleImp - with CanHavePeripherySerialModuleImp - with CanHavePeripheryIceNICModuleImp - with CanHavePeripheryUARTAdapterModuleImp - with DontTouch + with testchipip.CanHavePeripheryBlockDeviceModuleImp + with testchipip.CanHavePeripherySerialModuleImp + with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with icenet.CanHavePeripheryIceNICModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with freechips.rocketchip.util.DontTouch // DOC include end: Top diff --git a/generators/chipyard/src/main/scala/TopCakes.scala b/generators/chipyard/src/main/scala/TopCakes.scala deleted file mode 100644 index cd52ed55..00000000 --- a/generators/chipyard/src/main/scala/TopCakes.scala +++ /dev/null @@ -1,27 +0,0 @@ -package chipyard - -import chisel3._ - -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Field} -import freechips.rocketchip.diplomacy.{LazyModule, AddressSet} -import freechips.rocketchip.tilelink.{TLRAM} - -case class BackingScratchpadParams( - base: BigInt, - mask: BigInt) - -case object BackingScratchpadKey extends Field[Option[BackingScratchpadParams]](None) - -/** - * Trait to add a scratchpad on the mbus - */ -trait CanHaveBackingScratchpad { this: BaseSubsystem => - private val portName = "Backing-Scratchpad" - - val spadOpt = p(BackingScratchpadKey).map { param => - val spad = LazyModule(new TLRAM(address=AddressSet(param.base, param.mask), beatBytes=mbus.beatBytes)) - mbus.toVariableWidthSlave(Some(portName)) { spad.node } - spad - } -} diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala new file mode 100644 index 00000000..0e3457f0 --- /dev/null +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -0,0 +1,35 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.rocket.{DCacheParams} + +class TraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class BoomTraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenL2Config extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f0c9c664..2e4fbd24 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -3,52 +3,48 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.annotate -import freechips.rocketchip.config.{Field, Config} +import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} -import icenet.HasPeripheryIceNICModuleImpValidOnly +import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} +import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey -import firesim.util.RegisterBridgeBinder import tracegen.HasTraceGenTilesModuleImp -class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp => - target.debug.foreach(_.clockeddmi.foreach({ cdmi => - cdmi.dmi.req.valid := false.B - cdmi.dmi.req.bits := DontCare - cdmi.dmi.resp.ready := false.B - cdmi.dmiClock := false.B.asClock - cdmi.dmiReset := false.B - })) - Seq() +import boom.common.{BoomTile} + +import chipyard.iobinders.{IOBinders, RegisterIOBinder} +import chipyard.HasBoomAndRocketTilesModuleImp + +class WithSerialBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq }) -class WithSerialBridge extends RegisterBridgeBinder({ - case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.serial.get)(target.p)) +class WithNICBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq }) -class WithNICBridge extends RegisterBridgeBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) +class WithUARTBridge extends RegisterIOBinder({ + (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq }) -class WithUARTBridge extends RegisterBridgeBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) +class WithBlockDeviceBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq }) -class WithBlockDeviceBridge extends RegisterBridgeBinder({ - case target: CanHavePeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev.get, target.reset.toBool)(target.p)) -}) - -class WithFASEDBridge extends RegisterBridgeBinder({ - case t: CanHaveMasterAXI4MemPortModuleImp => +class WithFASEDBridge extends RegisterIOBinder({ + (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => @@ -59,24 +55,51 @@ class WithFASEDBridge extends RegisterBridgeBinder({ CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq + } }) -class WithTracerVBridge extends RegisterBridgeBinder({ - case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) +class WithTracerVBridge extends RegisterIOBinder({ + (c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p)) }) -class WithTraceGenBridge extends RegisterBridgeBinder({ - case target: HasTraceGenTilesModuleImp => - Seq(GroundTestBridge(target.success)(target.p)) +class WithTraceGenBridge extends RegisterIOBinder({ + (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) +class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ + (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { + target.outer.tiles.map { + case r: RocketTile => { + annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) + r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + } + case b: BoomTile => { + val core = b.module.core + core.iregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { + case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) + case _ => Nil + } + } + } + Nil + } +}) + + + // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new WithTiedOffDebug ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithTieOffInterrupts ++ new WithSerialBridge ++ new WithNICBridge ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ new WithFASEDBridge ++ + new WithFireSimMultiCycleRegfile ++ new WithTracerVBridge ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b57fc305..9ecf6f48 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -2,6 +2,7 @@ package firesim.firesim import java.io.File +import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Parameters, Config} import freechips.rocketchip.groundtest.TraceGenParams @@ -11,6 +12,7 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} +import freechips.rocketchip.diplomacy.LazyModule import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} @@ -21,6 +23,8 @@ import icenet._ import firesim.bridges._ import firesim.util.{WithNumNodes} import firesim.configs._ +import chipyard.{BuildTop} +import chipyard.config.ConfigValName._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -40,33 +44,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) }) -class WithUARTKey extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams( - address = BigInt(0x54000000L), - nTxEntries = 256, - nRxEntries = 256)) -}) - -class WithSerial extends Config((site, here, up) => { - case SerialKey => true -}) - -class WithBlockDevice extends Config(new testchipip.WithBlockDevice) - -class WithNICKey extends Config((site, here, up) => { - case NICKey => Some(NICConfig( - inBufFlits = 8192, - ctrlQueueDepth = 64, - checksumOffload = true)) -}) - -class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy( - nL2TLBEntries = entries - ) - )) -}) class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( @@ -74,11 +51,6 @@ class WithPerfCounters extends Config((site, here, up) => { )) }) -class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) -}) class WithBoomEnableTrace extends Config((site, here, up) => { case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) @@ -92,7 +64,11 @@ class WithoutClockGating extends Config((site, here, up) => { // Testing configurations // This enables printfs used in testing class WithScalaTestFeatures extends Config((site, here, up) => { - case PrintTracePort => true + case PrintTracePort => true +}) + +class WithFireSimTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module) }) // FASED Config Aliases. This to enable config generation via "_" concatenation @@ -114,20 +90,24 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * determine which driver to build. *******************************************************************************/ class FireSimRocketChipConfig extends Config( - new chipyard.WithNoGPIO ++ + new chipyard.config.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithSerial ++ - new WithBlockDevice ++ - new WithRocketL2TLBs(1024) ++ + new chipyard.config.WithUART ++ + new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithL2TLBs(1024) ++ new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ new WithDefaultFireSimBridges ++ + new WithFireSimTop ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -173,22 +153,26 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config( new FireSimRocketChipConfig) class FireSimBoomConfig extends Config( - new chipyard.WithNoGPIO ++ + new chipyard.config.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithSerial ++ - new WithBlockDevice ++ new WithBoomEnableTrace ++ - new WithBoomL2TLBs(1024) ++ + new chipyard.config.WithUART ++ + new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new WithDefaultFireSimBridges ++ + new WithFireSimTop ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.system.BaseConfig ) @@ -215,10 +199,12 @@ class FireSimBoomQuadCoreConfig extends Config( // dual core config (rocket + small boom) class FireSimRocketBoomConfig extends Config( - new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) + new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) new boom.common.WithRenumberHarts ++ // fix hart numbering new boom.common.WithSmallBooms ++ // change single BOOM to small new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new FireSimBoomConfig ) @@ -277,72 +263,3 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config( new WithNumNodes(4) ++ new WithExtMemSize(0x200000000L) ++ // 8GB new FireSimRocketChipOctaCoreConfig) - -class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => log2Up(params.size) -}) - -class FireSimTraceGenConfig extends Config( - new WithTraceGen( - List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new WithTraceGenBridge ++ - new FireSimRocketChipConfig) - -class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val sbp = site(SystemBusKey) - val l2p = site(InclusiveCacheKey) - val nSets = max(l2p.sets, dcp.nSets) - val nWays = max(l2p.ways, dcp.nWays) - val nBanks = site(BankedL2Key).nBanks - val blockOffset = sbp.blockOffset - val nBeats = min(2, sbp.blockBeats) - val beatBytes = sbp.beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => log2Up(params.size) -}) - -class FireSimTraceGenL2Config extends Config( - new WithL2TraceGen( - List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new WithInclusiveCache( - nBanks = 4, - capacityKB = 1024, - outerLatencyCycles = 50) ++ - new WithTraceGenBridge ++ - new FireSimRocketChipConfig) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetTraits.scala similarity index 100% rename from generators/firechip/src/main/scala/TargetMixins.scala rename to generators/firechip/src/main/scala/TargetTraits.scala diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index ecb6665c..bdbda075 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -26,6 +26,8 @@ object FireSimValName { } import FireSimValName._ + + /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -44,40 +46,23 @@ class FireSimDUT(implicit p: Parameters) extends chipyard.Top } class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp + with HasTraceIOImp + with CanHaveMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) +class FireSim(implicit p: Parameters) extends DefaultFireSimHarness -// Kept for legacy-reasons, this is equivalent to FireSimDUT -class FireSimNoNICDUT(implicit p: Parameters) extends FireSimDUT -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) - -class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem - with HasHierarchicalBusTopology - with HasTraceGenTiles - with CanHaveMasterAXI4MemPort { - override lazy val module = new FireSimTraceGenModuleImp(this) -} - -class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer) - with HasTraceGenTilesModuleImp - with CanHaveMasterAXI4MemPortModuleImp - -class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness( - () => new FireSimTraceGenDUT) - -// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 -class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) - -// Verilog blackbox integration demo -class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT - with chipyard.CanHavePeripheryGCD +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness { - override lazy val module = new FireSimVerilogGCDModuleImp(this) + throw new Exception("FireSimNoNIC is deprecated. Please add WithNoNIC to your TARGET_CONFIG and set DESIGN=FireSim to build a NoNIC simulator") } -class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l) -class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT) +object FireSimTypeAliases { + // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 + type FireSimSupernode = FireSim + + // Verilog blackbox integration demo + type FireSimVerilogGCD = FireSim +} +import FireSimTypeAliases._ diff --git a/generators/icenet b/generators/icenet index 49b6dfb6..4980d3a3 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 49b6dfb6341bf128e95c549e42f881ad16dd45a5 +Subproject commit 4980d3a311e487419f2e6358d678c18b7ff3ffe4 diff --git a/generators/testchipip b/generators/testchipip index c11549ba..ff1daef0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c11549ba30483ee3c0d331fb893c45814bdb6b63 +Subproject commit ff1daef09f2f9c2fdea5e93a3b38c58a226b7b3c diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index dd195296..c22b0e3d 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -60,19 +60,6 @@ class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1 }) - -class TraceGenConfig extends Config( - new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - -class NonBlockingTraceGenConfig extends Config( - new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - -class BoomTraceGenConfig extends Config( - new WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config((site, here, up) => { case TraceGenKey => params.map { dcp => TraceGenParams( @@ -100,7 +87,3 @@ class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size) }) -class NonBlockingTraceGenL2Config extends Config( - new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ - new WithInclusiveCache ++ - new BaseConfig) diff --git a/generators/tracegen/src/main/scala/TestHarness.scala b/generators/tracegen/src/main/scala/TestHarness.scala deleted file mode 100644 index 5e07909f..00000000 --- a/generators/tracegen/src/main/scala/TestHarness.scala +++ /dev/null @@ -1,27 +0,0 @@ -package tracegen - -import chisel3._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.util.GeneratorApp - -class TestHarness(implicit p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - val dut = Module(LazyModule(new TraceGenSystem).module) - io.success := dut.success - dut.connectSimAXIMem() -} - -object Generator extends GeneratorApp { - // specify the name that the generator outputs files as - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - // generate files - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/sims/firesim b/sims/firesim index 52aee63b..c771d114 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52aee63bc04c3769695a41ba18319e316c2e78d5 +Subproject commit c771d1143a98dd19f1c4a842cc8a572b5e54de98 diff --git a/variables.mk b/variables.mk index 1ddada7b..d124fed6 100644 --- a/variables.mk +++ b/variables.mk @@ -38,17 +38,6 @@ ifeq ($(SUB_PROJECT),chipyard) TB ?= TestDriver TOP ?= Top endif -ifeq ($(SUB_PROJECT),tracegen) - SBT_PROJECT ?= tracegen - MODEL ?= TestHarness - VLOG_MODEL ?= $(MODEL) - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= TraceGenConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver - TOP ?= TraceGenSystem -endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT ?= rocketchip From 0f56c4ce44affabc237d73e2e4cc1c4966918b61 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 11 Feb 2020 17:46:21 -0800 Subject: [PATCH 14/50] Unify configs between Chipyard and FireSim --- .circleci/config.yml | 2 +- .circleci/defaults.sh | 4 +- .../src/main/scala/RocketConfigs.scala | 4 +- generators/chipyard/src/main/scala/Top.scala | 2 + .../src/main/scala/BridgeBinders.scala | 5 +- .../src/main/scala/TargetConfigs.scala | 256 ++++++------------ .../src/main/scala/TargetTraits.scala | 74 ----- .../firechip/src/main/scala/Targets.scala | 25 -- generators/testchipip | 2 +- 9 files changed, 91 insertions(+), 283 deletions(-) delete mode 100644 generators/firechip/src/main/scala/TargetTraits.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index 8758064e..e86da712 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -307,7 +307,7 @@ jobs: extra-cache-restore: "extra-tests" project-key: "fireboom" run-script: "run-firesim-tests.sh" - timeout: "20m" + timeout: "30m" midasexamples-run-tests: executor: main-env diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 6c2fdd16..4393381e 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -50,5 +50,5 @@ mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" -mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" +mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" +mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index 4acf7943..6066f86f 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -228,7 +228,7 @@ class GPIORocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig -class DualCoreRocketConfig extends Config( +class QuadRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithSimAXIMem ++ @@ -243,7 +243,7 @@ class DualCoreRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles) + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala index b95794e5..d81d779a 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: Top class Top(implicit p: Parameters) extends System + with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port @@ -26,6 +27,7 @@ class Top(implicit p: Parameters) extends System } class TopModule[+L <: Top](l: L) extends SystemModule(l) + with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 2e4fbd24..3005d095 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp -import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} +import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} @@ -59,7 +59,7 @@ class WithFASEDBridge extends RegisterIOBinder({ }) class WithTracerVBridge extends RegisterIOBinder({ - (c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p)) + (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq }) class WithTraceGenBridge extends RegisterIOBinder({ @@ -93,6 +93,7 @@ class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( + new chipyard.iobinders.WithGPIOTiedOff ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithTieOffInterrupts ++ new WithSerialBridge ++ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9ecf6f48..11916662 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule import boom.common.BoomTilesKey -import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey} +import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} import tracegen.TraceGenKey @@ -52,10 +52,6 @@ class WithPerfCounters extends Config((site, here, up) => { }) -class WithBoomEnableTrace extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) -}) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -64,20 +60,37 @@ class WithoutClockGating extends Config((site, here, up) => { // Testing configurations // This enables printfs used in testing class WithScalaTestFeatures extends Config((site, here, up) => { - case PrintTracePort => true + case TracePortKey => up(TracePortKey, site).map(_.copy(print = true)) }) -class WithFireSimTop extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module) -}) // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package class DDR3FRFCFS extends FRFCFS16GBQuadRank class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB -// L2 Config Aliases. For use with "_" concatenation -class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache +class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) + + + +// Enables tracing on all cores +class WithTraceIO extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) +}) + + +// Tweaks that are generally applied to all firesim configs +class WithFireSimConfigTweaks extends Config( + new WithBootROM ++ // needed to support FireSim-as-top + new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ // 3.2 GHz + new WithoutClockGating ++ + new WithTraceIO ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // 16 GB + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithUART +) /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being @@ -88,178 +101,69 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * will store this name as part of the tags for the AGFI, so that later you can * reconstruct what is in a particular AGFI. These tags are also used to * determine which driver to build. -*******************************************************************************/ -class FireSimRocketChipConfig extends Config( - new chipyard.config.WithNoGPIO ++ - new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - new WithExtMemSize(0x400000000L) ++ // 16GB - new WithoutTLMonitors ++ - new chipyard.config.WithUART ++ - new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ - new testchipip.WithTSI ++ - new testchipip.WithBlockDevice ++ - new chipyard.config.WithL2TLBs(1024) ++ - new WithPerfCounters ++ - new WithoutClockGating ++ - new WithDefaultMemModel ++ + *******************************************************************************/ + +//***************************************************************** +// Rocket configs, base off chipyard's RocketConfig +//***************************************************************** +class FireSimRocketConfig extends Config( new WithDefaultFireSimBridges ++ - new WithFireSimTop ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.system.DefaultConfig) - -class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { - case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i)) -}) - -// single core config -class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig) - -// dual core config -class FireSimRocketChipDualCoreConfig extends Config( - new WithNDuplicatedRocketCores(2) ++ - new FireSimRocketChipSingleCoreConfig) - -// quad core config -class FireSimRocketChipQuadCoreConfig extends Config( - new WithNDuplicatedRocketCores(4) ++ - new FireSimRocketChipSingleCoreConfig) - -// hexa core config -class FireSimRocketChipHexaCoreConfig extends Config( - new WithNDuplicatedRocketCores(6) ++ - new FireSimRocketChipSingleCoreConfig) - -// octa core config -class FireSimRocketChipOctaCoreConfig extends Config( - new WithNDuplicatedRocketCores(8) ++ - new FireSimRocketChipSingleCoreConfig) - -// SHA-3 accelerator config -class FireSimRocketChipSha3L2Config extends Config( - new WithInclusiveCache ++ - new sha3.WithSha3Accel ++ - new WithNBigCores(1) ++ - new FireSimRocketChipConfig) - -// SHA-3 accelerator config with synth printfs enabled -class FireSimRocketChipSha3L2PrintfConfig extends Config( - new WithInclusiveCache ++ - new sha3.WithSha3Printf ++ - new sha3.WithSha3Accel ++ - new WithNBigCores(1) ++ - new FireSimRocketChipConfig) - -class FireSimBoomConfig extends Config( - new chipyard.config.WithNoGPIO ++ - new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - new WithExtMemSize(0x400000000L) ++ // 16GB - new WithoutTLMonitors ++ - new WithBoomEnableTrace ++ - new chipyard.config.WithUART ++ - new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ - new testchipip.WithTSI ++ - new testchipip.WithBlockDevice ++ - new chipyard.config.WithL2TLBs(1024) ++ - new WithoutClockGating ++ new WithDefaultMemModel ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new WithFireSimConfigTweaks ++ + new chipyard.RocketConfig) + +class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ - new WithFireSimTop ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.system.BaseConfig -) + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.QuadRocketConfig) -// A safer implementation than the one in BOOM in that it -// duplicates whatever BOOMTileKey.head is present N times. This prevents -// accidentally (and silently) blowing away configurations that may change the -// tile in the "up" view -class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => { - case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i)) - case MaxHartIdBits => log2Up(site(BoomTilesKey).size) -}) -class FireSimBoomDualCoreConfig extends Config( - new WithNDuplicatedBoomCores(2) ++ - new FireSimBoomConfig) +//***************************************************************** +// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig +//***************************************************************** +class FireSimSha3RocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.Sha3RocketConfig) -class FireSimBoomQuadCoreConfig extends Config( - new WithNDuplicatedBoomCores(4) ++ - new FireSimBoomConfig) +class FireSimSha3PrintfRocketConfig extends Config( + new sha3.WithSha3Printf ++ + new FireSimSha3RocketConfig) + +//***************************************************************** +// Boom config, base off chipyard's LargeBoomConfig +//***************************************************************** +class FireSimLargeBoomConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LargeBoomConfig) + + +//******************************************************************** +// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig +//******************************************************************** +class FireSimLargeBoomAndRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LargeBoomAndRocketConfig) + +//****************************************************************** +// Gemmini NN accel config, base off chipyard's GemminiRocketConfig +//****************************************************************** +class FireSimGemminiRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.GemminiRocketConfig) //********************************************************************************** -//* Heterogeneous Configurations -//*********************************************************************************/ - -// dual core config (rocket + small boom) -class FireSimRocketBoomConfig extends Config( - new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) - new boom.common.WithRenumberHarts ++ // fix hart numbering - new boom.common.WithSmallBooms ++ // change single BOOM to small - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new FireSimBoomConfig -) - +// Supernode Configurations, base off chipyard's RocketConfig //********************************************************************************** -//* Gemmini Configurations -//*********************************************************************************/ - -// Gemmini systolic accelerator default config -class FireSimRocketChipGemminiL2Config extends Config( - new WithInclusiveCache ++ - new gemmini.DefaultGemminiConfig ++ - new WithNBigCores(1) ++ - new FireSimRocketChipConfig) - - -//********************************************************************************** -//* Supernode Configurations -//*********************************************************************************/ - -class SupernodeFireSimRocketChipConfig extends Config( +class SupernodeFireSimRocketConfig extends Config( new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipConfig) - -class SupernodeFireSimRocketChipSingleCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipSingleCoreConfig) - -class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config( - new WithNumNodes(6) ++ - new WithExtMemSize(0x40000000L) ++ // 1GB - new FireSimRocketChipSingleCoreConfig) - -class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config( - new WithNumNodes(8) ++ - new WithExtMemSize(0x40000000L) ++ // 1GB - new FireSimRocketChipSingleCoreConfig) - -class SupernodeFireSimRocketChipDualCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipDualCoreConfig) - -class SupernodeFireSimRocketChipQuadCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipQuadCoreConfig) - -class SupernodeFireSimRocketChipHexaCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipHexaCoreConfig) - -class SupernodeFireSimRocketChipOctaCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipOctaCoreConfig) + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB + new FireSimRocketConfig) diff --git a/generators/firechip/src/main/scala/TargetTraits.scala b/generators/firechip/src/main/scala/TargetTraits.scala deleted file mode 100644 index 126dee1f..00000000 --- a/generators/firechip/src/main/scala/TargetTraits.scala +++ /dev/null @@ -1,74 +0,0 @@ -package firesim.firesim - -import chisel3._ -import chisel3.util.Cat -import chisel3.experimental.annotate -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile.RocketTile -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.rocket.TracedInstruction -import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} - -import midas.targetutils.MemModelAnnotation - -import boom.common.BoomTile - -/* Wires out tile trace ports to the top; and wraps them in a Bundle that the - * TracerV bridge can match on. - */ -object PrintTracePort extends Field[Boolean](false) - -trait HasTraceIO { - this: HasTiles => - val module: HasTraceIOImp - - // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp - val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]] - val tileTraceNodes = tiles.map(tile => tile.traceNode) - tileTraceNodes foreach { traceNexus := _ } -} - -trait HasTraceIOImp extends LazyModuleImp { - val outer: HasTraceIO - - val traceIO = IO(Output(new TraceOutputTop( - DeclockedTracedInstruction.fromNode(outer.traceNexus.in)))) - (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => - port := DeclockedTracedInstruction.fromVec(tileTrace) - }) - - // Enabled to test TracerV trace capture - if (p(PrintTracePort)) { - val traceprint = Wire(UInt(512.W)) - traceprint := Cat(traceIO.traces.map(_.reverse.asUInt)) - printf("TRACEPORT: %x\n", traceprint) - } -} - -trait CanHaveMultiCycleRegfileImp { - val outer: chipyard.HasBoomAndRocketTiles - - outer.tiles.map { - case r: RocketTile => { - annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) - r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) - } - case b: BoomTile => { - val core = b.module.core - core.iregfile match { - case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) - case _ => Nil - } - if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { - case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) - case _ => Nil - } - } - } -} - diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index bdbda075..6961782a 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -39,30 +39,5 @@ import FireSimValName._ * determine which driver to build. *******************************************************************************/ -class FireSimDUT(implicit p: Parameters) extends chipyard.Top - with HasTraceIO -{ - override lazy val module = new FireSimModuleImp(this) -} - -class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp class FireSim(implicit p: Parameters) extends DefaultFireSimHarness - - -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness -{ - throw new Exception("FireSimNoNIC is deprecated. Please add WithNoNIC to your TARGET_CONFIG and set DESIGN=FireSim to build a NoNIC simulator") -} - - -object FireSimTypeAliases { - // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 - type FireSimSupernode = FireSim - - // Verilog blackbox integration demo - type FireSimVerilogGCD = FireSim -} -import FireSimTypeAliases._ diff --git a/generators/testchipip b/generators/testchipip index ff1daef0..a3da53e8 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ff1daef09f2f9c2fdea5e93a3b38c58a226b7b3c +Subproject commit a3da53e87ad890be37138e27e477eb9a563fa82e From c12819eb5235281b3a0d53883038498a07ab42e3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Feb 2020 11:40:10 -0800 Subject: [PATCH 15/50] Update docs --- docs/Advanced-Concepts/Chip-Communication.rst | 9 +- docs/Advanced-Concepts/Top-Testharness.rst | 10 +- docs/Chipyard-Basics/Chipyard-Components.rst | 6 +- .../Configs-Parameters-Mixins.rst | 53 ++---- .../Chipyard-Basics/Development-Ecosystem.rst | 2 +- docs/Customization/Custom-Chisel.rst | 4 +- docs/Customization/DMA-Devices.rst | 8 +- docs/Customization/Heterogeneous-SoCs.rst | 8 +- .../Incorporating-Verilog-Blocks.rst | 12 +- docs/Customization/Keys-Traits-Configs.rst | 41 +---- docs/Customization/MMIO-Peripherals.rst | 24 +-- docs/Customization/Memory-Hierarchy.rst | 169 +++++++++--------- docs/Generators/Gemmini.rst | 4 +- docs/Generators/Rocket-Chip.rst | 7 +- docs/Generators/SHA3.rst | 2 +- docs/Generators/SiFive-Generators.rst | 6 +- docs/Generators/TestChipIP.rst | 7 +- docs/Generators/index.rst | 2 +- docs/Quick-Start.rst | 65 ------- docs/Simulation/Software-RTL-Simulation.rst | 6 +- docs/Software/FireMarshal.rst | 1 + .../NodeTypes.rst | 12 +- .../Register-Router.rst | 14 +- docs/TileLink-Diplomacy-Reference/index.rst | 2 +- docs/Tools/FIRRTL.rst | 1 - docs/Tools/index.rst | 2 +- docs/VLSI/Advanced-Usage.rst | 4 +- docs/index.rst | 67 ++++++- 28 files changed, 247 insertions(+), 301 deletions(-) delete mode 100644 docs/Quick-Start.rst diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 29979900..fe9b6f57 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -109,16 +109,13 @@ reminder, to run a software RTL simulation, run: FireSim FPGA-accelerated simulations use TSI by default as well. -If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must create a -top-level system with the DTM (``TopWithDTM``), a test-harness to connect to the DTM (``TestHarnessWithDTM``), as well as a config to use that top-level system. +If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDTM` instead of `WithTiedOffDebug ++ WithSimSerial`. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: DmiRocket :end-before: DOC include end: DmiRocket -In this example, the ``WithDTM`` mixin specifies that the top-level SoC will instantiate a DTM (that by default is setup to use DMI). -The rest of the mixins specify the rest of the system (cores, accelerators, etc). Then you can run simulations with the new DMI-enabled top-level and test-harness. .. code-block:: bash @@ -144,7 +141,7 @@ The configuration is very similar to a DMI-based configuration. The main differe is the addition of the ``WithJtagDTM`` mixin that configures the instantiated DTM to use the JTAG protocol as the bringup method. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: JtagRocket :end-before: DOC include end: JtagRocket diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 3d22e54a..43b0be51 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -27,7 +27,7 @@ We also see this class define several ``ElaborationArtefacts``, files emitted af Subsystem ^^^^^^^^^^^^^^^^^^^^^^^^^ -Looking in `generators/utilities/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` +Looking in `generators/chipyard/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that defines and instantiates BOOM or Rocket tiles, depending on the parameters specified. We also connect some basic IOs for each tile here, specifically the hartids and the reset vector. @@ -35,7 +35,7 @@ We also connect some basic IOs for each tile here, specifically the hartids and System ^^^^^^^^^^^^^^^^^^^^^^^^^ -``generators/utilities/src/main/scala/System.scala`` completes the definition of the ``System``. +``generators/chipyard/src/main/scala/System.scala`` completes the definition of the ``System``. - ``HasHierarchicalBusTopology`` is defined in Rocket Chip, and specifies connections between the top-level buses - ``HasAsyncExtInterrupts`` and ``HasExtInterruptsModuleImp`` adds IOs for external interrupts and wires them appropriately to tiles @@ -45,7 +45,7 @@ System Tops ^^^^^^^^^^^^^^^^^^^^^^^^^ -A SoC Top then extends the ``System`` class with any config-specific components. +A SoC Top then extends the ``System`` class with traits for custom components. In Chipyard, this includes things like adding a NIC, UART, and GPIO as well as setting up the hardware for the bringup method. Please refer to :ref:`Communicating with the DUT` for more information on these bringup methods. @@ -55,7 +55,7 @@ TestHarness The wiring between the ``TestHarness`` and the Top are performed in methods defined in mixins added to the Top. When these methods are called from the ``TestHarness``, they may instantiate modules within the scope of the harness, and then connect them to the DUT. For example, the ``connectSimAXIMem`` method defined in the -``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMem``s +``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMems`` and connect them to the correct IOs of the top. While this roundabout way of attaching to the IOs of the top may seem to be unnecessarily complex, it allows the designer to compose @@ -66,4 +66,4 @@ TestDriver The ``TestDriver`` is defined in ``generators/rocketchip/src/main/resources/vsrc/TestDriver.v``. This Verilog file executes a simulation by instantiating the ``TestHarness``, driving the clock and reset signals, and interpreting the success output. -This file is compiled with the generated Verilog for the ``TestHarness`` and the Top to produce a simulator. +This file is compiled with the generated Verilog for the ``TestHarness`` and the ``Top`` to produce a simulator. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 29828e44..cbca299f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -29,9 +29,9 @@ Accelerators Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. See :ref:`Hwacha` for more information. -.. Fixed Function Accelerators: - ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - TBD +**Gemmini** + A matrix-multiply accelerator targeting neural-networks + **SHA3** A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the Chipyard integration flows using the RoCC interface. diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index 6b8d0aca..e72a7444 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -74,52 +74,37 @@ Cake Pattern A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). It is used in the Rocket Chip SoC library and Chipyard framework in merging multiple system components and IO interfaces into a large system component. -This example shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design. +This example shows the Chipyard default top that composes multiple traits together into a fully-featured SoC with many optional components. -.. _cake-example: -.. code-block:: scala - class MySoC(implicit p: Parameters) extends RocketSubsystem - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with HasNoDebug - with HasPeripherySerial - with HasPeripheryUART - with HasPeripheryIceNIC - { - lazy val module = new MySoCModuleImp(this) - } +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala + :language: scala + :start-after: DOC include start: Top + :end-before: DOC include end: Top - class MySoCModuleImp(outer: MySoC) extends RocketSubsystemModuleImp(outer) - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with HasPeripheryUARTModuleImp - with HasPeripheryIceNICModuleImp -There are two "cakes" here. One for the lazy module (ex. ``HasPeripherySerial``) and one for the lazy module -implementation (ex. ``HasPeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines +There are two "cakes" here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module +implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. -In the ``MySoC`` example class, the "outer" ``MySoC`` instantiates the "inner" -``MySoCModuleImp`` as a lazy module implementation. This delays immediate elaboration +In the ``Top`` example class, the "outer" ``Top`` instantiates the "inner" +``TopModule`` as a lazy module implementation. This delays immediate elaboration of the module until all logical connections are determined and all configuration information is exchanged. -The ``RocketSubsystem`` outer base class, as well as the -``HasPeripheryX`` outer traits contain code to perform high-level logical -connections. For example, the ``HasPeripherySerial`` outer trait contains code -to lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s +The ``Syatem`` outer base class, as well as the +``CanHavePeripheryX`` outer traits contain code to perform high-level logical +connections. For example, the ``CanHavePeripherySerial`` outer trait contains code +to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s TileLink node to the Front bus. The ``ModuleImp`` classes and traits perform elaboration of real RTL. -For example, the ``HasPeripherySerialModuleImp`` trait physically connects +For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically connects the ``SerialAdapter`` module, and instantiates queues. In the test harness, the SoC is elaborated with -``val dut = Module(LazyModule(MySoC))``. -After elaboration, the result will be a ``MySoC`` module, which contains a -``SerialAdapter`` module (among others). +``val dut = Module(LazyModule(Top))``. +After elaboration, the result will be a ``Top`` module, which contains a +``SerialAdapter`` module (among others), if the config specified for that block to be instantiated. From a high level, classes which extend ``LazyModule`` *must* reference their module implementation through ``lazy val module``, and they @@ -134,8 +119,8 @@ Mix-in --------------------------- A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convention for an additive mix-in is ``Has``. -This is shown in the ``MySoC`` class where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. +The naming convention for an additive mix-in is ``CanHave``. +This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. Additional References --------------------------- diff --git a/docs/Chipyard-Basics/Development-Ecosystem.rst b/docs/Chipyard-Basics/Development-Ecosystem.rst index b0cb557d..087fde6e 100644 --- a/docs/Chipyard-Basics/Development-Ecosystem.rst +++ b/docs/Chipyard-Basics/Development-Ecosystem.rst @@ -16,7 +16,7 @@ Chisel is an embedded language within Scala that provides a set of libraries to FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more! These two tools in combination allow quick design space exploration and development of new RTL. -Generators +RTL Generators ------------------------------------------- Within this repository, all of the Chisel RTL is written as generators. diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst index feec3141..4ffbafbf 100644 --- a/docs/Customization/Custom-Chisel.rst +++ b/docs/Customization/Custom-Chisel.rst @@ -52,8 +52,8 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file. You can then import the classes defined in the submodule in a new project if you add it as a dependency. For instance, if you want to use this code in -the ``example`` project, change the final line in build.sbt to the following. +the ``chipyard`` project, change the final line in build.sbt to the following. .. code-block:: scala - lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) + lazy val chipyard = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) diff --git a/docs/Customization/DMA-Devices.rst b/docs/Customization/DMA-Devices.rst index f2e95e52..ed5678c9 100644 --- a/docs/Customization/DMA-Devices.rst +++ b/docs/Customization/DMA-Devices.rst @@ -12,10 +12,10 @@ having the CPU poll data from the device, we may want to have the device write directly to the coherent memory system instead. For example, here is a device that writes zeros to the memory at a configured address. -.. literalinclude:: ../../generators/example/src/main/scala/InitZero.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/InitZero.scala :language: scala -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top @@ -26,12 +26,12 @@ For more info on creating TileLink client nodes, take a look at :ref:`Client Nod Once we've created our top-level module including the DMA widget, we can create a configuration for it as we did before. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/InitZero.scala :language: scala :start-after: DOC include start: WithInitZero :end-before: DOC include end: WithInitZero -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: InitZeroRocketConfig :end-before: DOC include end: InitZeroRocketConfig diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index e1d58c6a..8087fd35 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -13,7 +13,7 @@ When used together you can create a heterogeneous system. The following example shows a dual core BOOM with a single core Rocket. -.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala :language: scala :start-after: DOC include start: DualBoomAndRocket :end-before: DOC include end: DualBoomAndRocket @@ -72,7 +72,7 @@ Adding Hwachas Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter. An example of adding a Hwacha to all tiles in the system is below. -.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala :language: scala :start-after: DOC include start: BoomAndRocketWithHwacha :end-before: DOC include end: BoomAndRocketWithHwacha @@ -83,12 +83,12 @@ All with the same Hwacha parameters. Assigning Accelerators to Specific Tiles with MultiRoCC ------------------------------------------------------- -Located in ``generators/example/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. +Located in ``generators/chipyard/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. -.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala :language: scala :start-after: DOC include start: DualBoomAndRocketOneHwacha :end-before: DOC include end: DualBoomAndRocketOneHwacha diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst index fc1b8d7d..bca9d067 100644 --- a/docs/Customization/Incorporating-Verilog-Blocks.rst +++ b/docs/Customization/Incorporating-Verilog-Blocks.rst @@ -48,12 +48,12 @@ Verilog files into the build process, which are part of the .settings(commonSettings) For this concrete GCD example, we will be using a ``GCDMMIOBlackBox`` -Verilog module that is defined in the ``example`` project. The Scala +Verilog module that is defined in the ``chipyard`` project. The Scala and Verilog sources follow the prescribed directory layout. .. code-block:: none - generators/example/ + generators/chipyard/ build.sbt src/main/ scala/ @@ -81,14 +81,14 @@ as the bitwidth of the GCD calculation does in this example. **Verilog GCD port list and parameters** -.. literalinclude:: ../../generators/example/src/main/resources/vsrc/GCDMMIOBlackBox.v +.. literalinclude:: ../../generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v :language: Verilog :start-after: DOC include start: GCD portlist :end-before: DOC include end: GCD portlist **Chisel BlackBox Definition** -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD blackbox :end-before: DOC include end: GCD blackbox @@ -103,7 +103,7 @@ peripheral-specific traits into a ``TLRegisterRouter``. The ``params`` member and ``HasRegMap`` base trait should look familiar from the previous memory-mapped GCD device example. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD instance regmap :end-before: DOC include end: GCD instance regmap @@ -115,7 +115,7 @@ Defining a Chip with a BlackBox Since we've parameterized the GCD instantiation to choose between the Chisel and the Verilog module, creating a config is easy. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDAXI4BlackBoxRocketConfig :end-before: DOC include end: GCDAXI4BlackBoxRocketConfig diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index e7705f44..bac311c5 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -16,7 +16,7 @@ Keys specify some parameter which controls some custom widget. Keys should typic Keys should be defined and documented in sub-projects, since they generally deal with some specific block, and not system-level integration. (We make an exception for the example GCD widget). -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD key :end-before: DOC include end: GCD key @@ -24,7 +24,7 @@ Keys should be defined and documented in sub-projects, since they generally deal The object within a key is typically a ``case class XXXParams``, which defines a set of parameters which some block accepts. For example, the GCD widget's ``GCDParams`` parameterizes its address, operand widths, whether the widget should be connected by Tilelink or AXI4, and whether the widget should use the blackbox-Verilog implementation, or the Chisel implementation. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD params :end-before: DOC include end: GCD params @@ -42,14 +42,14 @@ Top-level traits should be defined and documented in subprojects, alongside thei Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD imp trait These traits are added to the default ``Top`` in Chipyard. -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top @@ -57,49 +57,22 @@ These traits are added to the default ``Top`` in Chipyard. Mixins ------ -Mixins set the keys to a non-default value. Together, the collection of Mixins which define a configuration generate the values for all the keys used by the generator. +Config mixins set the keys to a non-default value. Together, the collection of Mixins which define a configuration generate the values for all the keys used by the generator. For example, the ``WithGCDMixin`` is parameterized by the type of GCD widget you want to instantiate. When this mixin is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD mixin :end-before: DOC include end: GCD mixin We can use this mixin when composing our configs. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDTLRocketConfig :end-before: DOC include end: GCDTLRocketConfig - -BuildTop --------- - -The ``BuildTop`` key is special, because sometimes, we need to instantiate ``TestHarness`` modules to interface with a custom widget. The ``BuildTop`` key provides a function which can call some method of the Top to instantiate these ``TestHarness`` modules. Since the ``BuildTop`` key is called from the ``TestHarness``, these modules will appear in the ``TestHarness``. The config system also lets the ``BuildTop`` key look recursively into previous definitions of itself. This enables composability of the ``Top`` configurations. - -For example, conside a config that contains the mixins ``WithGPIO ++ WithTSI``. We need to instantiate the TSI serial adapter, and connect it to the ``success`` signal of our ``TestHarness``. We also need to instantiate the GPIO pins, and tie their inputs to 0 in the ``TestHarness``, since we currently cannot drive the GPIOs in simulation. - -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala - :language: scala - :start-after: DOC include start: tsi mixin - :end-before: DOC include end: tsi mixin - - -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala - :language: scala - :start-after: DOC include start: gpio mixin - :end-before: DOC include end: gpio mixin - -When ``WithGPIO ++ WithTSI`` is evaluated right to left, the call to ``up(BuildTop, site)`` in ``WithGPIO`` will reference the function defined in the ``BuildTop`` key of ``WithTSI``. Thus, at elaboration time, when the ``BuildTop`` function is called by the ``TestHarness``, first the ``BuildTop`` function in ``WithTSI`` will be evaluated. This connects the ``success`` signal of the ``TestHarness`` to the ``SerialAdapter`` enabled by ``WithTSI``. Then, the rest of the code in the ``BuildTop`` function of ``WithGPIO`` will execute, tieing off the top-level GPIO input pins. Thus the evaluation of the ``BuildTop`` functions in a completed config is "right-to-left", matching how the evaluation of the mixins at compile-time is also "right-to-left". - -.. warning:: - In some cases, the ordering and duplication of mixins which extend ``BuildTop`` will have unintended consequences. - For example, ``WithTSI ++ WithTSI`` will attempt to generate and connect two ``SimSerial`` widgets in the ``TestHarness``, - which will likely break the simulation. - In general, you should avoid attaching multiple mixins which interface to the same top-level ports. - .. note:: Readers who want more information on the configuration system may be interested in reading :ref:`cdes`. diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index 23fddca4..c1c1a424 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -3,21 +3,21 @@ MMIO Peripherals ================== -The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/example/src/main/scala/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. +The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. For this example, we will show how to connect a MMIO peripheral which computes the GCD. -The full code can be found in ``generators/example/src/main/scala/GCD.scala``. +The full code can be found in ``generators/chipyard/src/main/scala/GCD.scala``. In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDModule`` class only creates the registers and hooks them up using ``regmap``. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD chisel :end-before: DOC include end: GCD chisel -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD instance regmap :end-before: DOC include end: GCD instance regmap @@ -51,7 +51,7 @@ The second set of arguments is the IO bundle constructor, which we create by ext The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. Notice how we can create an analogous AXI4 version of our peripheral. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD router :end-before: DOC include end: GCD router @@ -69,7 +69,7 @@ In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait a The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated. For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD lazy trait @@ -82,7 +82,7 @@ Also observe how we have to place additional AXI4 buffers and converters for the For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD imp trait :end-before: DOC include end: GCD imp trait @@ -91,9 +91,9 @@ Constructing the Top and Config ------------------------------- Now we want to mix our traits into the system as a whole. -This code is from ``generators/example/src/main/scala/Top.scala``. +This code is from ``generators/chipyard/src/main/scala/Top.scala``. -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top @@ -105,14 +105,14 @@ The ``TopModule`` class is the actual RTL that gets synthesized. -And finally, we create a configuration class in ``generators/example/src/main/scala/Configs.scala`` that uses the ``WithGCD`` mixin defined earlier. +And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` mixin defined earlier. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD mixin :end-before: DOC include end: GCD mixin -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDTLRocketConfig :end-before: DOC include end: GCDTLRocketConfig diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 6266e435..26bce436 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -14,25 +14,43 @@ configure 4 KiB direct-mapped caches for L1I and L1D. .. code-block:: scala - class SmallRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores - new freechips.rocketchip.system.BaseConfig) + class SmallRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores + new freechips.rocketchip.system.BaseConfig) + + class MediumRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNMediumCores(1) ++ // Medium rocket cores + new freechips.rocketchip.system.BaseConfig) + - class MediumRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNMedCores(1) ++ // medium rocket cores - new freechips.rocketchip.system.BaseConfig) If you only want to change the size or associativity, there are configuration mixins for those too. @@ -42,18 +60,11 @@ mixins for those too. import freechips.rocketchip.subsystem.{WithL1ICacheSets, WithL1DCacheSets, WithL1ICacheWays, WithL1DCacheWays} class MyL1RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithL1ICacheSets(128) ++ // change rocket I$ - new WithL1ICacheWays(2) ++ // change rocket I$ - new WithL1DCacheSets(128) ++ // change rocket D$ - new WithL1DCacheWays(2) ++ // change rocket D$ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithL1ICacheSets(128) ++ // change rocket I$ + new freechips.rocketchip.subsystem.WithL1ICacheWays(2) ++ // change rocket I$ + new freechips.rocketchip.subsystem.WithL1DCacheSets(128) ++ // change rocket D$ + new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++ // change rocket D$ + new RocketConfig) You can also configure the L1 data cache as an data scratchpad instead. However, there are some limitations on this. If you are using a data scratchpad, @@ -62,22 +73,26 @@ Note that these configurations fully remove the L2 cache and mbus. .. code-block:: scala - class SmallRocketConfigNoL2 extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + class ScratchpadSmallRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.system.BaseConfig) - class ScratchpadRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ - new SmallRocketConfigNoL2) This configuration fully removes the L2 cache and memory bus by setting the number of channels and number of banks to 0. @@ -92,23 +107,8 @@ set-associativity. However, you can change these parameters to obtain your desired cache configuration. The main restriction is that the number of ways and the number of banks must be powers of 2. -.. code-block:: scala - - import freechips.rocketchip.subsystem.WithInclusiveCache - - class MyCacheRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithInclusiveCache( // add 1MB, 4-way, 4-bank cache - capacityKB = 1024, - nWays = 4, - nBanks = 4) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) +Refer to the ``CacheParameters`` object defined in sifive-cache for +customization options. The Broadcast Hub ----------------- @@ -120,28 +120,29 @@ To make such a configuration, you can just copy the definition of ``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the list of included mixims. -.. code-block:: scala - - class CachelessRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - If you want to reduce the resources used even further, you can configure the Broadcast Hub to use a bufferless design. .. code-block:: scala - import freechips.rocketchip.subsystem.WithBufferlessBroadcastHub + class NoL2SmallRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithBufferlessBroadcastHub ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.system.BaseConfig) - class BufferlessRocketConfig extends Config( - new WithBufferlessBroadcastHub ++ - new CachelessRocketConfig) The Outer Memory System ----------------------- @@ -158,15 +159,9 @@ number of DRAM channels is restricted to powers of two. import freechips.rocketchip.subsystem.WithNMemoryChannels class DualChannelRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithNMemoryChannels(2) ++ // multi-channel outer mem - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ + new RocketConfig) + In VCS and Verilator simulation, the DRAM is simulated using the ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 66f8e017..fe126f02 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -9,7 +9,7 @@ To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConf The example Chipyard config includes the following example SoC configuration which includes Gemmini: -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GemminiRocketConfig :end-before: DOC include end: GemminiRocketConfig @@ -42,7 +42,7 @@ Major parameters of interest include: * DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``): Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. -Software +Gemmini Software ------------------ The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__. diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst index 1509b9d7..084a5634 100644 --- a/docs/Generators/Rocket-Chip.rst +++ b/docs/Generators/Rocket-Chip.rst @@ -58,8 +58,8 @@ The ``PeripheryBus`` attaches additional peripherals like the NIC and Block Devi It can also optionally expose an external AXI4 port, which can be attached to vendor-supplied AXI4 IP. -To learn more about adding MMIO peripherals, check out the :ref:`MMIO Peripheral` -section of :ref:`Adding an Accelerator/Device`. +To learn more about adding MMIO peripherals, check out the :ref:`mmio-accelerators` +section. DMA --- @@ -68,5 +68,4 @@ You can also add DMA devices that read and write directly from the memory system. These are attached to the ``FrontendBus``. The ``FrontendBus`` can also connect vendor-supplied AXI4 DMA devices through an AXI4 to TileLink converter. -To learn more about adding DMA devices, see the :ref:`Adding a DMA port` section -of :ref:`Adding an Accelerator/Device`. +To learn more about adding DMA devices, see the :ref:`dma-devices` section. diff --git a/docs/Generators/SHA3.rst b/docs/Generators/SHA3.rst index a9b87108..c8969c3a 100644 --- a/docs/Generators/SHA3.rst +++ b/docs/Generators/SHA3.rst @@ -72,7 +72,7 @@ it can be mixed into a Rocket or BOOM core by overriding the generator. An example configuration highlighting the use of this mixin is shown here: -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: Sha3Rocket :end-before: DOC include end: Sha3Rocket diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index 19360162..35b160f8 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -18,7 +18,7 @@ Peripheral Devices These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigMixins.scala :language: scala :start-after: DOC include start: gpio mixin :end-before: DOC include end: gpio mixin @@ -26,12 +26,12 @@ To integrate one of these devices in your SoC, you will need to define a custom Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC. When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. -This example instantiates a top-level module with include GPIO ports (``TopWithGPIO``), and then ties-off the GPIO port inputs to 0 (``false.B``). +This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). Finally, you add the relevant config mixin to the SoC config. For example: -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GPIORocketConfig :end-before: DOC include end: GPIORocketConfig diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 13b516e3..0e02c077 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -22,9 +22,7 @@ The block device controller provides a generic interface for secondary storage. This device is primarily used in FireSim to interface with a block device software simulation model. The default Linux configuration in `firesim-software `_ -To add a block device to your design, add ``HasPeripheryBlockDevice`` to your -lazy module and ``HasPeripheryBlockDeviceModuleImp`` to the implementation. -Then add the ``WithBlockDevice`` config mixin to your configuration. +To add a block device to your design, add the ``WithBlockDevice`` config mixin to your configuration. TileLink SERDES @@ -71,5 +69,4 @@ during Linux boot). In addition to working with ``stdin/stdout`` of the host, it output a UART log to a particular file using ``+uartlog=`` during simulation. By default, this UART Adapter is added to all systems within Chipyard by adding the -``CanHavePeripheryUARTWithAdapter`` and ``CanHavePeripheryUARTWithAdapterImp`` traits to the ``Top`` system. -These traits add a SiFive UART to the system as well as add the UART Adapter to the TestHarness. +``WithUART`` and ``WithUARTAdapter`` configs. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 5bb5d491..90db4ae8 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -1,6 +1,6 @@ .. _generator-index: -Generators +Included RTL Generators ============================ A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst deleted file mode 100644 index cc650bd6..00000000 --- a/docs/Quick-Start.rst +++ /dev/null @@ -1,65 +0,0 @@ -Quick Start -=============================== - -Requirements -------------------------------------------- - -Chipyard is developed and tested on Linux-based systems. - -.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. - -.. Warning:: Working under Windows is not recommended. - -Setting up the Chipyard Repo -------------------------------------------- - -Start by fetching Chipyard's sources. Run: - -.. code-block:: shell - - git clone https://github.com/ucb-bar/chipyard.git - cd chipyard - ./scripts/init-submodules-no-riscv-tools.sh - -This will initialize and checkout all of the necessary git submodules. - -Installing the RISC-V Tools -------------------------------------------- - -We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. -This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. -To build the toolchains, you should run: - -.. code-block:: shell - - ./scripts/build-toolchains.sh - -.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. - -Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: - -.. code-block:: shell - - source ./env.sh - -What's Next? -------------------------------------------- - -This depends on what you are planning to do with Chipyard. - -* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. - -* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. - -* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. - -* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. - -* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. - -* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. - -* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. - -* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 4ad0342e..9bc236ac 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -49,16 +49,16 @@ Simulating The Default Example To compile the example design, run ``make`` in the selected verilator or VCS directory. This will elaborate the ``RocketConfig`` in the example project. -An executable called ``simulator-example-RocketConfig`` will be produced. +An executable called ``simulator-chipyard-RocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell - ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + ./simulator-chipyard-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -.. Note:: In a VCS simulator, the simulator name will be ``simv-example-RocketConfig`` instead of ``simulator-example-RocketConfig``. +.. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: diff --git a/docs/Software/FireMarshal.rst b/docs/Software/FireMarshal.rst index dc53b77d..87dede12 100644 --- a/docs/Software/FireMarshal.rst +++ b/docs/Software/FireMarshal.rst @@ -1,4 +1,5 @@ .. _fire-marshal: + FireMarshal ================= diff --git a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst index be3fb33d..ff80f937 100644 --- a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst +++ b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst @@ -17,7 +17,7 @@ The L1 caches and DMA devices in RocketChip/Chipyard have client nodes. You can add a TileLink client node to your LazyModule using the TLHelper object from testchipip like so: -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClient :end-before: DOC include end: MyClient @@ -66,7 +66,7 @@ TileLink managers take requests from clients on the A channel and send responses back on the D channel. You can create a manager node using the TLHelper like so: -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyManager :end-before: DOC include end: MyManager @@ -146,7 +146,7 @@ to the outputs unchanged. This node is mainly used to combine multiple nodes into a single node with multiple edges. For instance, say we have two client lazy modules, each with their own client node. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClient1+MyClient2 :end-before: DOC include end: MyClient1+MyClient2 @@ -154,21 +154,21 @@ client lazy modules, each with their own client node. Now we instantiate these two clients in another lazy module and expose their nodes as a single node. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClientGroup :end-before: DOC include end: MyClientGroup We can also do the same for managers. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyManagerGroup :end-before: DOC include end: MyManagerGroup If we want to connect the client and manager groups together, we can now do this. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClientManagerComplex :end-before: DOC include end: MyClientManagerComplex diff --git a/docs/TileLink-Diplomacy-Reference/Register-Router.rst b/docs/TileLink-Diplomacy-Reference/Register-Router.rst index cc735578..7e28196f 100644 --- a/docs/TileLink-Diplomacy-Reference/Register-Router.rst +++ b/docs/TileLink-Diplomacy-Reference/Register-Router.rst @@ -11,14 +11,14 @@ for exposing registers themselves, it's much easier to use RocketChip's ``regmap`` interface, which can generate most of the glue logic. For TileLink devices, you can use the ``regmap`` interface by extending -the ``TLRegisterRouter`` class, as shown in :ref:`Adding An Accelerator/Device`, +the ``TLRegisterRouter`` class, as shown in :ref:`mmio-accelerators`, or you can create a regular LazyModule and instantiate a ``TLRegisterNode``. This section will focus on the second method. Basic Usage ----------- -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyDeviceController :end-before: DOC include end: MyDeviceController @@ -56,7 +56,7 @@ register. The ``RegField`` interface also provides support for reading and writing ``DecoupledIO`` interfaces. For instance, you can implement a hardware FIFO like so. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyQueueRegisters :end-before: DOC include end: MyQueueRegisters @@ -71,7 +71,7 @@ You need not specify both read and write for a register. You can also create read-only or write-only registers. So for the previous example, if you wanted enqueue and dequeue to use different addresses, you could write the following. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MySeparateQueueRegisters :end-before: DOC include end: MySeparateQueueRegisters @@ -93,7 +93,7 @@ You can also create registers using functions. Say, for instance, that you want to create a counter that gets incremented on a write and decremented on a read. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyCounterRegisters :end-before: DOC include end: MyCounterRegisters @@ -107,7 +107,7 @@ You can also pass functions that decouple the read/write request and response. The request will appear as a decoupled input and the response as a decoupled output. So for instance, if we wanted to do this for the previous example. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyCounterReqRespRegisters :end-before: DOC include end: MyCounterReqRespRegisters @@ -131,7 +131,7 @@ change the protocol being used. For instance, in the first example in :ref:`Basic Usage`, you could simply change the ``TLRegisterNode`` to and ``AXI4RegisterNode``. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyAXI4DeviceController :end-before: DOC include end: MyAXI4DeviceController diff --git a/docs/TileLink-Diplomacy-Reference/index.rst b/docs/TileLink-Diplomacy-Reference/index.rst index 23a5a175..dfc2ec5a 100644 --- a/docs/TileLink-Diplomacy-Reference/index.rst +++ b/docs/TileLink-Diplomacy-Reference/index.rst @@ -11,7 +11,7 @@ elaboration scheme. For a detailed explanation of Diplomacy, see `the paper by Cook, Terpstra, and Lee `_. A brief overview of how to connect simple TileLink widgets can be found -in the :ref:`Adding-an-Accelerator` section. This section will provide a +in the :ref:`mmio-accelerators` section. This section will provide a detailed reference for the TileLink and Diplomacy functionality provided by RocketChip. diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst index a434ca0e..e9e6425a 100644 --- a/docs/Tools/FIRRTL.rst +++ b/docs/Tools/FIRRTL.rst @@ -1,4 +1,3 @@ -.. _firrtl: FIRRTL ================================ diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index efe38e34..09fd0d04 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -1,4 +1,4 @@ -Tools +Development Tools ============================== The Chipyard framework relays heavily on a set of Scala-based tools. diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index 6ab44c02..b78eda54 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -49,6 +49,6 @@ Say you need to update some power straps settings in ``example.yml`` and want to make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' -Simulation ----------- +RTL and Gate-level Simulation +----------------------------- With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. diff --git a/docs/index.rst b/docs/index.rst index dd7afe52..a98c3088 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -12,8 +12,73 @@ Chipyard is a a framework for designing and evaluating full-system hardware usin It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. -.. include:: Quick-Start.rst +Quick Start +=============================== +System Requirements +------------------------------------------- + +Chipyard is developed and tested on Linux-based systems. + +.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. + +.. Warning:: Working under Windows is not recommended. + +Setting up the Chipyard Repo +------------------------------------------- + +Start by fetching Chipyard's sources. Run: + +.. code-block:: shell + + git clone https://github.com/ucb-bar/chipyard.git + cd chipyard + ./scripts/init-submodules-no-riscv-tools.sh + +This will initialize and checkout all of the necessary git submodules. + +Installing the RISC-V Tools +------------------------------------------- + +We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. +This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. +To build the toolchains, you should run: + +.. code-block:: shell + + ./scripts/build-toolchains.sh + +.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. + +Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: + +.. code-block:: shell + + source ./env.sh + +What's Next? +------------------------------------------- + +This depends on what you are planning to do with Chipyard. + +* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. + +* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. + +* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. + +* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. + +* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. + +* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. + +* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. + +* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. + + Getting Help ------------ From 701ea7c355f221146931d4c33577416cb1d3a435 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Feb 2020 12:31:36 -0800 Subject: [PATCH 16/50] Add new type of IOBinder macro --- .../chipyard/src/main/scala/IOBinders.scala | 36 +++++++++++++++++++ .../src/main/scala/BridgeBinders.scala | 4 +-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 969230b7..327db301 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -18,8 +18,31 @@ import tracegen.{HasTraceGenTilesModuleImp} import scala.reflect.{ClassTag, classTag} +// System for instantiating binders based +// on the scala type of the Target (_not_ its IO). This avoids needing to +// duplicate harnesses (essentially test harnesses) for each target. +// +// You could just as well create a custom harness module that instantiates +// bridges explicitly, or add methods to +// your target traits that instantiate the bridge there (i.e., akin to +// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match +// on the types rather than change trait code. + + + +// A map of partial functions that match on the type the DUT (_not_ it's +// IO) to generate an appropriate bridge. You can add your own binder by adding +// a new (key, fn) pair. You should override existing pairs in this map when +// using a custom IOBinder + +// Since we also want to compose this structure like the existing config system, +// use the scala string representation of the matched trait as a key + case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) + +// This macro overrides previous matches on some Top mixin. This is useful for +// binders which modify IO, since those typically cannot be composed class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((clock: Clock, reset: Bool, success: Bool, t: Any) => { @@ -31,6 +54,19 @@ class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit ta ) }) +// This macro composes with previous matches on some Top mixin. This is useful for +// annotation-like binders, since those can typically be composed +class RegisterBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + t match { + case top: T => fn(clock, reset, success, top) ++ + up(IOBinders, site).getOrElse(tag.runtimeClass.toString, (c: Clock, r: Bool, s: Bool, t: Any) => Nil)(clock, reset, success, top) + } + }) + ) +}) + class WithGPIOTiedOff extends RegisterIOBinder({ (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil }) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 3005d095..8561d7a1 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -24,7 +24,7 @@ import tracegen.HasTraceGenTilesModuleImp import boom.common.{BoomTile} -import chipyard.iobinders.{IOBinders, RegisterIOBinder} +import chipyard.iobinders.{IOBinders, RegisterIOBinder, RegisterBinder} import chipyard.HasBoomAndRocketTilesModuleImp class WithSerialBridge extends RegisterIOBinder({ @@ -66,7 +66,7 @@ class WithTraceGenBridge extends RegisterIOBinder({ (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) -class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ +class WithFireSimMultiCycleRegfile extends RegisterBinder({ (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { target.outer.tiles.map { case r: RocketTile => { From 941c217fbe2415f6a478f38e2ae854ce37d303d3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 14 Feb 2020 11:44:10 -0800 Subject: [PATCH 17/50] [ci] Use FireSim's setup script for CI --- .circleci/do-firesim-build.sh | 7 +++++++ .circleci/run-firesim-tests.sh | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/.circleci/do-firesim-build.sh b/.circleci/do-firesim-build.sh index 8114355f..709f3d0b 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/do-firesim-build.sh @@ -15,6 +15,13 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh +cd $LOCAL_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib +git submodule update --init elfutils libdwarf +cd $LOCAL_CHIPYARD_DIR/sims/firesim +./scripts/build-libelf.sh +./scripts/build-libdwarf.sh +cd $LOCAL_CHIPYARD_DIR + # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh index 6add6790..8cdf9e81 100755 --- a/.circleci/run-firesim-tests.sh +++ b/.circleci/run-firesim-tests.sh @@ -12,10 +12,19 @@ export FIRESIM_ENV_SOURCED=1 SIMULATION_ARGS="${mapping[$1]}" +cd $LOCAL_CHIPYARD_DIR/sims/firesim +./scripts/build-libelf.sh +./scripts/build-libdwarf.sh +cd $LOCAL_CHIPYARD_DIR + + run_test_suite () { + export RISCV=$LOCAL_RISCV_DIR + export LD_LIBRARY_PATH=$LOCAL_RISCV_DIR/lib make -C $LOCAL_FIRESIM_DIR $SIMULATION_ARGS run-${1}-tests-fast } + run_test_suite bmark run_test_suite nic run_test_suite blockdev From 9d45a2711e29a5cf59b4e37cde7b125349797ab9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 14 Feb 2020 23:41:14 -0800 Subject: [PATCH 18/50] Fix generation of env.sh for ZSH (#435) --- scripts/build-toolchains.sh | 2 +- scripts/firesim-setup.sh | 2 +- scripts/init-submodules-no-riscv-tools.sh | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 27c87417..b5d767c0 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -141,5 +141,5 @@ cd "$RDIR" } > env-$TOOLCHAIN.sh # create general env.sh -echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]}") )/env-$TOOLCHAIN.sh" >> env.sh +echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/env-$TOOLCHAIN.sh" >> env.sh echo "Toolchain Build Complete!" diff --git a/scripts/firesim-setup.sh b/scripts/firesim-setup.sh index 0787fd3c..959777d7 100755 --- a/scripts/firesim-setup.sh +++ b/scripts/firesim-setup.sh @@ -6,7 +6,7 @@ set -e set -o pipefail RDIR=$(pwd) -scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" +scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]:-${(%):-%x}}" )" >/dev/null 2>&1 && pwd )" cd "${scripts_dir}/.." diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index ef77374e..c4716ce4 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -60,4 +60,4 @@ git submodule update --init software/firemarshal if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml fi -echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh +echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh From 96fe47ab08856bf952c1e1c0848c55a56ea43280 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Mon, 17 Feb 2020 16:22:28 -0500 Subject: [PATCH 19/50] bump firemarshal to dev. This picks up bug fixes for drivers (firesim/firemarshal#130) and the '--workdir' option (firesim/firemarshal#132) --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index ef69bde3..d660c45a 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit ef69bde3b3fe7b233ac91e16aca3b955b6eff438 +Subproject commit d660c45ac12df4624d1784c19dab03b92347f878 From 1f85b2316988c02b65b4188952197e5ea4fffc79 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 18:32:00 +0000 Subject: [PATCH 20/50] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 52aee63b..dbe1ff19 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52aee63bc04c3769695a41ba18319e316c2e78d5 +Subproject commit dbe1ff19e8b51374791483104076175b1cff03f7 From 97847b8ef48251b1de25da11314381d8ee343d4d Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 20:09:21 +0000 Subject: [PATCH 21/50] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index dbe1ff19..2b3c64c8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit dbe1ff19e8b51374791483104076175b1cff03f7 +Subproject commit 2b3c64c8faaeb8b2d3c31cdb66204bd1743b8fd5 From aead38ab0b22d6d77571958f3edc363ff83412cd Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 22:16:09 +0000 Subject: [PATCH 22/50] bump to firesim dev --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 2b3c64c8..0eee2174 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2b3c64c8faaeb8b2d3c31cdb66204bd1743b8fd5 +Subproject commit 0eee217487ba766721a82a442075c52a1bdc2207 From 708a5fb9a610c6f003d3d78f3657cd8f125f879f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 23 Feb 2020 22:53:14 -0800 Subject: [PATCH 23/50] Address generator unification PR reviews --- .gitignore | 1 + docs/Advanced-Concepts/Chip-Communication.rst | 2 +- .../Configs-Parameters-Mixins.rst | 4 +- docs/Customization/IOBinders.rst | 25 +++++ docs/Customization/Memory-Hierarchy.rst | 102 ++---------------- docs/Customization/index.rst | 1 + docs/Makefile | 2 +- .../FPGA-Accelerated-Simulation.rst | 56 +++------- .../chipyard/src/main/scala/IOBinders.scala | 80 +++++++------- .../src/main/scala/RocketConfigs.scala | 6 +- .../src/main/scala/TracegenConfigs.scala | 1 + .../src/main/scala/BridgeBinders.scala | 18 ++-- .../firechip/src/main/scala/FireSim.scala | 38 +++++++ .../src/main/scala/TargetConfigs.scala | 16 +-- .../firechip/src/main/scala/Targets.scala | 43 -------- generators/icenet | 2 +- sims/firesim | 2 +- 17 files changed, 153 insertions(+), 246 deletions(-) create mode 100644 docs/Customization/IOBinders.rst create mode 100644 generators/firechip/src/main/scala/FireSim.scala delete mode 100644 generators/firechip/src/main/scala/Targets.scala diff --git a/.gitignore b/.gitignore index e2c66082..47cb4d87 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ bootrom/* +docs/warnings.txt /Makefrag.pkgs target *.jar diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index fe9b6f57..596ccd6d 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -109,7 +109,7 @@ reminder, to run a software RTL simulation, run: FireSim FPGA-accelerated simulations use TSI by default as well. -If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDTM` instead of `WithTiedOffDebug ++ WithSimSerial`. +If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDebug` instead of `WithTiedOffDebug ++ WithSimSerial`. .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index e72a7444..f490d2a1 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -91,8 +91,8 @@ lazy module implementation performs the actual Chisel RTL elaboration. In the ``Top`` example class, the "outer" ``Top`` instantiates the "inner" ``TopModule`` as a lazy module implementation. This delays immediate elaboration of the module until all logical connections are determined and all configuration information is exchanged. -The ``Syatem`` outer base class, as well as the -``CanHavePeripheryX`` outer traits contain code to perform high-level logical +The ``System`` outer base class, as well as the +``CanHavePeriphery`` outer traits contain code to perform high-level logical connections. For example, the ``CanHavePeripherySerial`` outer trait contains code to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s TileLink node to the Front bus. diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst new file mode 100644 index 00000000..798987b1 --- /dev/null +++ b/docs/Customization/IOBinders.rst @@ -0,0 +1,25 @@ +IOBinders +========= + +In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what modules to bind to the IOs of a ``Top`` in the ``TestHarness``. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala + :language: scala + :start-after: DOC include start: IOBinders + :end-before: DOC include end: IOBinders + + +This special key solves the problem of duplicating test-harnesses for each different ``Top`` type. + +You could just as well create a custom harness module that attaches IOs explicitly. Instead, the IOBinders key provides a map from Scala traits to attachment behaviors. + +For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala + :language: scala + :start-after: DOC include start: WithSimAXIMem + :end-before: DOC include end: WithSimAXIMem + +These classes are all ``Config`` objects, which can be mixed into the configs to specify IO connection behaviors. + +There are two macros for generating these ``Configs``. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 26bce436..99cc9f77 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -9,89 +9,30 @@ The L1 Caches Each CPU tile has an L1 instruction cache and L1 data cache. The size and associativity of these caches can be configured. The default ``RocketConfig`` uses 16 KiB, 4-way set-associative instruction and data caches. However, -if you use the ``NMedCores`` or ``NSmallCores`` configurations, you can +if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can configure 4 KiB direct-mapped caches for L1I and L1D. -.. code-block:: scala - - class SmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores - new freechips.rocketchip.system.BaseConfig) - - class MediumRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNMediumCores(1) ++ // Medium rocket cores - new freechips.rocketchip.system.BaseConfig) - - - If you only want to change the size or associativity, there are configuration -mixins for those too. +mixins for those too. See :ref:`Mixins` for how to add these to a custom ``Config`` .. code-block:: scala - import freechips.rocketchip.subsystem.{WithL1ICacheSets, WithL1DCacheSets, WithL1ICacheWays, WithL1DCacheWays} - - class MyL1RocketConfig extends Config( new freechips.rocketchip.subsystem.WithL1ICacheSets(128) ++ // change rocket I$ new freechips.rocketchip.subsystem.WithL1ICacheWays(2) ++ // change rocket I$ new freechips.rocketchip.subsystem.WithL1DCacheSets(128) ++ // change rocket D$ new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++ // change rocket D$ - new RocketConfig) + You can also configure the L1 data cache as an data scratchpad instead. However, there are some limitations on this. If you are using a data scratchpad, you can only use a single core and you cannot give the design an external DRAM. Note that these configurations fully remove the L2 cache and mbus. -.. code-block:: scala - class ScratchpadSmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala + :language: scala + :start-after: DOC include start: scratchpadrocket + :end-before: DOC include end: scratchpadrocket This configuration fully removes the L2 cache and memory bus by setting the @@ -121,27 +62,8 @@ To make such a configuration, you can just copy the definition of list of included mixims. If you want to reduce the resources used even further, you can configure -the Broadcast Hub to use a bufferless design. - -.. code-block:: scala - - class NoL2SmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithBufferlessBroadcastHub ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) +the Broadcast Hub to use a bufferless design. This mixin is +``freechips.rocketchip.subsystem.WithBufferlessBroadcastHub``. The Outer Memory System @@ -156,11 +78,7 @@ number of DRAM channels is restricted to powers of two. .. code-block:: scala - import freechips.rocketchip.subsystem.WithNMemoryChannels - - class DualChannelRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ - new RocketConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) In VCS and Verilator simulation, the DRAM is simulated using the diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index c5ec5778..496f4c0a 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -42,3 +42,4 @@ We recommend reading all these pages in order. Hit next to get started! Memory-Hierarchy Boot-Process Firrtl-Transforms + IOBinders diff --git a/docs/Makefile b/docs/Makefile index adea9f26..fe9f0963 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -2,7 +2,7 @@ # # You can set these variables from the command line. -SPHINXOPTS = +SPHINXOPTS = -w warnings.txt SPHINXBUILD = python -msphinx SPHINXPROJ = Chipyard SOURCEDIR = . diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 6964ee57..89c0a939 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -44,47 +44,19 @@ familiar with FireSim, please return to the `FireSim Docs `__, and proceed with the rest of the tutorial. -Current Limitations: -++++++++++++++++++++ - -FireSim integration in Chipyard is still a work in progress. Presently, you -cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, -which properly invokes MIDAS on the target RTL. - -In the interim, workaround this limitation by importing Config and Module -classes from other generator projects into FireChip. For example, assuming you Chipyard -config looks as following: - -.. code-block:: scala - - class CustomConfig extends Config( - new WithInclusiveCache ++ - new myproject.MyCustomConfig ++ - new DefaultRocketConfig - ) - -Then the equivalent FireChip config (in ``generators/firechip/src/main/scala/TargetConfigs.scala``) based on ``FireSimRocketChipConfig`` -will look as follows: - -.. code-block:: scala - - class FireSimCustomConfig extends Config( - new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - new WithExtMemSize(0x400000000L) ++ // 16GB - new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithBlockDevice ++ - new WithRocketL2TLBs(1024) ++ - new WithPerfCounters ++ - new WithoutClockGating ++ - new WithInclusiveCache ++ - new myproject.MyCustomConfig ++ - new freechips.rocketchip.system.DefaultConfig) +Running your Design in FireSim +------------------------------ +Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. -You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` -variables. Note that if your target machine has I/O not provided in the default -FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need -to write a custom bridge. +.. literalinclude:: ../../generators/firechip/src/main/scala/TargetConfigs.scala + :language: scala + :start-after: DOC include start: firesimconfig + :end-before: DOC include end: firesimconfig + + +Only 3 additional config-mixins are needed. + +* ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. +* ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documnetation for details. diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 327db301..22715aaf 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -16,34 +16,29 @@ import testchipip._ import icenet._ import tracegen.{HasTraceGenTilesModuleImp} -import scala.reflect.{ClassTag, classTag} +import scala.reflect.{ClassTag} // System for instantiating binders based // on the scala type of the Target (_not_ its IO). This avoids needing to // duplicate harnesses (essentially test harnesses) for each target. -// -// You could just as well create a custom harness module that instantiates -// bridges explicitly, or add methods to -// your target traits that instantiate the bridge there (i.e., akin to -// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match -// on the types rather than change trait code. +// IOBinders is map between string representations of traits to the desired +// IO connection behavior for tops matching that trait. We use strings to enable +// composition and overriding of IOBinders, much like how normal Keys in the config +// system are used/ At elaboration, the testharness traverses this set of functions, +// and functions which match the type of the Top are evaluated. +// You can add your own binder by adding a new (key, fn) pair, typically by using +// the OverrideIOBinder or ComposeIOBinder macros -// A map of partial functions that match on the type the DUT (_not_ it's -// IO) to generate an appropriate bridge. You can add your own binder by adding -// a new (key, fn) pair. You should override existing pairs in this map when -// using a custom IOBinder - -// Since we also want to compose this structure like the existing config system, -// use the scala string representation of the matched trait as a key - -case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) - +// DOC include start: IOBinders +case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]]( + Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]().withDefaultValue((c: Clock, r: Bool, s: Bool, t: Any) => Nil) +) // This macro overrides previous matches on some Top mixin. This is useful for -// binders which modify IO, since those typically cannot be composed -class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +// binders which drive IO, since those typically cannot be composed +class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((clock: Clock, reset: Bool, success: Bool, t: Any) => { t match { @@ -56,34 +51,41 @@ class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit ta // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class RegisterBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((clock: Clock, reset: Bool, success: Bool, t: Any) => { t match { - case top: T => fn(clock, reset, success, top) ++ - up(IOBinders, site).getOrElse(tag.runtimeClass.toString, (c: Clock, r: Bool, s: Bool, t: Any) => Nil)(clock, reset, success, top) + case top: T => (up(IOBinders, site)(tag.runtimeClass.toString)(clock, reset, success, top) + ++ fn(clock, reset, success, top)) + case _ => Nil } }) ) }) -class WithGPIOTiedOff extends RegisterIOBinder({ +// DOC include end: IOBinders + +class WithGPIOTiedOff extends OverrideIOBinder({ (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil }) -class WithSimBlockDevice extends RegisterIOBinder({ +class WithSimBlockDevice extends OverrideIOBinder({ (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil }) -class WithBlockDeviceModel extends RegisterIOBinder({ +class WithBlockDeviceModel extends OverrideIOBinder({ (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil }) -class WithLoopbackNIC extends RegisterIOBinder({ +class WithLoopbackNIC extends OverrideIOBinder({ (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil }) -class WithUARTAdapter extends RegisterIOBinder({ +class WithSimNIC extends OverrideIOBinder({ + (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectSimNetwork(c, r); Nil +}) + +class WithUARTAdapter extends OverrideIOBinder({ (c, r, s, top: HasPeripheryUARTModuleImp) => { val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate top.uart.zipWithIndex.foreach{ case (dut_io, i) => @@ -95,23 +97,25 @@ class WithUARTAdapter extends RegisterIOBinder({ } }) -class WithSimAXIMem extends RegisterIOBinder({ +// DOC include start: WithSimAXIMem +class WithSimAXIMem extends OverrideIOBinder({ (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil }) +// DOC include end: WithSimAXIMem -class WithSimAXIMMIO extends RegisterIOBinder({ +class WithSimAXIMMIO extends OverrideIOBinder({ (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil }) -class WithDontTouchPorts extends RegisterIOBinder({ +class WithDontTouchPorts extends OverrideIOBinder({ (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil }) -class WithTieOffInterrupts extends RegisterIOBinder({ +class WithTieOffInterrupts extends OverrideIOBinder({ (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil }) -class WithTieOffL2FBusAXI extends RegisterIOBinder({ +class WithTieOffL2FBusAXI extends OverrideIOBinder({ (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { top.l2_frontend_bus_axi4.foreach(axi => { axi.tieoff() @@ -129,7 +133,7 @@ class WithTieOffL2FBusAXI extends RegisterIOBinder({ } }) -class WithTiedOffDebug extends RegisterIOBinder({ +class WithTiedOffDebug extends OverrideIOBinder({ (c, r, s, top: HasPeripheryDebugModuleImp) => { Debug.tieoffDebug(top.debug, top.psd) // tieoffDebug doesn't actually tie everything off :/ @@ -138,7 +142,7 @@ class WithTiedOffDebug extends RegisterIOBinder({ } }) -class WithSimSerial extends RegisterIOBinder({ +class WithSimSerial extends OverrideIOBinder({ (c, r, s, top: CanHavePeripherySerialModuleImp) => { val ser_success = top.connectSimSerial() when (ser_success) { s := true.B } @@ -146,12 +150,12 @@ class WithSimSerial extends RegisterIOBinder({ } }) -class WithTiedOffSerial extends RegisterIOBinder({ +class WithTiedOffSerial extends OverrideIOBinder({ (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil }) -class WithSimDTM extends RegisterIOBinder({ +class WithSimDebug extends OverrideIOBinder({ (c, r, s, top: HasPeripheryDebugModuleImp) => { val dtm_success = Wire(Bool()) top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) @@ -162,6 +166,6 @@ class WithSimDTM extends RegisterIOBinder({ }) -class WithTraceGenSuccessBinder extends RegisterIOBinder({ - (c, r, s, top: HasTraceGenTilesModuleImp) => s := top.success; Nil +class WithTraceGenSuccessBinder extends OverrideIOBinder({ + (c, r, s, top: HasTraceGenTilesModuleImp) => when (top.success) { s := true.B }; Nil }) diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index 6066f86f..2e0f856a 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -90,7 +90,7 @@ class jtagRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithSimDTM ++ // add SimJtag and SimSerial, use both to drive sim + new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new chipyard.config.WithNoGPIO ++ @@ -112,7 +112,7 @@ class dmiRocketConfig extends Config( new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithSimAXIMem ++ new chipyard.iobinders.WithTiedOffSerial ++ - new chipyard.iobinders.WithSimDTM ++ // add SimDTM and use it to drive simulation + new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ @@ -345,6 +345,7 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include start: scratchpadrocket class ScratchpadRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ @@ -363,3 +364,4 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include end: scratchpadrocket diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala index 0e3457f0..1e9be623 100644 --- a/generators/chipyard/src/main/scala/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -24,6 +24,7 @@ class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 8561d7a1..9a19e6ef 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -24,26 +24,26 @@ import tracegen.HasTraceGenTilesModuleImp import boom.common.{BoomTile} -import chipyard.iobinders.{IOBinders, RegisterIOBinder, RegisterBinder} +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.HasBoomAndRocketTilesModuleImp -class WithSerialBridge extends RegisterIOBinder({ +class WithSerialBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq }) -class WithNICBridge extends RegisterIOBinder({ +class WithNICBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq }) -class WithUARTBridge extends RegisterIOBinder({ +class WithUARTBridge extends OverrideIOBinder({ (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq }) -class WithBlockDeviceBridge extends RegisterIOBinder({ +class WithBlockDeviceBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq }) -class WithFASEDBridge extends RegisterIOBinder({ +class WithFASEDBridge extends OverrideIOBinder({ (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -58,15 +58,15 @@ class WithFASEDBridge extends RegisterIOBinder({ } }) -class WithTracerVBridge extends RegisterIOBinder({ +class WithTracerVBridge extends OverrideIOBinder({ (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq }) -class WithTraceGenBridge extends RegisterIOBinder({ +class WithTraceGenBridge extends OverrideIOBinder({ (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) -class WithFireSimMultiCycleRegfile extends RegisterBinder({ +class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { target.outer.tiles.map { case r: RocketTile => { diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala new file mode 100644 index 00000000..884dbbf3 --- /dev/null +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -0,0 +1,38 @@ +//See LICENSE for license details. + +package firesim.firesim + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} + +import midas.widgets.{Bridge, PeekPokeBridge} + +import chipyard.{BuildTop} +import chipyard.iobinders.{IOBinders} + +// Determines the number of times to instantiate the DUT in the harness. +// Subsumes legacy supernode support +case object NumNodes extends Field[Int](1) + +class WithNumNodes(n: Int) extends Config((pname, site, here) => { + case NumNodes => n +}) + +class FireSim(implicit val p: Parameters) extends RawModule { + val clock = IO(Input(Clock())) + val reset = WireInit(false.B) + withClockAndReset(clock, reset) { + // Instantiate multiple instances of the DUT to implement supernode + val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val peekPokeBridge = PeekPokeBridge(reset) + // A Seq of partial functions that will instantiate the right bridge only + // if that Mixin trait is present in the target's class instance + // + // Apply each partial function to each DUT instance + for ((target) <- targets) { + p(IOBinders).values.map(fn => fn(false.B, target)) + } + } +} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 11916662..dcc5be90 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -21,7 +21,6 @@ import tracegen.TraceGenKey import icenet._ import firesim.bridges._ -import firesim.util.{WithNumNodes} import firesim.configs._ import chipyard.{BuildTop} import chipyard.config.ConfigValName._ @@ -106,11 +105,13 @@ class WithFireSimConfigTweaks extends Config( //***************************************************************** // Rocket configs, base off chipyard's RocketConfig //***************************************************************** +// DOC include start: firesimconfig class FireSimRocketConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ new chipyard.RocketConfig) +// DOC include end: firesimconfig class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ @@ -119,19 +120,6 @@ class FireSimQuadRocketConfig extends Config( new chipyard.QuadRocketConfig) -//***************************************************************** -// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig -//***************************************************************** -class FireSimSha3RocketConfig extends Config( - new WithDefaultFireSimBridges ++ - new WithDefaultMemModel ++ - new WithFireSimConfigTweaks ++ - new chipyard.Sha3RocketConfig) - -class FireSimSha3PrintfRocketConfig extends Config( - new sha3.WithSha3Printf ++ - new FireSimSha3RocketConfig) - //***************************************************************** // Boom config, base off chipyard's LargeBoomConfig //***************************************************************** diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala deleted file mode 100644 index 6961782a..00000000 --- a/generators/firechip/src/main/scala/Targets.scala +++ /dev/null @@ -1,43 +0,0 @@ -package firesim.firesim - -import chisel3._ -import freechips.rocketchip._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.amba.axi4.AXI4Bundle -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.diplomacy.LazyModule -import icenet._ -import firesim.util.DefaultFireSimHarness -import testchipip._ -import testchipip.SerialAdapter.SERIAL_IF_WIDTH -import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp} -import sifive.blocks.devices.uart._ -import java.io.File - - -object FireSimValName { - implicit val valName = ValName("FireSimHarness") -} -import FireSimValName._ - - - -/******************************************************************************* -* Top level DESIGN configurations. These describe the basic instantiations of -* the designs being simulated. -* -* In general, if you're adding or removing features from any of these, you -* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager -* will store this name as part of the tags for the AGFI, so that later you can -* reconstruct what is in a particular AGFI. These tags are also used to -* determine which driver to build. -*******************************************************************************/ - - -class FireSim(implicit p: Parameters) extends DefaultFireSimHarness diff --git a/generators/icenet b/generators/icenet index 4980d3a3..e235801c 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 4980d3a311e487419f2e6358d678c18b7ff3ffe4 +Subproject commit e235801c4c7088a303dd2136e02fb9548b4ec2f8 diff --git a/sims/firesim b/sims/firesim index c771d114..59885ac8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c771d1143a98dd19f1c4a842cc8a572b5e54de98 +Subproject commit 59885ac828e5433ae6fea7490a7c100a6ea63155 From 43086465a8c96eb0d8d35ab7d6c394b223a820f9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 24 Feb 2020 16:09:34 -0800 Subject: [PATCH 24/50] Bump FireSim for naming changes --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 89c0a939..1b7e47bb 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -59,4 +59,4 @@ Only 3 additional config-mixins are needed. * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. -* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documnetation for details. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documentation for details. diff --git a/sims/firesim b/sims/firesim index 59885ac8..70fc4325 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 59885ac828e5433ae6fea7490a7c100a6ea63155 +Subproject commit 70fc43259b8f66e42ef682c17183dff5f16228bf From e206917b56fc5f087820a55c6d9bb90a2ca4694a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 25 Feb 2020 13:23:49 -0800 Subject: [PATCH 25/50] Bump firesim --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 1b7e47bb..ea4f3297 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -59,4 +59,4 @@ Only 3 additional config-mixins are needed. * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. -* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documentation for details. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSim documentation for details. diff --git a/sims/firesim b/sims/firesim index 70fc4325..1c7caed6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 70fc43259b8f66e42ef682c17183dff5f16228bf +Subproject commit 1c7caed637a64a231905af9aea2148be60add16b From de2170e7a67badbc134ab2eb3ef071f9b88b79b1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 25 Feb 2020 21:27:53 -0800 Subject: [PATCH 26/50] [setup] log init submodules (#433) --- .../init-submodules-no-riscv-tools-nolog.sh | 64 +++++++++++++++++++ scripts/init-submodules-no-riscv-tools.sh | 61 +----------------- 2 files changed, 67 insertions(+), 58 deletions(-) create mode 100755 scripts/init-submodules-no-riscv-tools-nolog.sh diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh new file mode 100755 index 00000000..ed4f5b6a --- /dev/null +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -0,0 +1,64 @@ +#!/usr/bin/env bash + +# exit script if any command fails +set -e +set -o pipefail + +RDIR=$(git rev-parse --show-toplevel) + +# Ignore toolchain submodules +cd "$RDIR" +for name in toolchains/*-tools/*/ ; do + git config submodule."${name%/}".update none +done +git config submodule.toolchains/libgloss.update none +git config submodule.toolchains/qemu.update none + +# Don't automatically initialize generators with big submodules (e.g. linux source) +git config submodule.generators/sha3.update none + +# Disable updates to the FireSim submodule until explicitly requested +git config submodule.sims/firesim.update none +# Disable updates to the hammer tool plugins repos +git config submodule.vlsi/hammer-cadence-plugins.update none +git config submodule.vlsi/hammer-synopsys-plugins.update none +git config submodule.vlsi/hammer-mentor-plugins.update none +git config submodule.software/firemarshal.update none +git submodule update --init --recursive #--jobs 8 + +# Un-ignore toolchain submodules +for name in toolchains/*-tools/*/ ; do + git config --unset submodule."${name%/}".update +done +git config --unset submodule.toolchains/libgloss.update +git config --unset submodule.toolchains/qemu.update + +git config --unset submodule.vlsi/hammer-cadence-plugins.update +git config --unset submodule.vlsi/hammer-synopsys-plugins.update +git config --unset submodule.vlsi/hammer-mentor-plugins.update + +git config --unset submodule.generators/sha3.update +git config --unset submodule.software/firemarshal.update + +# Non-recursive clone to exclude riscv-linux +git submodule update --init generators/sha3 + +git config --unset submodule.sims/firesim.update +# Minimal non-recursive clone to initialize sbt dependencies +git submodule update --init sims/firesim +( + cd sims/firesim + # Initialize dependencies for MIDAS-level RTL simulation + git submodule update --init sim/midas +) +git config submodule.sims/firesim.update none + +# Only shallow clone needed for basic SW tests +git submodule update --init software/firemarshal + +# Configure firemarshal to know where our firesim installation is +if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then + echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml +fi +echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh + diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index c4716ce4..550d8846 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -1,63 +1,8 @@ #!/usr/bin/env bash -# exit script if any command fails +# wrapper to log output from init-submodules script + set -e set -o pipefail -RDIR=$(git rev-parse --show-toplevel) - -# Ignore toolchain submodules -cd "$RDIR" -for name in toolchains/*-tools/*/ ; do - git config submodule."${name%/}".update none -done -git config submodule.toolchains/libgloss.update none -git config submodule.toolchains/qemu.update none - -# Don't automatically initialize generators with big submodules (e.g. linux source) -git config submodule.generators/sha3.update none - -# Disable updates to the FireSim submodule until explicitly requested -git config submodule.sims/firesim.update none -# Disable updates to the hammer tool plugins repos -git config submodule.vlsi/hammer-cadence-plugins.update none -git config submodule.vlsi/hammer-synopsys-plugins.update none -git config submodule.vlsi/hammer-mentor-plugins.update none -git config submodule.software/firemarshal.update none -git submodule update --init --recursive #--jobs 8 - -# Un-ignore toolchain submodules -for name in toolchains/*-tools/*/ ; do - git config --unset submodule."${name%/}".update -done -git config --unset submodule.toolchains/libgloss.update -git config --unset submodule.toolchains/qemu.update - -git config --unset submodule.vlsi/hammer-cadence-plugins.update -git config --unset submodule.vlsi/hammer-synopsys-plugins.update -git config --unset submodule.vlsi/hammer-mentor-plugins.update - -git config --unset submodule.generators/sha3.update -git config --unset submodule.software/firemarshal.update - -# Non-recursive clone to exclude riscv-linux -git submodule update --init generators/sha3 - -git config --unset submodule.sims/firesim.update -# Minimal non-recursive clone to initialize sbt dependencies -git submodule update --init sims/firesim -( - cd sims/firesim - # Initialize dependencies for MIDAS-level RTL simulation - git submodule update --init sim/midas -) -git config submodule.sims/firesim.update none - -# Only shallow clone needed for basic SW tests -git submodule update --init software/firemarshal - -# Configure firemarshal to know where our firesim installation is -if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then - echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml -fi -echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh +./scripts/init-submodules-no-riscv-tools-nolog.sh "$@" 2>&1 | tee init-submodules-no-riscv-tools.log From b6faed283a55b4f2acd484bdc90a102210b56c30 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 26 Feb 2020 05:20:54 -0800 Subject: [PATCH 27/50] Bump barstools to fix #428 (#447) barstools is now compatible with chisel 3.2.x --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 5198b388..63d74bc1 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 5198b3883c8dfb744c24e7586eec5c9e80a8dd68 +Subproject commit 63d74bc177cb070126eb0e662ff0ea500722a8d7 From 01238c8b7a5945dd437bcd407534839f574bb9df Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 27 Feb 2020 09:31:08 -0800 Subject: [PATCH 28/50] Rename Config Mixins to Fragments (#451) * [docs] rename config mixins -> fragments [ci skip] * [docs] cleanup naming | link similar sections [ci skip] * [boom] bump for mixin rename [ci skip] * [docs] cleanup capitalization [ci skip] * [docs] consistent config fragment naming [ci skip] * [boom] bump boom for documentation changes [ci skip] * [docs] update source comments [ci skip] * [docs] fix last config fragment name [ci skip] Co-Authored-By: alonamid Co-authored-by: alonamid --- docs/Advanced-Concepts/CDEs.rst | 8 ++--- docs/Advanced-Concepts/Chip-Communication.rst | 4 +-- docs/Advanced-Concepts/Top-Testharness.rst | 2 +- docs/Advanced-Concepts/index.rst | 2 +- .../Configs-Parameters-Mixins.rst | 34 +++++++++---------- docs/Customization/Heterogeneous-SoCs.rst | 30 ++++++++-------- docs/Customization/IOBinders.rst | 2 +- docs/Customization/Keys-Traits-Configs.rst | 20 +++++------ docs/Customization/MMIO-Peripherals.rst | 6 ++-- docs/Customization/Memory-Hierarchy.rst | 10 +++--- docs/Customization/index.rst | 2 +- docs/Generators/Gemmini.rst | 12 +++---- docs/Generators/Hwacha.rst | 4 +-- docs/Generators/IceNet.rst | 6 ++-- docs/Generators/SHA3.rst | 4 +-- docs/Generators/SiFive-Generators.rst | 14 ++++---- docs/Generators/TestChipIP.rst | 2 +- .../FPGA-Accelerated-Simulation.rst | 2 +- docs/Simulation/Software-RTL-Simulation.rst | 2 +- generators/boom | 2 +- ...nfigMixins.scala => ConfigFragments.scala} | 12 +++---- generators/chipyard/src/main/scala/GCD.scala | 4 +-- 22 files changed, 91 insertions(+), 93 deletions(-) rename generators/chipyard/src/main/scala/{ConfigMixins.scala => ConfigFragments.scala} (92%) diff --git a/docs/Advanced-Concepts/CDEs.rst b/docs/Advanced-Concepts/CDEs.rst index b8e130e6..6904106e 100644 --- a/docs/Advanced-Concepts/CDEs.rst +++ b/docs/Advanced-Concepts/CDEs.rst @@ -28,11 +28,11 @@ Consider the following example using CDEs. } -When forming a query based on a ``Parameters`` object, like ``p(SomeKeyX)``, the configuration system traverses the "chain" of mixins until it finds a partial function which is defined at the key, and then returns that value. +When forming a query based on a ``Parameters`` object, like ``p(SomeKeyX)``, the configuration system traverses the "chain" of config fragments until it finds a partial function which is defined at the key, and then returns that value. .. code:: scala - val params = Config(new WithX(true) ++ new WithY(true)) // "chain" together mixins + val params = Config(new WithX(true) ++ new WithY(true)) // "chain" together config fragments params(SomeKeyX) // evaluates to true params(SomeKeyY) // evaluates to true params(SomeKeyZ) // evaluates to false @@ -68,7 +68,7 @@ In this example, the partial function in ``WithXEqualsYSite`` will look up the v Here ~~~~ -``here`` provides a ``View`` of the locally defined Config, which typically just contains some partial function. +``here`` provides a ``View`` of the locally defined config, which typically just contains some partial function. .. code:: scala @@ -103,7 +103,7 @@ Up params_1(SomeKeyX) // evaluates to true params_2(SomeKeyX) // evaluates to false -In this example, note how ``up(SomeKeyY, site)`` in ``WithXEqualsYUp`` will refer to *either* the the partial function defining ``SomeKeyY`` in ``WithY(true)`` *or* the default value for ``SomeKeyY`` provided in the original ``case object SomeKeyY`` definition, *depending on the order in which the mixins were used*. Since the order of mixins affects the the order of the ``View`` traversal, ``up`` provides a different ``View`` of the parameterization in ``params_1`` and ``params_2``. +In this example, note how ``up(SomeKeyY, site)`` in ``WithXEqualsYUp`` will refer to *either* the the partial function defining ``SomeKeyY`` in ``WithY(true)`` *or* the default value for ``SomeKeyY`` provided in the original ``case object SomeKeyY`` definition, *depending on the order in which the config fragments were used*. Since the order of config fragments affects the the order of the ``View`` traversal, ``up`` provides a different ``View`` of the parameterization in ``params_1`` and ``params_2``. Also note that again, ``site`` must be recursively passed through the call to ``up``. diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 596ccd6d..eff08670 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -81,7 +81,7 @@ Similar to TSI, the DMI protocol is an implementation of HTIF. In order to communicate with the DUT with the DMI protocol, the DUT needs to contain a Debug Transfer Module (DTM). The DTM is given in the `RISC-V Debug Specification `__ and is responsible for managing communication between the DUT and whatever lives on the other side of the DMI (in this case FESVR). -This is implemented in the Rocket Chip ``Subsystem`` by having the ``HasPeripheryDebug`` and ``HasPeripheryDebugModuleImp`` mixins. +This is implemented in the Rocket Chip ``Subsystem`` by having the ``HasPeripheryDebug`` and ``HasPeripheryDebugModuleImp`` traits. During simulation, the host sends DMI commands to a simulation stub called ``SimDTM`` (C++ class) that resides in a ``SimDTM`` Verilog module (both are located in the ``generators/rocket-chip`` project). This ``SimDTM`` Verilog module then @@ -138,7 +138,7 @@ Creating a DTM+JTAG Config First, a DTM config must be created for the system that you want to create. This step is similar to the DMI simulation section within the :ref:`Starting the TSI or DMI Simulation` section. The configuration is very similar to a DMI-based configuration. The main difference -is the addition of the ``WithJtagDTM`` mixin that configures the instantiated DTM to use the JTAG protocol as the +is the addition of the ``WithJtagDTM`` config fragment that configures the instantiated DTM to use the JTAG protocol as the bringup method. .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 43b0be51..8df37769 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -52,7 +52,7 @@ Please refer to :ref:`Communicating with the DUT` for more information on these TestHarness ------------------------- -The wiring between the ``TestHarness`` and the Top are performed in methods defined in mixins added to the Top. +The wiring between the ``TestHarness`` and the Top are performed in methods defined in traits added to the Top. When these methods are called from the ``TestHarness``, they may instantiate modules within the scope of the harness, and then connect them to the DUT. For example, the ``connectSimAXIMem`` method defined in the ``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMems`` diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index af23525a..c13e569b 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -2,7 +2,7 @@ Advanced Concepts ================================ The following sections are advanced topics about how to Chipyard works, how to use Chipyard, and special features of the framework. -They expect you to know about Chisel, Parameters, Configs, etc. +They expect you to know about Chisel, Parameters, configs, etc. .. toctree:: :maxdepth: 2 diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index f490d2a1..9d7d86d0 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -1,4 +1,4 @@ -Configs, Parameters, Mix-ins, and Everything In Between +Configs, Parameters, Mixins, and Everything In Between ======================================================== A significant portion of generators in the Chipyard framework use the Rocket Chip parameter system. @@ -14,12 +14,12 @@ We are still investigating methods to facilitate parameter exploration and disco Configs --------------------- -A *Config* is a collection of multiple generator parameters being set to specific values. -Configs are additive, can override each other, and can be composed of other Configs. -The naming convention for an additive Config is ``With``, while the naming convention for a non-additive Config will be ````. +A *config* is a collection of multiple generator parameters being set to specific values. +Configs are additive, can override each other, and can be composed of other configs (sometimes referred to as config fragments). +The naming convention for an additive config or config fragment is ``With``, while the naming convention for a non-additive config will be ````. Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Parameters`). -This example shows a basic additive Config class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. +This example shows a basic config fragment class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a set of variables that the generator can use when referencing the ``MyAcceleratorKey`` in the design. .. _basic-config-example: @@ -36,7 +36,7 @@ In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a se someLength = 256) }) -This next example shows a "higher-level" additive Config that uses prior parameters that were set to derive other parameters. +This next example shows a "higher-level" additive config fragment that uses prior parameters that were set to derive other parameters. .. _complex-config-example: .. code-block:: scala @@ -50,8 +50,8 @@ This next example shows a "higher-level" additive Config that uses prior paramet hartId = up(RocketTilesKey, site).length) }) -The following example shows a non-additive Config that combines the prior two additive Configs using ``++``. -The additive Configs are applied from the right to left in the list (or bottom to top in the example). +The following example shows a non-additive config that combines or "assembles" the prior two config fragments using ``++``. +The additive config fragments are applied from the right to left in the list (or bottom to top in the example). Thus, the order of the parameters being set will first start with the ``DefaultExampleConfig``, then ``WithMyAcceleratorParams``, then ``WithMyMoreComplexAcceleratorConfig``. .. _top-level-config: @@ -68,10 +68,10 @@ The ``site`` map gives you the definitions as seen from the root of the configur The ``here`` map gives the definitions as seen at the current level of the hierarchy (i.e. in ``WithMyMoreComplexAcceleratorConfig`` itself). The ``up`` map gives the definitions as seen from the next level up from the current (i.e. from ``WithMyAcceleratorParams``). -Cake Pattern +Cake Pattern / Mixin ------------------------- -A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). +A cake pattern or mixin is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). It is used in the Rocket Chip SoC library and Chipyard framework in merging multiple system components and IO interfaces into a large system component. This example shows the Chipyard default top that composes multiple traits together into a fully-featured SoC with many optional components. @@ -83,7 +83,7 @@ This example shows the Chipyard default top that composes multiple traits togeth :end-before: DOC include end: Top -There are two "cakes" here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module +There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. @@ -114,15 +114,13 @@ contain the implementation for the module, and may instantiate other normal modules OR lazy modules (for nested Diplomacy graphs, for example). - -Mix-in ---------------------------- - -A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convention for an additive mix-in is ``CanHave``. +The naming convention for an additive mixin or trait is ``CanHave``. This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. Additional References --------------------------- -A brief explanation of some of these topics is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. +Another description of traits/mixins and config fragments is given in :ref:`Keys, Traits, and Configs`. +Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. + +.. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins). diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 8087fd35..6385f3b3 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -7,8 +7,8 @@ This discussion will focus on how you combine Rocket, BOOM and Hwacha in particu Creating a Rocket and BOOM System ------------------------------------------- -Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific mixins. -Both BOOM and Rocket have mixins labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_. +Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific config fragments. +Both BOOM and Rocket have config fragments labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_. When used together you can create a heterogeneous system. The following example shows a dual core BOOM with a single core Rocket. @@ -18,18 +18,18 @@ The following example shows a dual core BOOM with a single core Rocket. :start-after: DOC include start: DualBoomAndRocket :end-before: DOC include end: DualBoomAndRocket -In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively. -However, for BOOM, an extra mixin called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters. -This mixin applies to all BOOM cores in the system and changes the parameters for each. +In this example, the ``WithNBoomCores`` and ``WithNBigCores`` config fragments set up the default parameters for the multiple BOOM and Rocket cores, respectively. +However, for BOOM, an extra config fragment called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters. +This config fragment applies to all BOOM cores in the system and changes the parameters for each. Great! Now you have a heterogeneous setup with BOOMs and Rockets. The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core). -The ``WithRenumberHarts`` mixin solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first). -The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only BOOM or only Rocket cores in the system. -Thus, without the ``WithRenumberHarts`` mixin, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. +The ``WithRenumberHarts`` config fragment solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first). +The reason this is needed is because by default the ``WithN...Cores(X)`` config fragment assumes that there are only BOOM or only Rocket cores in the system. +Thus, without the ``WithRenumberHarts`` config fragment, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. -The mixin to add to your system would look something like the following. +The config fragment to add to your system would look something like the following. .. code-block:: scala @@ -50,7 +50,7 @@ The mixin to add to your system would look something like the following. } }) -Then you could use this new mixin like the following. +Then you could use this new config fragment like the following. .. code-block:: scala @@ -83,7 +83,7 @@ All with the same Hwacha parameters. Assigning Accelerators to Specific Tiles with MultiRoCC ------------------------------------------------------- -Located in ``generators/chipyard/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. +Located in ``generators/chipyard/src/main/scala/ConfigFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. @@ -94,13 +94,13 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a :end-before: DOC include end: DualBoomAndRocketOneHwacha In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores. -Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` mixin assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core). -Finally, the ``WithMultiRoCC`` mixin is called. -This mixin sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. +Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core). +Finally, the ``WithMultiRoCC`` config fragment is called. +This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter. If this is used earlier in the configuration sequence, then MultiRoCC does not work. -This mixin can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``). +This config fragment can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``). .. [1] Note, in this section "core" and "tile" are used interchangeably but there is subtle distinction between a "core" and "tile" ("tile" contains a "core", L1D/I$, PTW). diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 798987b1..59924a0f 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -22,4 +22,4 @@ For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` wh These classes are all ``Config`` objects, which can be mixed into the configs to specify IO connection behaviors. -There are two macros for generating these ``Configs``. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. +There are two macros for generating these ``Config``s. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index bac311c5..0dd20a65 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -3,7 +3,7 @@ Keys, Traits, and Configs ========================= -You have probably seen snippets of Chisel referencing Keys, Traits, and Configs by this point. +You have probably seen snippets of Chisel referencing keys, traits, and configs by this point. This section aims to elucidate the interactions between these Chisel/Scala components, and provide best practices for how these should be used to create a parameterized design and configure it. @@ -36,9 +36,9 @@ Traits Typically, most custom blocks will need to modify the behavior of some pre-existing block. For example, the GCD widget needs the ``Top`` module to instantiate and connect the widget via Tilelink, generate a top-level ``gcd_busy`` port, and connect that to the module as well. Traits let us do this without modifying the existing code for the ``Top``, and enables compartmentalization of code for different custom blocks. -Top-level traits specify that the ``Top`` has been parameterized to read some custom Key and optionally instantiate and connect a widget defined by that Key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the Key is unset is a no-op. +Top-level traits specify that the ``Top`` has been parameterized to read some custom key and optionally instantiate and connect a widget defined by that key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the key is unset is a no-op. -Top-level traits should be defined and documented in subprojects, alongside their corresponding Keys. The traits should then be added to the ``Top`` being used by Chipyard. +Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``Top`` being used by Chipyard. Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. @@ -54,19 +54,19 @@ These traits are added to the default ``Top`` in Chipyard. :start-after: DOC include start: Top :end-before: DOC include end: Top -Mixins ------- +Config Fragments +---------------- -Config mixins set the keys to a non-default value. Together, the collection of Mixins which define a configuration generate the values for all the keys used by the generator. +Config fragments set the keys to a non-default value. Together, the collection of config fragments which define a configuration generate the values for all the keys used by the generator. -For example, the ``WithGCDMixin`` is parameterized by the type of GCD widget you want to instantiate. When this mixin is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. +For example, the ``WithGCD`` config fragment is parameterized by the type of GCD widget you want to instantiate. When this config fragment is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. .. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala - :start-after: DOC include start: GCD mixin - :end-before: DOC include end: GCD mixin + :start-after: DOC include start: GCD config fragment + :end-before: DOC include end: GCD config fragment -We can use this mixin when composing our configs. +We can use this config fragment when composing our configs. .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index c1c1a424..4801d4d4 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -105,12 +105,12 @@ The ``TopModule`` class is the actual RTL that gets synthesized. -And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` mixin defined earlier. +And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` config fragment defined earlier. .. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala - :start-after: DOC include start: GCD mixin - :end-before: DOC include end: GCD mixin + :start-after: DOC include start: GCD fragment + :end-before: DOC include end: GCD fragment .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 99cc9f77..436a0ea9 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -12,8 +12,8 @@ uses 16 KiB, 4-way set-associative instruction and data caches. However, if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can configure 4 KiB direct-mapped caches for L1I and L1D. -If you only want to change the size or associativity, there are configuration -mixins for those too. See :ref:`Mixins` for how to add these to a custom ``Config`` +If you only want to change the size or associativity, there are config +fragments for those too. See :ref:`Config Fragments` for how to add these to a custom ``Config``. .. code-block:: scala @@ -41,7 +41,7 @@ number of channels and number of banks to 0. The SiFive L2 Cache ------------------- -The default RocketConfig provided in the Chipyard example project uses SiFive's +The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's InclusiveCache generator to produce a shared L2 cache. In the default configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way set-associativity. However, you can change these parameters to obtain your @@ -58,11 +58,11 @@ If you do not want to use the L2 cache (say, for a resource-limited embedded design), you can create a configuration without it. Instead of using the L2 cache, you will instead use RocketChip's TileLink broadcast hub. To make such a configuration, you can just copy the definition of -``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the +``RocketConfig`` but omit the ``WithInclusiveCache`` config fragment from the list of included mixims. If you want to reduce the resources used even further, you can configure -the Broadcast Hub to use a bufferless design. This mixin is +the Broadcast Hub to use a bufferless design. This config fragment is ``freechips.rocketchip.subsystem.WithBufferlessBroadcastHub``. diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 496f4c0a..90d36fda 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -11,7 +11,7 @@ These guides will walk you through customization of your system-on-chip: - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs -- Standard practices for using Keys, Traits, and Configs to parameterize your design +- Standard practices for using keys, traits, and configs to parameterize your design - Customizing the memory hierarchy diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index fe126f02..80767ce0 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -3,9 +3,9 @@ Gemmini The Gemmini project is developing a systolic-array based matrix multiplication unit generator for the investigation of software/hardware implications of such integrated SoC accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. -Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the System Bus (i.e., directly to the L2 cache). +Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the System Bus (i.e., directly to the L2 cache). -To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``, which you can view under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. +To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config fragment to the SoC configurations. To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``, which you can view under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. The example Chipyard config includes the following example SoC configuration which includes Gemmini: @@ -46,12 +46,12 @@ Gemmini Software ------------------ The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__. -The ISA includes configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. +The ISA includes configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. The Gemmini generator includes a C matrix multiplication library which wraps the calls to the custom Gemmini instructions. -The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. +The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` @@ -64,7 +64,7 @@ To build Gemmini tests: cd generators/gemmini/software/gemmini-rocc-tests/ ./build.sh - + Afterwards, the test binaries will be found in ``generators/gemmini/software/gemmini-rocc-tests/build``. Binaries whose names end in ``-baremetal`` are meant to be run in a bare-metal environment, while binaries whose names end in ``-linux`` are meant to run in a Linux environment. You can run the tests either on a cycle-accurate RTL simulator, or on a (much faster) functional ISA simulator called Spike. The Gemmini generator implements a custom non-standard version of Spike. This implementation is found within the ``esp-tools`` Spike implementation, together with the Hwacha vector accelerator non-standard ISA-extension. In order to use this version of Spike, please make sure to build the ``esp-tools`` software toolchain, as described in :ref:`build-toolchains`. @@ -80,7 +80,7 @@ Spike is built by default without a commit log. However, if you would like to ad Alternative SoC Configs -------------------------- -The Gemmini generator includes additional alternative SoC configs (configs that are not in the Chipyard example project). +The Gemmini generator includes additional alternative SoC configs (configs that are not in the Chipyard example project). If you would like to build one of these alternative SoC configurations which are defined in within the Gemmini project repository, you can run the following commands. These commands are similar to the one required when building a simulation from the example project, but they specify that the location of the configs are in the Gemmini subproject, as opposed to the Chipyard example project: .. code-block:: shell diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst index ac4f4fdf..1980cddf 100644 --- a/docs/Generators/Hwacha.rst +++ b/docs/Generators/Hwacha.rst @@ -7,9 +7,9 @@ The Hwacha project includes the Hwacha microarchitecture generator, as well as t For more information on the Hwacha project, please visit the `Hwacha website `__. -To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config mixin to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). +To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala `__ to see the possible configuration parameters. - + Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions. To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it. diff --git a/docs/Generators/IceNet.rst b/docs/Generators/IceNet.rst index b520eb6c..a8595038 100644 --- a/docs/Generators/IceNet.rst +++ b/docs/Generators/IceNet.rst @@ -8,7 +8,7 @@ A diagram of IceNet's microarchitecture is shown below. .. image:: ../_static/images/nic-design.png -There are four basic parts of the NIC: the :ref:`Controller`, which takes requests +There are four basic parts of the NIC: the :ref:`Controller`, which takes requests from and sends responses to the CPU; the :ref:`Send Path`, which reads data from memory and sends it out to the network; the :ref:`Receive Path`, which receives data from the network and writes it to memory; and, optionally, @@ -80,8 +80,8 @@ and ``HasPeripheryIceNICModuleImp`` to the module implementation. If you are confused about the distinction between lazy module and module implementation, refer to :ref:`Cake Pattern`. -Then add the ``WithIceNIC`` config mixin to your configuration. This will -define ``NICKey``, which IceNIC uses to determine its parameters. The mixin +Then add the ``WithIceNIC`` config fragment to your configuration. This will +define ``NICKey``, which IceNIC uses to determine its parameters. The config fragment takes two arguments. The ``inBufFlits`` argument is the number of 64-bit flits that the input packet buffer can hold and the ``usePauser`` argument determines whether or not the NIC will have a pause handler. diff --git a/docs/Generators/SHA3.rst b/docs/Generators/SHA3.rst index c8969c3a..92173995 100644 --- a/docs/Generators/SHA3.rst +++ b/docs/Generators/SHA3.rst @@ -68,9 +68,9 @@ Using a SHA3 Accelerator ------------------------ Since the SHA3 accelerator is designed as a RoCC accelerator, it can be mixed into a Rocket or BOOM core by overriding the -``BuildRoCC`` key. The configuration mixin is defined in the SHA3 +``BuildRoCC`` key. The config fragment is defined in the SHA3 generator. An example configuration highlighting the use of -this mixin is shown here: +this config fragment is shown here: .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index 35b160f8..68c239c7 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -1,13 +1,13 @@ SiFive Generators ================== -Chipyard includes several open-source generators developed and maintained by `SiFive `__. +Chipyard includes several open-source generators developed and maintained by `SiFive `__. These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``. Last-Level Cache Generator ----------------------------- -``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` mixin to your SoC configuration. +``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration. To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section. @@ -16,24 +16,24 @@ Peripheral Devices ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. -To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. +To integrate one of these devices in your SoC, you will need to define a custom config fragment with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following config fragment to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. -.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigFragments.scala :language: scala :start-after: DOC include start: gpio mixin :end-before: DOC include end: gpio mixin -Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC. +Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC. When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). -Finally, you add the relevant config mixin to the SoC config. For example: +Finally, you add the relevant config fragment to the SoC config. For example: .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GPIORocketConfig :end-before: DOC include end: GPIORocketConfig -Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined mixins within the Chipyard example project. You may be able to use these config mixins directly, but you should be aware of their addresses within the SoC address map. +Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined config fragments within the Chipyard example project. You may be able to use these config fragments directly, but you should be aware of their addresses within the SoC address map. diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 0e02c077..f85636b1 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -22,7 +22,7 @@ The block device controller provides a generic interface for secondary storage. This device is primarily used in FireSim to interface with a block device software simulation model. The default Linux configuration in `firesim-software `_ -To add a block device to your design, add the ``WithBlockDevice`` config mixin to your configuration. +To add a block device to your design, add the ``WithBlockDevice`` config fragment to your configuration. TileLink SERDES diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index ea4f3297..82692643 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -55,7 +55,7 @@ Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireS :end-before: DOC include end: firesimconfig -Only 3 additional config-mixins are needed. +Only 3 additional config fragments are needed. * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 9bc236ac..957913e9 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -93,7 +93,7 @@ The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. No The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class. -The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in. +The ``CONFIG`` is the name of the class used for the parameter config while the ``CONFIG_PACKAGE`` is the Scala package it resides in. The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design. diff --git a/generators/boom b/generators/boom index 779c62c5..28003f77 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 779c62c5634847b517be64c554af66829de40067 +Subproject commit 28003f7799fa9ea6cc89b56494dc77a3b427f6c9 diff --git a/generators/chipyard/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala similarity index 92% rename from generators/chipyard/src/main/scala/ConfigMixins.scala rename to generators/chipyard/src/main/scala/ConfigFragments.scala index 8234f0e3..d13f468a 100644 --- a/generators/chipyard/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -32,7 +32,7 @@ object ConfigValName { import ConfigValName._ // ----------------------- -// Common Parameter Mixins +// Common Config Fragments // ----------------------- class WithBootROM extends Config((site, here, up) => { @@ -40,12 +40,12 @@ class WithBootROM extends Config((site, here, up) => { contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") }) -// DOC include start: gpio mixin +// DOC include start: gpio config fragment class WithGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq( GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) }) -// DOC include end: gpio mixin +// DOC include end: gpio config fragment class WithUART extends Config((site, here, up) => { case PeripheryUARTKey => Seq( @@ -80,14 +80,14 @@ class WithTracegenTop extends Config((site, here, up) => { case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) /** - * Mixin to enable different RoCCs based on the hartId + * Config fragment to enable different RoCCs based on the hartId */ class WithMultiRoCC extends Config((site, here, up) => { case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) }) /** - * Mixin to add Hwachas to cores based on hart + * Config fragment to add Hwachas to cores based on hart * * For ex: * Core 0, 1, 2, 3 have been defined earlier @@ -110,7 +110,7 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { /** - * Mixin to add a small Rocket core to the system as a "control" core. + * Config fragment to add a small Rocket core to the system as a "control" core. * Used as an example of a PMU core. */ class WithControlCore extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala index 802520f0..049fa876 100644 --- a/generators/chipyard/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -200,8 +200,8 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { // DOC include end: GCD imp trait -// DOC include start: GCD mixin +// DOC include start: GCD config fragment class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) }) -// DOC include end: GCD mixin +// DOC include end: GCD config fragment From 24fe57d447466098cc32cbd38d8405f4e1065ece Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 11 Feb 2020 22:42:33 -0800 Subject: [PATCH 29/50] use blackboxed SimDRAM instead of SimAXIMem --- .gitmodules | 3 ++ build.sbt | 2 +- common.mk | 8 ++++- .../chipyard/src/main/scala/BoomConfigs.scala | 16 ++++----- .../src/main/scala/HeteroConfigs.scala | 14 ++++---- .../chipyard/src/main/scala/IOBinders.scala | 15 ++++++++ .../src/main/scala/RocketConfigs.scala | 34 +++++++++---------- .../src/main/scala/TracegenConfigs.scala | 8 ++--- generators/testchipip | 2 +- .../src/main/resources/csrc/emulator.cc | 11 ++++-- .../utilities/src/main/scala/Simulator.scala | 5 +++ sims/vcs/.gitignore | 1 + sims/vcs/Makefile | 6 ++-- sims/vcs/dramsim2_ini | 1 + sims/verilator/.gitignore | 1 + sims/verilator/Makefile | 8 ++--- sims/verilator/dramsim2_ini | 1 + tools/DRAMSim2 | 1 + 18 files changed, 90 insertions(+), 47 deletions(-) create mode 120000 sims/vcs/dramsim2_ini create mode 120000 sims/verilator/dramsim2_ini create mode 160000 tools/DRAMSim2 diff --git a/.gitmodules b/.gitmodules index c4a9b2b9..88096baf 100644 --- a/.gitmodules +++ b/.gitmodules @@ -113,3 +113,6 @@ [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git +[submodule "tools/DRAMSim2"] + path = tools/DRAMSim2 + url = https://github.com/firesim/DRAMSim2.git diff --git a/build.sbt b/build.sbt index 678fffb5..0a4e2167 100644 --- a/build.sbt +++ b/build.sbt @@ -127,7 +127,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) - .dependsOn(rocketchip, sifive_cache, boom) + .dependsOn(rocketchip, sifive_cache, boom, utilities) .settings(commonSettings) lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) diff --git a/common.mk b/common.mk index 1fd7a193..08e872f2 100644 --- a/common.mk +++ b/common.mk @@ -129,7 +129,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +dramsim +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator @@ -156,4 +156,10 @@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) tracegen: $(output_dir)/tracegen.result +dramsim_dir = $(base_dir)/tools/DRAMSim2 +dramsim_lib = $(dramsim_dir)/libdramsim.a + +$(dramsim_lib): + $(MAKE) -C $(dramsim_dir) $(notdir $@) + .PHONY: tracegen diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala index cd1e691b..bda5cccd 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.config.{Config} class SmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -32,7 +32,7 @@ class SmallBoomConfig extends Config( class MediumBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -51,7 +51,7 @@ class MediumBoomConfig extends Config( class LargeBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -70,7 +70,7 @@ class LargeBoomConfig extends Config( class MegaBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -89,7 +89,7 @@ class MegaBoomConfig extends Config( class DualSmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -108,7 +108,7 @@ class DualSmallBoomConfig extends Config( class SmallRV32BoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -129,7 +129,7 @@ class SmallRV32BoomConfig extends Config( class HwachaLargeBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -149,7 +149,7 @@ class HwachaLargeBoomConfig extends Config( class LoopbackNICLargeBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala index b5cc6b8c..c275433f 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.config.{Config} class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -33,7 +33,7 @@ class LargeBoomAndRocketConfig extends Config( class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -56,7 +56,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( class DualLargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -79,7 +79,7 @@ class DualLargeBoomAndRocketConfig extends Config( class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -105,7 +105,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( class LargeBoomAndRV32RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -129,7 +129,7 @@ class LargeBoomAndRV32RocketConfig extends Config( class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -151,7 +151,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 22715aaf..938ecc5f 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -103,6 +103,21 @@ class WithSimAXIMem extends OverrideIOBinder({ }) // DOC include end: WithSimAXIMem +class WithBlackBoxSimMem extends OverrideIOBinder({ + (clock, reset, _, top: CanHaveMasterAXI4MemPortModuleImp) => { + (top.mem_axi4 zip top.outer.memAXI4Node).foreach { case (io, node) => + val memSize = top.p(ExtMem).get.master.size + val lineSize = top.p(CacheBlockBytes) + (io zip node.in).foreach { case (axi4, (_, edge)) => + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) + mem.io.axi <> axi4 + mem.io.clock := clock + mem.io.reset := reset + } + }; Nil + } +}) + class WithSimAXIMMIO extends OverrideIOBinder({ (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil }) diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index 2e0f856a..c596dc29 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.config.{Config} class RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -29,7 +29,7 @@ class RocketConfig extends Config( class HwachaRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -49,7 +49,7 @@ class HwachaRocketConfig extends Config( class GemminiRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -69,7 +69,7 @@ class GemminiRocketConfig extends Config( class RoccRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -89,7 +89,7 @@ class RoccRocketConfig extends Config( class jtagRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -110,7 +110,7 @@ class jtagRocketConfig extends Config( class dmiRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation new chipyard.config.WithNoGPIO ++ @@ -129,7 +129,7 @@ class dmiRocketConfig extends Config( class GCDTLRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -150,7 +150,7 @@ class GCDTLRocketConfig extends Config( class GCDAXI4BlackBoxRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -170,7 +170,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config( class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice @@ -190,7 +190,7 @@ class SimBlockDeviceRocketConfig extends Config( class BlockDeviceModelRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel @@ -211,7 +211,7 @@ class BlockDeviceModelRocketConfig extends Config( class GPIORocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top @@ -231,7 +231,7 @@ class GPIORocketConfig extends Config( class QuadRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -249,7 +249,7 @@ class QuadRocketConfig extends Config( class RV32RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -267,7 +267,7 @@ class RV32RocketConfig extends Config( class GB1MemoryRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -287,7 +287,7 @@ class GB1MemoryRocketConfig extends Config( class Sha3RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -308,7 +308,7 @@ class Sha3RocketConfig extends Config( class InitZeroRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -328,7 +328,7 @@ class InitZeroRocketConfig extends Config( class LoopbackNICRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala index 1e9be623..fccac401 100644 --- a/generators/chipyard/src/main/scala/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -6,21 +6,21 @@ import freechips.rocketchip.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} class TraceGenConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ @@ -28,7 +28,7 @@ class BoomTraceGenConfig extends Config( new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ diff --git a/generators/testchipip b/generators/testchipip index a3da53e8..f1b41df8 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a3da53e87ad890be37138e27e477eb9a563fa82e +Subproject commit f1b41df80d12b35f8f514c3fb72775203a7edd2d diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 1a4f4dd2..0e86b836 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -35,6 +35,7 @@ extern tsi_t* tsi; extern dtm_t* dtm; extern remote_bitbang_t * jtag; +extern int dramsim; static uint64_t trace_count = 0; bool verbose; @@ -124,6 +125,8 @@ int main(int argc, char** argv) char ** htif_argv = NULL; int verilog_plusargs_legal = 1; + dramsim = 0; + while (1) { static struct option long_options[] = { {"cycle-count", no_argument, 0, 'c' }, @@ -132,6 +135,7 @@ int main(int argc, char** argv) {"seed", required_argument, 0, 's' }, {"rbb-port", required_argument, 0, 'r' }, {"verbose", no_argument, 0, 'V' }, + {"dramsim", no_argument, 0, 'D' }, #if VM_TRACE {"vcd", required_argument, 0, 'v' }, {"dump-start", required_argument, 0, 'x' }, @@ -140,9 +144,9 @@ int main(int argc, char** argv) }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:V", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); #endif if (c == -1) break; retry: @@ -155,6 +159,7 @@ int main(int argc, char** argv) case 's': random_seed = atoi(optarg); break; case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; + case 'D': dramsim = 1; break; #if VM_TRACE case 'v': { vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); @@ -188,6 +193,8 @@ int main(int argc, char** argv) #endif else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; + else if (arg == "+dramsim") + c = 'D'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index b1b2c4c4..b2982db7 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -83,6 +83,11 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { } def resources(sim: Simulator): Seq[String] = Seq( "/testchipip/csrc/SimSerial.cc", + "/testchipip/csrc/SimDRAM.cc", + "/testchipip/csrc/mm.h", + "/testchipip/csrc/mm.cc", + "/testchipip/csrc/mm_dramsim2.h", + "/testchipip/csrc/mm_dramsim2.cc", "/csrc/SimDTM.cc", "/csrc/SimJTAG.cc", "/csrc/remote_bitbang.h", diff --git a/sims/vcs/.gitignore b/sims/vcs/.gitignore index a0991ff4..c3e65b20 100644 --- a/sims/vcs/.gitignore +++ b/sims/vcs/.gitignore @@ -1,3 +1,4 @@ * !.gitignore !Makefile +!dramsim2_ini diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 86c28f23..e5c6e1be 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -47,7 +47,9 @@ VCS = vcs -full64 VCS_CC_OPTS = \ -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ + -CC "-I$(dramsim_dir)" \ -CC "-std=c++11" \ + $(dramsim_lib) \ $(RISCV)/lib/libfesvr.a VCS_NONCC_OPTS = \ @@ -78,11 +80,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_common_files) +$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_common_files) +$(sim_debug) : $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp diff --git a/sims/vcs/dramsim2_ini b/sims/vcs/dramsim2_ini new file mode 120000 index 00000000..19d93477 --- /dev/null +++ b/sims/vcs/dramsim2_ini @@ -0,0 +1 @@ +../../generators/testchipip/src/main/resources/dramsim2_ini \ No newline at end of file diff --git a/sims/verilator/.gitignore b/sims/verilator/.gitignore index afbfb95f..136aa28f 100644 --- a/sims/verilator/.gitignore +++ b/sims/verilator/.gitignore @@ -2,3 +2,4 @@ !.gitignore !Makefile !verilator.mk +!dramsim2_ini diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index caaba672..140f54fd 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -45,8 +45,8 @@ include $(sim_dir)/verilator.mk ######################################################################################### VERILATOR := $(INSTALLED_VERILATOR) --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim VERILATOR_CC_OPTS = \ -O3 \ @@ -97,10 +97,10 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### -$(sim): $(model_mk) +$(sim): $(model_mk) $(dramsim_lib) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk -$(sim_debug): $(model_mk_debug) +$(sim_debug): $(model_mk_debug) $(dramsim_lib) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk ######################################################################################### diff --git a/sims/verilator/dramsim2_ini b/sims/verilator/dramsim2_ini new file mode 120000 index 00000000..19d93477 --- /dev/null +++ b/sims/verilator/dramsim2_ini @@ -0,0 +1 @@ +../../generators/testchipip/src/main/resources/dramsim2_ini \ No newline at end of file diff --git a/tools/DRAMSim2 b/tools/DRAMSim2 new file mode 160000 index 00000000..2ec7965b --- /dev/null +++ b/tools/DRAMSim2 @@ -0,0 +1 @@ +Subproject commit 2ec7965b2ee051aaff03d5db21c6709aea4dd24e From 4dd97e0b0fe8ca89008b966dc1a27b34f15c35c1 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 2 Mar 2020 21:08:30 -0800 Subject: [PATCH 30/50] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1c7caed6..23b80238 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1c7caed637a64a231905af9aea2148be60add16b +Subproject commit 23b80238aae22625b0a0ef1c173008655c8c3842 From 48a7f22c09ba0df9f92603a17232483b59f34a11 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 3 Mar 2020 09:27:51 -0800 Subject: [PATCH 31/50] move DRAMSim2 makefrag rules --- common.mk | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 08e872f2..839e7b54 100644 --- a/common.mk +++ b/common.mk @@ -156,10 +156,14 @@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) tracegen: $(output_dir)/tracegen.result +.PHONY: tracegen + +####################################### +# Rules for building DRAMSim2 library # +####################################### + dramsim_dir = $(base_dir)/tools/DRAMSim2 dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) - -.PHONY: tracegen From 9f7247b927db222ef06131b027c61c7a23d1c1ef Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 5 Mar 2020 09:17:47 -0800 Subject: [PATCH 32/50] bump firesim for makefile fix --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 23b80238..2f033c21 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 23b80238aae22625b0a0ef1c173008655c8c3842 +Subproject commit 2f033c2101612097fa27cf1768a280c980125b39 From 1e26cb1f499e3e91fa0110b2b69e8f06217c80cf Mon Sep 17 00:00:00 2001 From: John Wright Date: Thu, 5 Mar 2020 13:04:54 -0800 Subject: [PATCH 33/50] Add a git version check to the init scripts and make them work outside of the repo root. (#459) * Fixes #453 - Update scripts/init-submodules-no-riscv-tools.sh to also work if you're in scripts/ - Provide a git version check to ensure the init scripts will work (>= 1.7.8) - Update the documentation to be more explicit that the init script is also for updating. * Update scripts/init-submodules-no-riscv-tools-nolog.sh Co-Authored-By: Albert Ou --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 3 +++ scripts/init-submodules-no-riscv-tools-nolog.sh | 14 +++++++++++++- scripts/init-submodules-no-riscv-tools.sh | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 931da013..c4732e8a 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -34,6 +34,9 @@ After cloning this repo, you will need to initialize all of the submodules. cd chipyard ./scripts/init-submodules-no-riscv-tools.sh +When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. +Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. + .. _build-toolchains: Building a Toolchain diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index ed4f5b6a..888feb0e 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -4,6 +4,19 @@ set -e set -o pipefail +# Check that git version is at least 1.7.8 +MYGIT=$(git --version) +MYGIT=${MYGIT#'git version '} # Strip prefix +case ${MYGIT} in +[1-9]*) ;; +*) echo 'warning: unknown git version' ;; +esac +MINGIT="1.7.8" +if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then + echo "This script requires git version $MINGIT or greater. Exiting." + false +fi + RDIR=$(git rev-parse --show-toplevel) # Ignore toolchain submodules @@ -61,4 +74,3 @@ if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml fi echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh - diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 550d8846..d788f804 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -5,4 +5,7 @@ set -e set -o pipefail +RDIR=$(git rev-parse --show-toplevel) +cd "$RDIR" + ./scripts/init-submodules-no-riscv-tools-nolog.sh "$@" 2>&1 | tee init-submodules-no-riscv-tools.log From 854e71a205d1b16aed615f6943771fee0d71dfdc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 5 Mar 2020 19:35:47 -0800 Subject: [PATCH 34/50] Add tutorial config and tutorial patches --- .circleci/config.yml | 31 ++++ .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 6 + build.sbt | 8 +- generators/boom | 2 +- .../src/main/scala/ConfigFragments.scala | 12 ++ .../main/scala/{ => config}/BoomConfigs.scala | 4 +- .../scala/{ => config}/HeteroConfigs.scala | 18 +-- .../scala/{ => config}/RocketConfigs.scala | 4 +- .../scala/{ => config}/TracegenConfigs.scala | 2 - .../main/scala/config/TutorialConfigs.scala | 138 ++++++++++++++++++ .../src/main/scala/{ => example}/GCD.scala | 0 .../main/scala/{ => example}/InitZero.scala | 0 .../main/scala/{ => example}/NodeTypes.scala | 0 .../{ => example}/RegisterNodeExample.scala | 0 generators/sha3 | 2 +- .../RocketConfigs.scala.patch | 13 ++ scripts/tutorial-patches/build.sbt.patch | 35 +++++ scripts/tutorial-setup.sh | 11 ++ 19 files changed, 265 insertions(+), 22 deletions(-) rename generators/chipyard/src/main/scala/{ => config}/BoomConfigs.scala (99%) rename generators/chipyard/src/main/scala/{ => config}/HeteroConfigs.scala (95%) rename generators/chipyard/src/main/scala/{ => config}/RocketConfigs.scala (99%) rename generators/chipyard/src/main/scala/{ => config}/TracegenConfigs.scala (98%) create mode 100644 generators/chipyard/src/main/scala/config/TutorialConfigs.scala rename generators/chipyard/src/main/scala/{ => example}/GCD.scala (100%) rename generators/chipyard/src/main/scala/{ => example}/InitZero.scala (100%) rename generators/chipyard/src/main/scala/{ => example}/NodeTypes.scala (100%) rename generators/chipyard/src/main/scala/{ => example}/RegisterNodeExample.scala (100%) create mode 100644 scripts/tutorial-patches/RocketConfigs.scala.patch create mode 100644 scripts/tutorial-patches/build.sbt.patch create mode 100755 scripts/tutorial-setup.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index e86da712..a1e67f18 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -143,6 +143,15 @@ jobs: name: Check commits of each submodule command: | .circleci/check-commit.sh + tutorial-setup-check: + executor: main-env + steps: + - checkout + - run: + name: Check that the tutorial-setup patches apply + command: | + scripts/tutorial-setup.sh + install-riscv-toolchain: executor: main-env steps: @@ -193,6 +202,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-rocket" + prepare-chipyard-sha3: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sha3" prepare-chipyard-hetero: executor: main-env steps: @@ -256,6 +270,11 @@ jobs: steps: - run-tests: project-key: "chipyard-rocket" + chipyard-sha3-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sha3" chipyard-hetero-run-tests: executor: main-env steps: @@ -343,6 +362,9 @@ workflows: - commit-on-master-check + # Attempt to apply the tutorial patches + - tutorial-setup-check + # Build extra tests - build-extra-tests: requires: @@ -354,6 +376,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-sha3: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-hetero: requires: - install-riscv-toolchain @@ -417,6 +444,10 @@ workflows: requires: - prepare-chipyard-rocket + - chipyard-sha3-run-tests: + requires: + - prepare-chipyard-sha3 + - chipyard-hetero-run-tests: requires: - prepare-chipyard-hetero diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 4393381e..7fa7c68c 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -42,6 +42,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" +mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 100418aa..ac63ff15 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -28,6 +28,8 @@ run_tracegen () { make tracegen -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ } +# TODO BUG: the run-binary command forces a rebuild of the simulator in CI +# instead, directly run the simulator binary case $1 in chipyard-rocket) run_bmark ${mapping[$1]} @@ -58,6 +60,10 @@ case $1 in $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; + chipyard-sha3) + (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) + $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv + ;; tracegen) run_tracegen ${mapping[$1]} ;; diff --git a/build.sbt b/build.sbt index 0a4e2167..52fc3cb5 100644 --- a/build.sbt +++ b/build.sbt @@ -123,7 +123,9 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet, tracegen) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, + sha3, // On separate line to allow for cleaner tutorial-setup patches + gemmini, icenet, tracegen) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -195,7 +197,9 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, + sha3, // On separate line to allow for cleaner tutorial-setup patches + utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/boom b/generators/boom index 28003f77..5323559b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 28003f7799fa9ea6cc89b56494dc77a3b427f6c9 +Subproject commit 5323559b3075d9cd86d2e87d7b00d1c16444c328 diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index d13f468a..dae6e055 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -70,6 +70,18 @@ class WithTracegenTop extends Config((site, here, up) => { }) +class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => + r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length)) + } + case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => + b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0)) + } + case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) +}) + + + // ------------------ // Multi-RoCC Support // ------------------ diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala similarity index 99% rename from generators/chipyard/src/main/scala/BoomConfigs.scala rename to generators/chipyard/src/main/scala/config/BoomConfigs.scala index bda5cccd..3804b97f 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} // --------------------- @@ -12,7 +10,7 @@ import freechips.rocketchip.config.{Config} class SmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala similarity index 95% rename from generators/chipyard/src/main/scala/HeteroConfigs.scala rename to generators/chipyard/src/main/scala/config/HeteroConfigs.scala index c275433f..af2145e7 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} // --------------------- @@ -11,7 +9,7 @@ import freechips.rocketchip.config.{Config} class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -19,7 +17,7 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new boom.common.WithRenumberHarts ++ // avoid hartid overlap + new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap new boom.common.WithLargeBooms ++ // 3-wide boom new boom.common.WithNBoomCores(1) ++ // single-core boom new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) @@ -42,7 +40,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -64,7 +62,7 @@ class DualLargeBoomAndRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -89,7 +87,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -113,7 +111,7 @@ class LargeBoomAndRV32RocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -137,7 +135,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -160,7 +158,7 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.config.WithUART ++ new chipyard.config.WithControlCore ++ // add small control core to last hartid new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala similarity index 99% rename from generators/chipyard/src/main/scala/RocketConfigs.scala rename to generators/chipyard/src/main/scala/config/RocketConfigs.scala index c596dc29..bc1dab63 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} // -------------- @@ -11,7 +9,7 @@ import freechips.rocketchip.config.{Config} class RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala similarity index 98% rename from generators/chipyard/src/main/scala/TracegenConfigs.scala rename to generators/chipyard/src/main/scala/config/TracegenConfigs.scala index fccac401..b8f503c6 100644 --- a/generators/chipyard/src/main/scala/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala new file mode 100644 index 00000000..0c74b581 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -0,0 +1,138 @@ +package chipyard + +import freechips.rocketchip.config.{Config} + +// This file is designed to accompany a live tutorial, with slides. +// For each of 4 phases, participants will customize and build a +// small demonstration config. + +// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh, +// which removes the SHA3 accelerator RTL, and provides participants +// the experience of integrating external RTL. + +// This file was originally developed for the cancelled ASPLOS-2020 +// Chipyard tutorial. While the configs here work, the corresponding +// slideware has not yet been created + +// NOTE: Configs should be read bottom-up, since they are applied bottom-up + +// Tutorial Phase 1: Configure the cores, caches +class TutorialStarterConfig extends Config( + // IOBinders specify how to connect to IOs in our TestHarness + // These config fragments do not affect + new chipyard.iobinders.WithUARTAdapter ++ // Connect a SimUART adapter to display UART on stdout + new chipyard.iobinders.WithBlackBoxSimMem ++ // Connect simulated external memory + new chipyard.iobinders.WithTieOffInterrupts ++ // Do not simulate external interrupts + new chipyard.iobinders.WithTiedOffDebug ++ // Disconnect the debug module, since we use TSI for bring-up + new chipyard.iobinders.WithSimSerial ++ // Connect external SimSerial widget to drive TSI + + // Config fragments below this line affect hardware generation + // of the Top + new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core + new chipyard.config.WithNoGPIO ++ // Disable GPIOs. + new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM + new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op + new chipyard.config.WithUART ++ // Add a UART + + // CUSTOMIZE THE CORE + // Uncomment out one (or multiple) of the lines below, and choose + // how many cores you want. + // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores + // new boom.common.WithSmallBooms ++ // Specify all BOOM cores should be Small-sized (NOTE: other options are Medium/Large/Mega) + // new boom.common.WithNBoomCores(1) ++ // Specify we want some number of BOOM cores + + // CUSTOMIZE the L2 + // Uncomment this line, and specify a size if you want to have a L2 + // new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++ + + // For simpler designs, we want to minimize IOs on + // our Top. These config fragments remove unnecessary + // ports + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + // BaseConfig configures "bare" rocketchip system + new freechips.rocketchip.system.BaseConfig +) + + +// Tutorial Phase 2: Integrate a TileLink or AXI4 MMIO device +class TutorialMMIOConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithRenumberHarts ++ + new chipyard.config.WithUART ++ + + // Attach either a TileLink or AXI4 version of GCD + // Uncomment one of the below lines + // new chipyard.example.WithGCD(useAXI4=false) ++ // Use TileLink version + // new chipyard.example.WithGCD(useAXI4=true) ++ // Use AXI4 version + + // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.system.BaseConfig +) + +// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator +class TutorialSha3Config extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithRenumberHarts ++ + new chipyard.config.WithUART ++ + + // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo + // new sha3.WithSha3Accel ++ + + // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.system.BaseConfig +) + +// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator +class TutorialSha3BlackBoxConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithRenumberHarts ++ + new chipyard.config.WithUART ++ + + // Uncomment these lines once SHA3 is integrated + // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl + // new sha3.WithSha3Accel ++ + + // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.system.BaseConfig +) diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala similarity index 100% rename from generators/chipyard/src/main/scala/GCD.scala rename to generators/chipyard/src/main/scala/example/GCD.scala diff --git a/generators/chipyard/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala similarity index 100% rename from generators/chipyard/src/main/scala/InitZero.scala rename to generators/chipyard/src/main/scala/example/InitZero.scala diff --git a/generators/chipyard/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala similarity index 100% rename from generators/chipyard/src/main/scala/NodeTypes.scala rename to generators/chipyard/src/main/scala/example/NodeTypes.scala diff --git a/generators/chipyard/src/main/scala/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala similarity index 100% rename from generators/chipyard/src/main/scala/RegisterNodeExample.scala rename to generators/chipyard/src/main/scala/example/RegisterNodeExample.scala diff --git a/generators/sha3 b/generators/sha3 index 543adb4f..cec8db9d 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 543adb4ff1ac8b4f21f8d3ac5f7e865f8d109731 +Subproject commit cec8db9d6b3a602771cae63eaf6705baa3492f6a diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch new file mode 100644 index 00000000..eca5596d --- /dev/null +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -0,0 +1,13 @@ +diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala +index bc1dab6..1d84129 100644 +--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala ++++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala +@@ -293,7 +293,7 @@ class Sha3RocketConfig extends Config( + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ +- new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator ++// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch new file mode 100644 index 00000000..b5eb87bf --- /dev/null +++ b/scripts/tutorial-patches/build.sbt.patch @@ -0,0 +1,35 @@ +diff --git a/build.sbt b/build.sbt +index 52fc3cb..875e3b4 100644 +--- a/build.sbt ++++ b/build.sbt +@@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) + + lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, +- sha3, // On separate line to allow for cleaner tutorial-setup patches ++// sha3, // On separate line to allow for cleaner tutorial-setup patches + gemmini, icenet, tracegen) + .settings(commonSettings) + +@@ -147,9 +147,9 @@ lazy val boom = (project in file("generators/boom")) + .dependsOn(rocketchip) + .settings(commonSettings) + +-lazy val sha3 = (project in file("generators/sha3")) +- .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .settings(commonSettings) ++// lazy val sha3 = (project in file("generators/sha3")) ++// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(commonSettings) + + lazy val gemmini = (project in file("generators/gemmini")) + .dependsOn(rocketchip, chisel_testers, testchipip) +@@ -198,7 +198,7 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") + + lazy val firechip = (project in file("generators/firechip")) + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, +- sha3, // On separate line to allow for cleaner tutorial-setup patches ++// sha3, // On separate line to allow for cleaner tutorial-setup patches + utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .settings( + commonSettings, diff --git a/scripts/tutorial-setup.sh b/scripts/tutorial-setup.sh new file mode 100755 index 00000000..88843f35 --- /dev/null +++ b/scripts/tutorial-setup.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e -x + +rm -rf generators/sha3 + +for p in scripts/tutorial-patches/*.patch +do + echo "Applying tutorial patch $p" + git apply $p +done From 7cf37b604e8e16383e6910d83a217e35b436bd03 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 30 Aug 2019 22:53:30 -0700 Subject: [PATCH 35/50] add ring topology system bus --- .../src/main/scala/config/RocketConfigs.scala | 19 +++++++++++++++++++ .../main/scala/config/TracegenConfigs.scala | 9 +++++++++ .../src/main/scala/TargetConfigs.scala | 10 ++++++++++ generators/testchipip | 2 +- 4 files changed, 39 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index bc1dab63..954c531b 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -363,3 +363,22 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket + +class RingSystemBusRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new testchipip.WithRingSystemBus ++ // Ring-topology system bus + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index b8f503c6..ead38869 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -32,3 +32,12 @@ class NonBlockingTraceGenL2Config extends Config( new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenL2RingConfig extends Config( + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new testchipip.WithRingSystemBus ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index dcc5be90..d13ba0a2 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -19,6 +19,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ +import testchipip.WithRingSystemBus import firesim.bridges._ import firesim.configs._ @@ -148,6 +149,15 @@ class FireSimGemminiRocketConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.GemminiRocketConfig) +//****************************************************************** +// Configuration with Ring topology SystemBus +//****************************************************************** +class FireSimRingSystemBusRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.RingSystemBusRocketConfig) + //********************************************************************************** // Supernode Configurations, base off chipyard's RocketConfig //********************************************************************************** diff --git a/generators/testchipip b/generators/testchipip index f1b41df8..535eb6c5 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit f1b41df80d12b35f8f514c3fb72775203a7edd2d +Subproject commit 535eb6c58374b96c60e4e8217c709d60a66dab4a From d0bec3fba766bb5f3292dfc47e6aae0c183a8384 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 9 Mar 2020 18:06:41 -0700 Subject: [PATCH 36/50] Ariane Integration (#448) * [ariane/make] integrate ariane | have verilator be installed on path not in makefile * [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore * [firesim] bump * [ci] add midas ariane tests * [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments * [ci] remove references to local verilator install * [verilator] update flags * [verilator] minimal set of flags for ariane * [ariane] bump ariane to master * [ci] revert to 4.016 verilator * [ci] install verilator to ci server | misc compile fixes * [ci/make] add longer ci timeout | update when assert is added in verilator sim * [firesim] bump for misc. updates * [make/ci] cleanup makefile and remove firesim tests of it * [docs/firesim] bump and clean docs * [firesim] bump * [ci] use remote verilator for midas tests * [misc] cleanup built.sbt more * [firesim] bump * [misc] bump build.sbt patch for tutorials * [firesim/ci] cleanup and bump firesim --- .circleci/README.md | 9 +-- .circleci/build-verilator.sh | 35 ------------ .circleci/config.yml | 56 +++++++++---------- .circleci/defaults.sh | 8 ++- .circleci/do-firesim-build.sh | 13 ++--- .circleci/do-rtl-build.sh | 12 ++-- .circleci/install-verilator.sh | 23 ++++++++ .circleci/run-firesim-tests.sh | 1 - .circleci/run-midasexamples-tests.sh | 13 ++--- .circleci/run-tests.sh | 13 +++-- .gitmodules | 3 + README.md | 5 +- build.sbt | 13 +++-- common.mk | 15 +++-- docs/Chipyard-Basics/Chipyard-Components.rst | 4 ++ docs/Generators/Ariane.rst | 14 +++++ docs/Generators/index.rst | 1 + generators/ariane | 1 + .../src/main/scala/ArianeConfigs.scala | 42 ++++++++++++++ .../chipyard/src/main/scala/Generator.scala | 1 + .../chipyard/src/main/scala/Subsystem.scala | 22 +++++--- .../chipyard/src/main/scala/TestSuites.scala | 41 ++++++++++++++ .../src/main/scala/config/BoomConfigs.scala | 2 - .../src/main/scala/BridgeBinders.scala | 6 +- .../firechip/src/main/scala/Generator.scala | 3 +- .../src/main/scala/TargetConfigs.scala | 11 ++++ scripts/centos-req.sh | 8 +++ scripts/tutorial-patches/build.sbt.patch | 21 ++----- scripts/ubuntu-req.sh | 8 +++ sims/firesim | 2 +- sims/vcs/Makefile | 20 ++++--- sims/verilator/Makefile | 44 +++++++++++---- sims/verilator/verilator.mk | 39 ------------- variables.mk | 8 +-- 34 files changed, 315 insertions(+), 202 deletions(-) delete mode 100755 .circleci/build-verilator.sh create mode 100755 .circleci/install-verilator.sh create mode 100644 docs/Generators/Ariane.rst create mode 160000 generators/ariane create mode 100644 generators/chipyard/src/main/scala/ArianeConfigs.scala delete mode 100644 sims/verilator/verilator.mk diff --git a/.circleci/README.md b/.circleci/README.md index 83fd3264..a50fc44a 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -16,9 +16,8 @@ For example: - prepare-rocketchip: requires: - install-riscv-toolchain - - install-verilator -This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` and `install-verilator` steps to run before it can run. +This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` steps to run before it can run. All jobs in the CI workflow are specified at the top of `config.yml` They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment. @@ -36,7 +35,6 @@ This directory contains all the collateral for the Chipyard CI to work. The following is included: `build-toolchains.sh` # build either riscv-tools or esp-tools - `build-verilator.sh` # build verilator (remotely) `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work `do-rtl-build.sh` # use verilator to build a sim executable (remotely) `config.yml` # main circleci config script to enumerate jobs/workflows @@ -48,11 +46,10 @@ How things are setup for Chipyard The steps for CI to run are as follows. 1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run). The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused). -2nd, install verilator using the `*.mk` to cache unique versions of verilator (mainly for if verilator is bumped). -3rd, create the simulator binary. +2nd, create the simulator binary. This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). -4th, finally run the tests that were wanted. +3rd, finally run the desired tests. Other CI Setup -------------- diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh deleted file mode 100755 index a6780d1c..00000000 --- a/.circleci/build-verilator.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/bin/bash - -# build verilator - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR - -if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then - # set stricthostkeychecking to no (must happen before rsync) - run "echo \"Ping $SERVER\"" - - clean - - run "mkdir -p $REMOTE_CHIPYARD_DIR" - copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR - - run "make -j$NPROC -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install" - - # copy so that circleci can cache - mkdir -p $LOCAL_CHIPYARD_DIR - mkdir -p $LOCAL_VERILATOR_DIR - copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR - copy $SERVER:$REMOTE_VERILATOR_DIR/ $LOCAL_VERILATOR_DIR - - cp -r $LOCAL_VERILATOR_DIR/install/bin/* $LOCAL_VERILATOR_DIR/install/share/verilator/bin/. -fi diff --git a/.circleci/config.yml b/.circleci/config.yml index a1e67f18..5fdc774d 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -4,9 +4,6 @@ version: 2.1 parameters: - verilator-cache-version: - type: string - default: "v3" tools-cache-version: type: string default: "v4" @@ -15,7 +12,7 @@ parameters: executors: main-env: docker: - - image: riscvboom/riscvboom-images:0.0.12 + - image: riscvboom/riscvboom-images:0.0.13 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit @@ -54,8 +51,8 @@ commands: - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - setup-tools-verilator: - description: "Get toolchain and verilator" + setup-tools: + description: "Get toolchain" parameters: tools-version: type: string @@ -69,9 +66,6 @@ commands: - restore_cache: keys: - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} - - restore_cache: - keys: - - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} prepare-rtl: description: "Run the prepare step of RTL" @@ -88,7 +82,7 @@ commands: type: string default: "do-rtl-build.sh" steps: - - setup-tools-verilator: + - setup-tools: tools-version: "<< parameters.tools-version >>" - run: name: Building << parameters.project-key >> subproject using Verilator @@ -117,7 +111,7 @@ commands: type: string default: "10m" steps: - - setup-tools-verilator: + - setup-tools: tools-version: "<< parameters.tools-version >>" - restore_cache: keys: @@ -166,18 +160,10 @@ jobs: executor: main-env steps: - ssh-checkout - - restore_cache: - keys: - - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Build Verilator + name: Install Verilator to remote command: | - .circleci/build-verilator.sh - no_output_timeout: 120m - - save_cache: - key: verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} - paths: - - "/home/riscvuser/verilator" + .circleci/install-verilator.sh build-extra-tests: executor: main-env steps: @@ -262,9 +248,11 @@ jobs: - prepare-rtl: project-key: "fireboom" build-script: "do-firesim-build.sh" - - - + prepare-chipyard-ariane: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-ariane" chipyard-rocket-run-tests: executor: main-env steps: @@ -327,14 +315,19 @@ jobs: project-key: "fireboom" run-script: "run-firesim-tests.sh" timeout: "30m" - midasexamples-run-tests: executor: main-env steps: - - setup-tools-verilator + - setup-tools - run: name: Run midasexamples tests command: .circleci/run-midasexamples-tests.sh + chipyard-ariane-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-ariane" + # Order and dependencies of jobs to run workflows: version: 2 @@ -357,7 +350,6 @@ workflows: - install-esp-toolchain - # Build verilator - install-verilator - commit-on-master-check @@ -431,13 +423,17 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-ariane: + requires: + - install-riscv-toolchain + - install-verilator + # Run the respective tests # Run midasexamples test - midasexamples-run-tests: requires: - install-riscv-toolchain - - install-verilator # Run the example tests - chipyard-rocket-run-tests: @@ -486,3 +482,7 @@ workflows: requires: - prepare-fireboom - build-extra-tests + + - chipyard-ariane-run-tests: + requires: + - prepare-chipyard-ariane diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 7fa7c68c..552ac1db 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -20,22 +20,24 @@ clean () { # make parallelism NPROC=8 +# verilator version +VERILATOR_VERSION=v4.028 + # remote variables REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard -REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) LOCAL_CHECKOUT_DIR=$HOME/project LOCAL_RISCV_DIR=$HOME/riscv-tools-install LOCAL_ESP_DIR=$HOME/esp-tools-install LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR -LOCAL_VERILATOR_DIR=$HOME/verilator LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim @@ -53,3 +55,5 @@ mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" +mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" +mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-firesim-build.sh b/.circleci/do-firesim-build.sh index 709f3d0b..7d86c779 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/do-firesim-build.sh @@ -28,18 +28,15 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv/esp-tools, verilator, and chipyard to remote +# copy over riscv/esp-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_VERILATOR_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR @@ -54,9 +51,11 @@ fi # Build MIDAS-level verilator sim FIRESIM_VARS="${mapping[$1]}" run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$VERILATOR_BIN_DIR:\$PATH\"; export FIRESIM_ENV_SOURCED=1; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \ +run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export FIRESIM_ENV_SOURCED=1; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator" run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 5276080f..52c920f5 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -21,11 +21,9 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv/esp-tools, verilator, and chipyard to remote +# copy over riscv/esp-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_VERILATOR_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" run "cp -r ~/.sbt $REMOTE_WORK_DIR" @@ -56,9 +54,11 @@ fi # enter the verilator directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \ - make -j$NPROC -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" +run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + make -j$NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/install-verilator.sh b/.circleci/install-verilator.sh new file mode 100755 index 00000000..86d1ae04 --- /dev/null +++ b/.circleci/install-verilator.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +# move verilator to the remote server + +# turn echo on and error on earliest command +set -ex + +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR + +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" + +run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \ + cd $REMOTE_VERILATOR_DIR; \ + git checkout $VERILATOR_VERSION; \ + autoconf; \ + export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \ + ./configure; \ + make -j$NPROC;" diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh index 8cdf9e81..d1111e60 100755 --- a/.circleci/run-firesim-tests.sh +++ b/.circleci/run-firesim-tests.sh @@ -7,7 +7,6 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh -export PATH=$LOCAL_VERILATOR_DIR/install/bin:$PATH export FIRESIM_ENV_SOURCED=1 SIMULATION_ARGS="${mapping[$1]}" diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 7d31ac11..467dc0e9 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -19,13 +19,11 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv-tools, verilator, and chipyard to remote +# copy over riscv-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_VERILATOR_DIR" run "mkdir -p $REMOTE_RISCV_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR # Copy ivy2 and sbt directories @@ -35,12 +33,13 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin # Run midasexamples test run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$VERILATOR_BIN_DIR:\$PATH\"; export FIRESIM_ENV_SOURCED=1; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \ +run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export FIRESIM_ENV_SOURCED=1; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index ac63ff15..480908c9 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -9,14 +9,12 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh -export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator - run_bmark () { - make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ + make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ } run_asm () { - make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ + make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ } run_both () { @@ -25,7 +23,7 @@ run_both () { } run_tracegen () { - make tracegen -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ + make tracegen -C $LOCAL_SIM_DIR $@ } # TODO BUG: the run-binary command forces a rebuild of the simulator in CI @@ -47,7 +45,7 @@ case $1 in export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH - make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} + make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} ;; chipyard-gemmini) export RISCV=$LOCAL_ESP_DIR @@ -70,6 +68,9 @@ case $1 in tracegen-boom) run_tracegen ${mapping[$1]} ;; + chipyard-ariane) + make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + ;; *) echo "No set of tests for $1. Did you spell it right?" exit 1 diff --git a/.gitmodules b/.gitmodules index 88096baf..34846d61 100644 --- a/.gitmodules +++ b/.gitmodules @@ -113,6 +113,9 @@ [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git +[submodule "generators/ariane"] + path = generators/ariane + url = https://github.com/ucb-bar/ariane-wrapper.git [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git diff --git a/README.md b/README.md index 26f32cf5..0eec2d87 100644 --- a/README.md +++ b/README.md @@ -10,14 +10,14 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. ## Resources * Chipyard Documentation: https://chipyard.readthedocs.io/ -* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf +* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf * Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf ## Need help? @@ -63,3 +63,4 @@ These publications cover many of the internal components used in Chipyard. Howev [rocket-chip]: https://github.com/freechipsproject/rocket-chip [boom]: https://github.com/ucb-bar/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ +[ariane]: https://github.com/pulp-platform/ariane/ diff --git a/build.sbt b/build.sbt index 52fc3cb5..a633066f 100644 --- a/build.sbt +++ b/build.sbt @@ -125,7 +125,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen) + gemmini, icenet, tracegen, ariane) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -147,6 +147,10 @@ lazy val boom = (project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) +lazy val ariane = (project in file("generators/ariane")) + .dependsOn(rocketchip) + .settings(commonSettings) + lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) .settings(commonSettings) @@ -196,12 +200,9 @@ lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") -lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, - sha3, // On separate line to allow for cleaner tutorial-setup patches - utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") +lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) + .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) ) - diff --git a/common.mk b/common.mk index 839e7b54..bf40e602 100644 --- a/common.mk +++ b/common.mk @@ -6,10 +6,12 @@ SHELL=/bin/bash ######################################################################################### # variables to get all *.scala files ######################################################################################### -lookup_scala_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.scala" -print 2> /dev/null) +lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS=$(addprefix $(base_dir)/,generators sims/firesim/sim) -SCALA_SOURCES=$(call lookup_scala_srcs,$(SOURCE_DIRS)) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) +SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) +VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) +ARIANE_VLOG_SOURCES = $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v) ######################################################################################### # rocket and testchipip classes @@ -42,7 +44,8 @@ $(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null -generator_temp: $(SCALA_SOURCES) $(sim_files) +# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile +generator_temp: $(SCALA_SOURCES) $(ARIANE_VLOG_SOURCES) $(sim_files) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" @@ -64,7 +67,7 @@ HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNES $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp @echo "" > /dev/null -firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) +firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) # DOC include end: FirrtlCompiler @@ -89,7 +92,7 @@ harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp # remove duplicate files and headers in list of simulation file inputs ######################################################################################## $(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes) - awk '{print $1;}' $^ | sort -u | grep -v '.*\.h$$' > $@ + awk '{print $1;}' $^ | sort -u | grep -v '.*\.\(svh\|h\)$$' > $@ ######################################################################################### # helper rule to just make verilog files diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index cbca299f..d3ec9a95 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -20,6 +20,10 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. +**Ariane Core** + An in-order RISC-V core written in System Verilog. + See :ref:`Ariane Core` for more information. + Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/Generators/Ariane.rst b/docs/Generators/Ariane.rst new file mode 100644 index 00000000..e58f9dfc --- /dev/null +++ b/docs/Generators/Ariane.rst @@ -0,0 +1,14 @@ +Ariane Core +==================================== + +`Ariane `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`. +The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. + +.. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface). + +While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters). + +.. Warning:: This target does not support Verilator simulation at this time. Please use VCS. + +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 90db4ae8..675318d9 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -27,4 +27,5 @@ so changes to the generators themselves will automatically be used when building TestChipIP SiFive-Generators SHA3 + Ariane diff --git a/generators/ariane b/generators/ariane new file mode 160000 index 00000000..145b5ed1 --- /dev/null +++ b/generators/ariane @@ -0,0 +1 @@ +Subproject commit 145b5ed106efd0b22c2105c20722ab303fa4039b diff --git a/generators/chipyard/src/main/scala/ArianeConfigs.scala b/generators/chipyard/src/main/scala/ArianeConfigs.scala new file mode 100644 index 00000000..e0cb771e --- /dev/null +++ b/generators/chipyard/src/main/scala/ArianeConfigs.scala @@ -0,0 +1,42 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +// --------------------- +// Ariane Configs +// --------------------- + +class ArianeConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new ariane.WithNArianeCores(1) ++ // single Ariane core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + +class dmiArianeConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffSerial ++ + new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new ariane.WithNArianeCores(1) ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala index 32619f29..4baba357 100644 --- a/generators/chipyard/src/main/scala/Generator.scala +++ b/generators/chipyard/src/main/scala/Generator.scala @@ -14,6 +14,7 @@ object Generator extends GeneratorApp { implicit val p: Parameters = params TestSuiteHelper.addRocketTestSuites TestSuiteHelper.addBoomTestSuites + TestSuiteHelper.addArianeTestSuites // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index d8635cd5..96443a9f 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -22,24 +22,26 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} +import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} - -trait HasBoomAndRocketTiles extends HasTiles +trait HasChipyardTiles extends HasTiles with CanHavePeripheryPLIC with CanHavePeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem => - val module: HasBoomAndRocketTilesModuleImp + val module: HasChipyardTilesModuleImp protected val rocketTileParams = p(RocketTilesKey) protected val boomTileParams = p(BoomTilesKey) + protected val arianeTileParams = p(ArianeTilesKey) // crossing can either be per tile or global (aka only 1 crossing specified) private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) + private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size) - val allTilesInfo = (rocketTileParams ++ boomTileParams) zip (rocketCrossings ++ boomCrossings) + val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. @@ -59,6 +61,10 @@ trait HasBoomAndRocketTiles extends HasTiles val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately } + case a: ArianeTileParams => { + val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) + (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately + } } connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) @@ -79,14 +85,14 @@ trait HasBoomAndRocketTiles extends HasTiles }.toList } -trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp +trait HasChipyardTilesModuleImp extends HasTilesModuleImp with HasPeripheryDebugModuleImp { - val outer: HasBoomAndRocketTiles + val outer: HasChipyardTiles } class Subsystem(implicit p: Parameters) extends BaseSubsystem - with HasBoomAndRocketTiles + with HasChipyardTiles { override lazy val module = new SubsystemModuleImp(this) @@ -95,7 +101,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) with HasResetVectorWire - with HasBoomAndRocketTilesModuleImp + with HasChipyardTilesModuleImp { tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => wire.hartid := i.U diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 05c4bf6e..7d901c62 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} import boom.common.{BoomTilesKey} +import ariane.{ArianeTilesKey} /** * A set of pre-chosen regression tests @@ -139,4 +140,44 @@ object TestSuiteHelper TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } + + /** + * Add Ariane tests (asm, bmark, regression) + */ + def addArianeTestSuites(implicit p: Parameters) = { + val xlen = p(XLen) + p(ArianeTilesKey).find(_.hartId == 0).map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + } diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 3804b97f..35934eab 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -6,7 +6,6 @@ import freechips.rocketchip.config.{Config} // BOOM Configs // --------------------- - class SmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts @@ -26,7 +25,6 @@ class SmallBoomConfig extends Config( new boom.common.WithNBoomCores(1) ++ // single-core boom new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system - class MediumBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 9a19e6ef..cfa1a873 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -21,11 +21,12 @@ import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey import tracegen.HasTraceGenTilesModuleImp +import ariane.ArianeTile import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} -import chipyard.HasBoomAndRocketTilesModuleImp +import chipyard.HasChipyardTilesModuleImp class WithSerialBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq @@ -67,7 +68,7 @@ class WithTraceGenBridge extends OverrideIOBinder({ }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { + (c, r, s, target: HasChipyardTilesModuleImp) => { target.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -84,6 +85,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ case _ => Nil } } + case a: ArianeTile => Nil } Nil } diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 11598719..18aeefc8 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -26,6 +26,7 @@ trait HasTestSuites { def addTestSuites(targetName: String, params: Parameters) { TestSuiteHelper.addRocketTestSuites(params) TestSuiteHelper.addBoomTestSuites(params) + TestSuiteHelper.addArianeTestSuites(params) TestGeneration.addSuite(FastBlockdevTests) TestGeneration.addSuite(SlowBlockdevTests) if (!targetName.contains("NoNIC")) @@ -61,7 +62,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike { override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs lazy val generatorArgs = GeneratorArgs(args) lazy val genDir = new File(names.targetDir) - // The only reason this is not generateFirrtl; generateAnno is that we need to use a different + // The only reason this is not generateFirrtl; generateAnno is that we need to use a different // JsonProtocol to properly write out the annotations. Fix once the generated are unified elaborate generateTestSuiteMakefrags diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d13ba0a2..e07a73a6 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -19,6 +19,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ +import ariane.ArianeTilesKey import testchipip.WithRingSystemBus import firesim.bridges._ @@ -76,6 +77,7 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) // Enables tracing on all cores class WithTraceIO extends Config((site, here, up) => { case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) case TracePortKey => Some(TracePortParams()) }) @@ -165,3 +167,12 @@ class SupernodeFireSimRocketConfig extends Config( new WithNumNodes(4) ++ new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB new FireSimRocketConfig) + +//********************************************************************************** +//* Ariane Configurations +//*********************************************************************************/ +class FireSimArianeConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.ArianeConfig) diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index 8fac61af..30b9fe70 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -1,5 +1,7 @@ #!/bin/bash +set -ex + sudo yum groupinstall -y "Development tools" sudo yum install -y gmp-devel mpfr-devel libmpc-devel zlib-devel vim git java java-devel curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm.repo @@ -16,3 +18,9 @@ sudo yum install -y centos-release-scl sudo yum install -y devtoolset-8-make # install DTC sudo yum install -y dtc + +# install verilator +git clone http://git.veripool.org/git/verilator +cd verilator +git checkout v4.028 +autoconf && ./configure && make -j16 && sudo make install diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index b5eb87bf..422c59c8 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,5 +1,5 @@ diff --git a/build.sbt b/build.sbt -index 52fc3cb..875e3b4 100644 +index a633066..3df8b74 100644 --- a/build.sbt +++ b/build.sbt @@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) @@ -8,28 +8,19 @@ index 52fc3cb..875e3b4 100644 .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen) + gemmini, icenet, tracegen, ariane) .settings(commonSettings) -@@ -147,9 +147,9 @@ lazy val boom = (project in file("generators/boom")) +@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) - .settings(commonSettings) -+// lazy val sha3 = (project in file("generators/sha3")) -+// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) -+// .settings(commonSettings) ++//lazy val sha3 = (project in file("generators/sha3")) ++// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) -@@ -198,7 +198,7 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") - - lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, -- sha3, // On separate line to allow for cleaner tutorial-setup patches -+// sha3, // On separate line to allow for cleaner tutorial-setup patches - utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") - .settings( - commonSettings, diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index 1858c3a4..da626052 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -1,5 +1,7 @@ #!/bin/bash +set -ex + sudo apt-get install -y build-essential bison flex sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html @@ -17,3 +19,9 @@ sudo apt-get install -y libgtk-3-dev sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat ctags # install DTC sudo apt-get install -y device-tree-compiler + +# install verilator +git clone http://git.veripool.org/git/verilator +cd verilator +git checkout v4.028 +autoconf && ./configure && make -j16 && sudo make install diff --git a/sims/firesim b/sims/firesim index 2f033c21..9f970576 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2f033c2101612097fa27cf1768a280c980125b39 +Subproject commit 9f9705762a7e19b1e9ff77a92f7f4413ffe83265 diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e5c6e1be..e829047c 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -62,20 +62,25 @@ VCS_NONCC_OPTS = \ +v2k \ +vcs+lic+wait \ +vc+list \ - -f $(sim_common_files) \ + -error=noZMMCM \ + -assert svaext \ -sverilog \ + +libext+.v \ +incdir+$(build_dir) \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +VCS_DEFINES = \ + +define+VCS \ +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v + +define+RANDOMIZE_INVALID_ASSIGN -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) ######################################################################################### # vcs simulator rules @@ -84,9 +89,10 @@ $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG -debug_pp + +define+DEBUG \ + -debug_pp ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 140f54fd..13e7d201 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -1,6 +1,9 @@ ######################################################################################### # verilator makefile ######################################################################################### +ifeq ($(shell which verilator),) +$(error Did not find Verilator in PATH. Make sure all requirements are installed) +endif ######################################################################################### # general path variables @@ -38,12 +41,11 @@ debug: $(sim_debug) # import other necessary rules and variables ######################################################################################### include $(base_dir)/common.mk -include $(sim_dir)/verilator.mk ######################################################################################### # verilator binary and flags ######################################################################################### -VERILATOR := $(INSTALLED_VERILATOR) --cc --exe +VERILATOR := verilator --cc --exe CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim @@ -54,17 +56,38 @@ VERILATOR_CC_OPTS = \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ -LDFLAGS "$(LDFLAGS)" +# default flags added for ariane +ARIANE_VERILATOR_FLAGS = \ + --unroll-count 256 \ + -Werror-PINMISSING \ + -Werror-IMPLICIT \ + -Wno-fatal \ + -Wno-PINCONNECTEMPTY \ + -Wno-ASSIGNDLY \ + -Wno-DECLFILENAME \ + -Wno-UNUSED \ + -Wno-UNOPTFLAT \ + -Wno-BLKANDNBLK \ + -Wno-style \ + -Wall + +# normal flags used for chipyard builds (that are incompatible with ariane) +CHIPYARD_VERILATOR_FLAGS = \ + --assert + VERILATOR_NONCC_OPTS = \ --top-module $(VLOG_MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) \ - --assert \ + $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ --output-split-cfuncs 100 \ - $(sim_vsrcs) \ - -f $(sim_common_files) + -f $(sim_common_files) \ + $(sim_vsrcs) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) +VERILATOR_DEFINES = \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) + +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) ######################################################################################### # verilator build paths and file names @@ -81,14 +104,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### - -$(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) +$(model_mk): $(sim_vsrcs) $(sim_common_files) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) +$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk deleted file mode 100644 index 12ab165d..00000000 --- a/sims/verilator/verilator.mk +++ /dev/null @@ -1,39 +0,0 @@ -######################################################################################### -# verilator installation makefrag -######################################################################################### - -######################################################################################### -# verilator version, binary, and path -######################################################################################### -VERILATOR_VERSION = 4.016 -VERILATOR_INSTALL_DIR ?= verilator_install -VERILATOR_SRCDIR = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator) - -######################################################################################### -# build and install our own verilator to work around versioning issues -######################################################################################### -$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator - $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata - touch $@ - -.PHONY: -verilator_install: $(INSTALLED_VERILATOR) - -$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile - $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin - touch $@ - -$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure - mkdir -p $(dir $@) - cd $(dir $@) && ./configure --prefix=$(abspath $(VERILATOR_INSTALL_DIR)/install) - -$(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz - rm -rf $(dir $@) - mkdir -p $(dir $@) - cat $^ | tar -xz --strip-components=1 -C $(dir $@) - touch $@ - -$(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: - mkdir -p $(dir $@) - wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ diff --git a/variables.mk b/variables.mk index d124fed6..8a1bb1df 100644 --- a/variables.mk +++ b/variables.mk @@ -114,11 +114,11 @@ HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir # files that contain lists of files needed for VCS or Verilator simulation -sim_files ?= $(build_dir)/sim_files.f -sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f -sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f +sim_files ?= $(build_dir)/sim_files.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f +sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's) -sim_common_files ?= $(build_dir)/sim_files.common.f +sim_common_files ?= $(build_dir)/sim_files.common.f ######################################################################################### # java arguments used in sbt From 0a66a3504714417683fd5af21752ac02d8f51932 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 9 Mar 2020 21:40:38 -0700 Subject: [PATCH 37/50] [GCD] Fix GCD example (#465) --- generators/chipyard/src/main/scala/example/GCD.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 049fa876..475e0bdc 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -125,7 +125,7 @@ trait GCDModule extends HasRegMap { gcd.valid := impl.io.output_valid impl.io.output_ready := gcd.ready - status := Cat(impl.io.input_ready, impl.io.output_ready) + status := Cat(impl.io.input_ready, impl.io.output_valid) io.gcd_busy := impl.io.busy regmap( From f517070432ddfede9a0bc93cb241ee01b4d4cb65 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 10 Mar 2020 11:33:06 -0700 Subject: [PATCH 38/50] Move DockerImage into Chipyard + Bump BOOM (#463) * [ci] move docker image to chipyard [ci skip] * [ci] bump with new image * [boom] bump --- .circleci/config.yml | 2 +- .circleci/images/Dockerfile | 196 ++++++++++++++++++++++++++++++++++++ .circleci/images/README.md | 18 ++++ generators/boom | 2 +- 4 files changed, 216 insertions(+), 2 deletions(-) create mode 100644 .circleci/images/Dockerfile create mode 100644 .circleci/images/README.md diff --git a/.circleci/config.yml b/.circleci/config.yml index 5fdc774d..dfadcba6 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: riscvboom/riscvboom-images:0.0.13 + - image: ucbbar/chipyard-image:1.0.0 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit diff --git a/.circleci/images/Dockerfile b/.circleci/images/Dockerfile new file mode 100644 index 00000000..807c15f0 --- /dev/null +++ b/.circleci/images/Dockerfile @@ -0,0 +1,196 @@ +### Note: This DockerFile is adapted from https://github.com/CircleCI-Public/example-images/openjdk + +FROM openjdk:11.0.1-jdk-sid + +# man directory is missing in some base images +# https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=863199 +RUN apt-get update \ + && mkdir -p /usr/share/man/man1 \ + && apt-get install -y \ + bzip2 \ + ca-certificates \ + curl \ + git \ + gnupg \ + gzip \ + locales \ + mercurial \ + netcat \ + net-tools \ + openssh-client \ + parallel \ + sudo \ + tar \ + unzip \ + wget \ + xvfb \ + zip + +# Set timezone to UTC by default +RUN ln -sf /usr/share/zoneinfo/Etc/UTC /etc/localtime + +# Use unicode +RUN locale-gen C.UTF-8 || true +ENV LANG=C.UTF-8 + +# install jq +RUN JQ_URL="https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/jq-latest" \ + && curl --silent --show-error --location --fail --retry 3 --output /usr/bin/jq $JQ_URL \ + && chmod +x /usr/bin/jq \ + && jq --version + +# Install Docker + +# Docker.com returns the URL of the latest binary when you hit a directory listing +# We curl this URL and `grep` the version out. +# The output looks like this: + +#> # To install, run the following commands as root: +#> curl -fsSLO https://download.docker.com/linux/static/stable/x86_64/docker-17.05.0-ce.tgz && tar --strip-components=1 -xvzf docker-17.05.0-ce.tgz -C /usr/local/bin +#> +#> # Then start docker in daemon mode: +#> /usr/local/bin/dockerd + +RUN set -ex \ + && export DOCKER_VERSION=$(curl --silent --fail --retry 3 https://download.docker.com/linux/static/stable/x86_64/ | grep -o -e 'docker-[.0-9]*-ce\.tgz' | sort -r | head -n 1) \ + && DOCKER_URL="https://download.docker.com/linux/static/stable/x86_64/${DOCKER_VERSION}" \ + && echo Docker URL: $DOCKER_URL \ + && curl --silent --show-error --location --fail --retry 3 --output /tmp/docker.tgz "${DOCKER_URL}" \ + && ls -lha /tmp/docker.tgz \ + && tar -xz -C /tmp -f /tmp/docker.tgz \ + && mv /tmp/docker/* /usr/bin \ + && rm -rf /tmp/docker /tmp/docker.tgz \ + && which docker \ + && (docker version || true) + +# docker compose +RUN COMPOSE_URL="https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/docker-compose-latest" \ + && curl --silent --show-error --location --fail --retry 3 --output /usr/bin/docker-compose $COMPOSE_URL \ + && chmod +x /usr/bin/docker-compose \ + && docker-compose version + +# install dockerize +RUN DOCKERIZE_URL="https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/dockerize-latest.tar.gz" \ + && curl --silent --show-error --location --fail --retry 3 --output /tmp/dockerize-linux-amd64.tar.gz $DOCKERIZE_URL \ + && tar -C /usr/local/bin -xzvf /tmp/dockerize-linux-amd64.tar.gz \ + && rm -rf /tmp/dockerize-linux-amd64.tar.gz \ + && dockerize --version + +RUN groupadd --gid 3434 riscvuser \ + && useradd --uid 3434 --gid riscvuser --shell /bin/bash --create-home riscvuser \ + && echo 'riscvuser ALL=NOPASSWD: ALL' >> /etc/sudoers.d/50-riscvuser \ + && echo 'Defaults env_keep += "DEBIAN_FRONTEND"' >> /etc/sudoers.d/env_keep + +# BEGIN IMAGE CUSTOMIZATIONS + +# cacerts from OpenJDK 9-slim to workaround http://bugs.java.com/view_bug.do?bug_id=8189357 +# AND https://github.com/docker-library/openjdk/issues/145 +# +# Created by running: +# docker run --rm openjdk:9-slim cat /etc/ssl/certs/java/cacerts | # aws s3 cp - s3://circle-downloads/circleci-images/cache/linux-amd64/openjdk-9-slim-cacerts --acl public-read +RUN if java -fullversion 2>&1 | grep -q '"9.'; then curl --silent --show-error --location --fail --retry 3 --output /etc/ssl/certs/java/cacerts https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/openjdk-9-slim-cacerts; fi + +# Install Maven Version: 3.6.3 +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/apache-maven.tar.gz https://www.apache.org/dist/maven/maven-3/3.6.3/binaries/apache-maven-3.6.3-bin.tar.gz \ + && tar xf /tmp/apache-maven.tar.gz -C /opt/ \ + && rm /tmp/apache-maven.tar.gz \ + && ln -s /opt/apache-maven-* /opt/apache-maven \ + && /opt/apache-maven/bin/mvn -version + +# Install Ant Version: 1.10.5 +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/apache-ant.tar.gz https://archive.apache.org/dist/ant/binaries/apache-ant-1.10.5-bin.tar.gz \ + && tar xf /tmp/apache-ant.tar.gz -C /opt/ \ + && ln -s /opt/apache-ant-* /opt/apache-ant \ + && rm -rf /tmp/apache-ant.tar.gz \ + && /opt/apache-ant/bin/ant -version + +ENV ANT_HOME=/opt/apache-ant + +# Install Gradle Version: 5.0 +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/gradle.zip https://services.gradle.org/distributions/gradle-5.0-bin.zip \ + && unzip -d /opt /tmp/gradle.zip \ + && rm /tmp/gradle.zip \ + && ln -s /opt/gradle-* /opt/gradle \ + && /opt/gradle/bin/gradle -version + +# Install sbt from https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/sbt-latest.tgz +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/sbt.tgz https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/sbt-latest.tgz \ + && tar -xzf /tmp/sbt.tgz -C /opt/ \ + && rm /tmp/sbt.tgz \ + && /opt/sbt/bin/sbt sbtVersion + +# Install openjfx +RUN apt-get update +RUN apt-get install -y --no-install-recommends openjfx + +# Add build-essential +RUN apt-get install -y build-essential + +# Add RISCV toolchain necessary dependencies +RUN apt-get install -y \ + autoconf \ + automake \ + autotools-dev \ + babeltrace \ + bc \ + bison \ + curl \ + device-tree-compiler \ + expat \ + flex \ + gawk \ + gperf \ + libexpat-dev \ + libgmp-dev \ + libmpc-dev \ + libmpfr-dev \ + libtool \ + libusb-1.0-0-dev \ + patchutils \ + pkg-config \ + python \ + python-pexpect \ + python3 \ + texinfo \ + zlib1g-dev \ + rsync + +# Add minimal QEMU dependencies +RUN apt-get install -y \ + libfdt-dev \ + libglib2.0-dev \ + libpixman-1-dev + +# Install verilator +RUN git clone http://git.veripool.org/git/verilator \ + && cd verilator \ + && git checkout v4.028 \ + && autoconf && ./configure && make && make install + +# Update PATH for Java tools +ENV PATH="/opt/sbt/bin:/opt/apache-maven/bin:/opt/apache-ant/bin:/opt/gradle/bin:$PATH" + +# Add HOME environment variable +ENV HOME="/home/riscvuser" + +# Update PATH for RISCV toolchain (note: hardcoded for CircleCI) +ENV RISCV="$HOME/riscv-tools-install" +ENV LD_LIBRARY_PATH="$RISCV/lib" +ENV PATH="$RISCV/bin:$PATH" + +WORKDIR $HOME +USER riscvuser + +# smoke test with path +RUN mvn -version \ + && ant -version \ + && gradle -version \ + && sbt sbtVersion \ + && verilator --version + +# remove extra folders +RUN rm -rf project/ + +# END IMAGE CUSTOMIZATIONS + +CMD ["/bin/sh"] diff --git a/.circleci/images/README.md b/.circleci/images/README.md new file mode 100644 index 00000000..a2172ba2 --- /dev/null +++ b/.circleci/images/README.md @@ -0,0 +1,18 @@ +General +------- +This DockerFile contains the necessary steps to build a Docker container that can run +projects with riscv-tools, chisel3, firrtl, and verilator. It installs the necessary +apt-get packages and sets the environment variables needed in CircleCI. + +Build and Deploy the Container +------------------------------ + + sudo docker build . # to test build before building it with a tag + sudo docker build -t :tag . # to build with tag (ex. 0.0.3) + sudo docker login # login into the account to push to + sudo docker push :tag # to push to repo with tag + +Path Names +---------- +Older docker images (when this Dockerfile was in `riscv-boom/riscv-boom`) can be found in the `riscvboom/riscvboom-images`. +Current up-to-date images are located in `ucbbar/chipyard-image` diff --git a/generators/boom b/generators/boom index 5323559b..a26504f3 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 5323559b3075d9cd86d2e87d7b00d1c16444c328 +Subproject commit a26504f34db8327a5d4d9bb3a342dddf79e02b35 From 72dfbfabd4dc890065872042c45881db4663352d Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Thu, 12 Mar 2020 15:29:01 +0200 Subject: [PATCH 39/50] Allow user to override MAKE command used by toolchain and openocd build. On macOS, "gnumake" and "make" are both supplied by the OS, but are too old to build glibc (both are version 3.81 as of this writing). Homebrew provides the "gmake" executable, which is recent enough for glibc. However, the existing logic in "scripts/build-util.sh" will always prefer "gnumake" over "gmake". The configure logic in the riscv-glibc library allows a user to override the preference for "gnumake" by setting the MAKE environment variable. This change makes "scripts/build-openocd.sh" and "scripts/build-toolchains.sh" mimic that behavior. A user can now use "gmake" instead of "gnumake" during the toolchain build like so: MAKE=gmake ./scripts/build-toolchains.sh --- scripts/build-util.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/build-util.sh b/scripts/build-util.sh index be58a6a1..10a7cb7b 100644 --- a/scripts/build-util.sh +++ b/scripts/build-util.sh @@ -14,7 +14,8 @@ case ${ncpu} in *) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;; esac -MAKE=$(command -v gnumake || command -v gmake || command -v make) +# Allow user to override MAKE +[ -n "${MAKE}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make) readonly MAKE From d540899b48e473f490d4d5fad98993838f9e1ff8 Mon Sep 17 00:00:00 2001 From: Tynan McAuley <16469394+tymcauley@users.noreply.github.com> Date: Fri, 13 Mar 2020 23:51:09 +0200 Subject: [PATCH 40/50] Fix name of Ubuntu/Debian package "libexpat1-dev". (#466) The "libxpat1-dev" package doesn't exist on Ubuntu/Debian, and results in an error when installing Ubuntu/Debian dependencies. The desired package: https://packages.ubuntu.com/bionic/libexpat1-dev Co-authored-by: Tynan McAuley --- scripts/ubuntu-req.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index da626052..ee541e81 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -10,7 +10,7 @@ curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89 sudo apt-get update sudo apt-get install -y sbt sudo apt-get install -y texinfo gengetopt -sudo apt-get install -y libxpat1-dev libusb-dev libncurses5-dev cmake +sudo apt-get install -y libexpat1-dev libusb-dev libncurses5-dev cmake # deps for poky sudo apt-get install -y python3.6 patch diffstat texi2html texinfo subversion chrpath git wget # deps for qemu From 179dd5973433126690dcea124126800fce3bc391 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Mar 2020 18:34:36 -0700 Subject: [PATCH 41/50] bump gemmini to v0.2 (#469) * bump gemmini to v0.2 * bump gemmini * bump gemmini v0.2 --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 6602434b..d6f36d37 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 6602434b34fb33d005af50cd5e7bf8534f82ebf7 +Subproject commit d6f36d37d1e10b7fd514e6680b1eaea032cee628 From d5592ca1a7829cbbe24a0db7a58844c4125abf63 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Mar 2020 18:44:47 -0700 Subject: [PATCH 42/50] bump firesim (#470) * Fix capitalization in docs (#419) * Update Quick-Start.rst * [ci skip] Fix Typos (#444) * Update Quick-Start.rst * bump firesim Co-authored-by: Sagar Karandikar --- docs/Customization/RoCC-Accelerators.rst | 2 +- docs/index.rst | 4 ++-- sims/firesim | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/Customization/RoCC-Accelerators.rst b/docs/Customization/RoCC-Accelerators.rst index 7a3f4447..2d420177 100644 --- a/docs/Customization/RoCC-Accelerators.rst +++ b/docs/Customization/RoCC-Accelerators.rst @@ -45,7 +45,7 @@ The other interfaces available to the accelerator are ``mem``, which provides ac the ``busy`` signal, which indicates when the accelerator is still handling an instruction; and the ``interrupt`` signal, which can be used to interrupt the CPU. -Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRocc.scala`` for detailed information on the different IOs. +Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala`` for detailed information on the different IOs. Adding RoCC accelerator to Config ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/index.rst b/docs/index.rst index a98c3088..debfaf99 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,8 +8,8 @@ Welcome to Chipyard's documentation! .. image:: ./_static/images/chipyard-logo.svg -Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. -It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. +Chipyard is a framework for designing and evaluating full-system hardware using agile teams. +It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. Quick Start diff --git a/sims/firesim b/sims/firesim index 9f970576..e64e51df 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9f9705762a7e19b1e9ff77a92f7f4413ffe83265 +Subproject commit e64e51dfca00e5ad53089847a1781a73acfe8b9b From a99a1c8025c0cf5af03df9bad1ec4469878b1877 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Mar 2020 19:14:36 -0700 Subject: [PATCH 43/50] Resolve conflict (#471) * Fix capitalization in docs (#419) * Update Quick-Start.rst * [ci skip] Fix Typos (#444) * Update Quick-Start.rst Co-authored-by: Sagar Karandikar From dc7e8f748dfc7c02825630989a1330b877db84a8 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sat, 14 Mar 2020 11:36:53 -0700 Subject: [PATCH 44/50] Barstools and chip docs (#446) * WIP; Add some information on building a chip [skip ci] * [docs] [ci skip] re-org chip/barstools docs Also add macrocompiler flag descriptions * [docs] Add MDF description [ci-skip] * [docs] Address some of Abe and Harrison's feedback [ci skip] * [docs] Update hierarchy/transform section [ci skip] * [docs] Address all feedback except cost function [ci skip] * [docs] Describe macro compiler cost function [ci skip] Co-authored-by: John Wright --- docs/Tools/Barstools.rst | 130 ++++++++++++++++++++++++++++++++++ docs/VLSI/Building-A-Chip.rst | 52 +++++++++++++- 2 files changed, 180 insertions(+), 2 deletions(-) diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 81435130..34562227 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -3,3 +3,133 @@ Barstools Barstools is a collection of useful FIRRTL transformations and compilers to help the build process. Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more. + +Mapping technology SRAMs (MacroCompiler) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If you are planning on building a real chip, it is likely that you will plan on using some amount of static random access memory, or SRAM. +SRAM macros offer superior storage density over flip-flop arrays at the cost of restricting the number of read or write transactions that can happen in a cycle. +Unlike in Verilog, these types of sequential memory elements are first-class primitives in Chisel and FIRRTL (``SeqMem`` elements). +This allows Chisel designs to contain abstract instantiations of sequential memory elements without knowing the underlying implementation or process technology. + +Modern CAD tools typically cannot synthesize SRAMs from a high-level RTL description. +This, unfortunately, requires the designer to include the SRAM instantiation in the source RTL, which removes its process portability. +In Verilog-entry designs, it is possible to create a layer of abstraction that allows a new process technology to implement a specific sequential memory block in a wrapper module. +However, this method can be fragile and laborious. + +The FIRRTL compiler contains a transformation to replace the ``SeqMem`` primitives called ``ReplSeqMem``. +This simply converts all ``SeqMem`` instances above a size threshold into external module references. +An external module reference is a FIRRTL construct that enables a design to reference a module without describing its contents, only its inputs and outputs. +A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, which is used to map technology SRAMs. +Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route. + +The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Barstools` scala package. +MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. +Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`SRAM MDF Fields`). +Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file. +This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying. +Arraying can be done in both width and depth, as well as to solve masking constraints. +For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth. +If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration. +For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`SRAM MDF Fields` section. + +The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``. +If the technology supports an SRAM compiler, then MacroCompiler will also emit HammerIR that can be passed to Hammer to run the compiler itself and generate design collateral. +Documentation for SRAM compilers is forthcoming. + +MacroCompiler Options ++++++++++++++++++++++ +MacroCompiler accepts many command-line parameters which affect how it maps ``SeqMem`` s to technology specific macros. +This highest level option ``--mode`` specifies in general how MacroCompiler should map the input ``SeqMem`` s to technology macros. +The ``strict`` value forces MacroCompiler to map all memories to technology macros and error if it is unable to do so. +The ``synflops`` value forces MacroCompiler to map all memories to flip flops. +The ``compileandsynflops`` value instructs MacroCompiler to use the technology compiler to determine sizes of technology macros used but to then create mock versions of these macros with flip flops. +The ``fallbacksynflops`` value causes MacroCompiler to compile all possible memories to technology macros but when unable to do so to use flip flops to implement the remaining memories. +The final and default value, ``compileavailable``, instructs MacroCompiler to compile all memories to the technology macros and do nothing if it is unable to map them. + +Most of the rest of the options are used to control where different inputs and outputs are expected and produced. +The option ``--macro-conf`` is the file that contains the set of input ``SeqMem`` configurations to map in the ``.conf`` format described above. +The option ``--macro-mdf`` also describes the input ``SeqMem`` s but is instead in the ``.mdf`` format. +The option ``--library`` is an ``.mdf`` description of the available technology macros that can be mapped to. +This file could be a list of fixed size memories often referred to as a cache of macros, or a description of what size memories could be made available through some technology specific process (usually an SRAM compiler), or a mix of both. +The option ``--use-compiler`` instructs MacroCompiler that it is allowed to use any compilers listed in the ``--library`` specification. +If this option is not set MacroCompiler will only map to macros directly listed in the ``--library`` specification. +The ``--verilog`` option specifies where MacroCompiler will write the verilog containing the new technology mapped memories. +The ``--firrtl`` option similarly specifies where MacroCompiler will write the FIRRTL that will be used to generate this verilog. +This option is optional and no FIRRTL will be emitted if it is not specified. +The ``--hammer-ir`` option specifies where MacroCompiler will write the details of which macros need to be generated from a technology compiler. +This option is not needed if ``--use-compiler`` is not specified. +This file can then be passed to HAMMER to have it run the technology compiler producing the associated macro collateral. +The ``--cost-func`` option allows the user to specify a different cost function for the mapping task. +Because the mapping of memories is a multi-dimensional space spanning performance, power, and area, the cost function setting of MacroCompiler allows the user to tune the mapping to their preference. +The default option is a reasonable heuristic that attempts to minimize the number of technology macros instantiated per ``SeqMem`` without wasting too many memory bits. +There are two ways to add additional cost functions. +First, you can simply write another one in scala and call `registerCostMetric` which then enables you to pass its name to this command-line flag. +Second, there is a pre-defined `ExternalMetric` which will execute a program (passed in as a path) with the MDF description of the memory being compiled and the memory being proposed as a mapping. +The program should print a floating point number which is the cost for this mapping, if no number is printed MacroCompiler will assume this is an illegal mapping. +The ``--cost-param`` option allows the user to specify parameters to pass to the cost function if the cost function supports that. +The ``--force-synflops [mem]`` options allows the user to override any heuristics in MacroCompiler and force it to map the given memory to flip-flops. +Likewise, the ``--force-compile [mem]`` option allows the user to force MacroCompiler to map the given ``mem`` to a technology macro. + +SRAM MDF Fields ++++++++++++++++ + +Technology SRAM macros described in MDF can be defined at three levels of detail. +A single instance can be defined with the `SRAMMacro` format. +A group of instances that share the number and type of ports but vary in width and depth can be defined with the `SRAMGroup` format. +A set of groups of SRAMs that can be generated together from a single source like a compiler can be defined with the `SRAMCompiler` format. + +At the most concrete level the `SRAMMAcro` defines a particular instance of an SRAM. +That includes its functional attributes such as its width, depth, and number of access ports. +These ports can be read, write, or read and write ports, and the instance can have any number. +In order to correctly map to these functional ports to the physical instance each port is described in a list of sub-structures, in the parent instance's structure. +Each port is only required to have an address and data field, but can have many other optional fields. +These optional fields include a clock, write enable, read enable, chip enable, mask. +The mask field can have a different granularity than the data field, e.g. it could be a bit mask or a byte mask. +Each field must also specify its polarity, whether it is active high or active low. + +In addition to these functional descriptions of the SRAM there are also other fields that specify physical/implementation characteristics. +These include the threshold voltage, the mux factor, as well as a list of extra non-functional ports. + +The next level of detail, an `SRAMGroup` includes a range of depths and widths, as well as a set of threshold voltages. +A range has a lower bound, upper bound, and a step size. +The least concrete level, an `SRAMCompiler` is simply a set of `SRAMGroups`. + +Separating the Top module from the TestHarness module +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Unlike the FireSim and Software simulation flows, a VLSI flow needs to separate the test harness and the chip (a.k.a. DUT) into separate files. +This is necessary to facilitate post-synthesis and post-place-and-route simulation, as the module names in the RTL and gate-level verilog files would collide. +Simulations after you the design goes through a VLSI flow will use the verilog netlist generated from the flow and will need an untouched test harness to drive it. +Separating these components into separate files makes this straightforward. +Without the separation the file that included the test harness would also redefine the DUT which is often disallowed in simulation tools. +To do this, there is a FIRRTL ``App`` in :ref:`Barstools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately. +This also renames modules in the test harness so that any modules that are instantiated in both the test harness and the chip are uniquified. + +.. Note:: For VLSI projects, this ``App`` is run instead of the normal FIRRTL ``App`` to elaborate Verilog. + +Macro Description Format +~~~~~~~~~~~~~~~~~~~~~~~~ + +The SRAM technology macros and IO cells are described in a json format called Macro Description Format (MDF). +MDF is specialized for each type of macro it supports. +The specialization is defined in their respective sections. + + + +Mapping technology IO cells +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Like technology SRAMs, IO cells are almost always included in digital ASIC designs to allow pin configurability, increase the voltage level of the IO signal, and provide ESD protection. +Unlike SRAMs, there is no corresponding primitive in Chisel or FIRRTL. +However, this problem can be solved similarly to ``SeqMems`` by leveraging the strong typing available in these scala-based tools. +We are actively developing a FIRRTL transform that will automatically configure, map, and connect technology IO cells. +Stay tuned for more information! + +In the meantime, it is recommended that you instantiate the IO cells in your Chisel design. +This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recommended that inclusion of these cells be configurable using the ``rocket-chip`` parameterization system. +The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness. +When simulating chip-specific designs, it is important to include the IO cells. +The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check. +They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the top module from the test harness`) consistent after synthesis and place-and-route, +which allows the RTL simulation test harness to be reused. diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index 6f7cd4b1..b684a07b 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -1,6 +1,54 @@ .. _build-a-chip: Building A Chip -============================== +=============== + +In this section, we will discuss many of the ASIC-specific transforms and methodologies within Chipyard. +For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. + +Transforming the RTL +-------------------- + +Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication. +This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Barstools`. +In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier. +This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module. + + +Modifying the logical hierarchy +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Building a large or complex chip often requires using hierarchical design to place and route sections of the chip separately. +In addition, the design as written in Chipyard may not have a hierarchy that matches the physical hierarchy that would work best in the place and route tool. +In order to reorganize the design to have its logical hierarchy match its physical hierarchy there are several FIRRTL transformations that can be run. +These include grouping, which pull several modules into a larger one, and flattening, which dissolves a modules boundary leaving its components in its containing module. +These transformations can be applied repeatedly to different parts of the design to arrange it as the physical designer sees fit. +More details on how to use these transformations to reorganize the design hierarchy are forthcoming. + + +Creating a floorplan +-------------------- + +An ASIC floorplan is a specification that the place-and-route tools will follow when placing instances in the design. +This includes the top-level chip dimensions, placement of SRAM macros, placement of custom (analog) circuits, IO cell placement, bump or wirebond pad placement, blockages, hierarchical boundaries, and pin placement. + +Much of the design effort that goes into building a chip involves developing optimal floorplans for the instance of the design that is being manufactured. +Often this is a highly manual and iterative process which consumes much of the physical designer's time. +This cost becomes increasingly apparent as the parameterization space grows rapidly when using tools like Chisel- cycle times are hampered by the human labor +that is required to floorplan each instance of the design. +The Hammer team is actively developing methods of improving the agility of floorplanning for generator-based designs, like those that use Chisel. +The libraries we are developing will emit Hammer IR that can be passed directly to the Hammer tool without the need for human intervention. +Stay tuned for more information. + +In the meantime, see the `Hammer Documentation `__ for information on the Hammer IR floorplan API. +It is possible to write this IR directly, or to generate it using simple python scripts. +While we certainly look forward to having a more featureful toolkit, we have built many chips to date in this way. + + +Running the VLSI flow +--------------------- + +For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. +For an example of how to use the VLSI in the context of Chipyard, see :ref:`ASAP7 Tutorial`. + -.. Note:: Please refer to the other sections in VLSI for tools/flows on how to build a chip. This section will be filled in ASAP. From c798592f448fd545b5424e84cfe75d76a9c2a430 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 14 Mar 2020 12:08:08 -0700 Subject: [PATCH 45/50] Update CHANGELOG.md (#475) * Update CHANGELOG.md * [skip CI] Update CHANGELOG.md Co-Authored-By: Sagar Karandikar * Update CHANGELOG.md Co-authored-by: Sagar Karandikar --- CHANGELOG.md | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 31fb2250..22783946 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,43 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.2.0] - 2020-03-14 + +A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418 + +### Added +* Ring Topology System Bus NoC (#461) +* Integration of the Ariane core into Chipyard (#448) +* FireMarshal now generates an extra copy of linux kernel with dwarf debugging info for use in FirePerf (#427) +* Add option to use blackboxed SimDRAM instead of SimAXIMem (#449) +* Log `init-submodules` script (#433) +* Moved the Docker image used for CI into Chipyard (prev. in BOOM) (#463) + +### Changed +* Bump FireSim to 1.9.0 - Includes FirePerf TracerV Flame Graph features +* IOBinders and BuildTop unification between FireChip and Chipyard (#390) +* Bump BOOM to version 2.2.4 (#463) +* Bump Gemmini to version 0.2 (#469) +* Update to CircleCI 2.1 config. syntax and cleanup CI file (#421) +* FireMarshal moved from FireSim to Chipyard (#415) +* Rename config. mixins to config fragments (#451) + +### Fixed +* `git status` should be clean. (Although you will need to manually cleanup the libgloss and qemu directories after first setup). (#411, #414) +* Fix Hetero. BOOM + Rocket + Hwacha config (#413) +* Fix VCS stdout (#417) +* Add a git version check to the init scripts and make them work outside of the repo root (#459) +* Fix generation of env.sh for zsh (#435) +* GCD example bug (#465) + +### Deprecated + + +### Removed + + + + ## [1.1.0] - 2020-01-25 A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/367 From 0d902f5e92534c15d6479554062fbe36d3c2acab Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 14 Mar 2020 12:41:14 -0700 Subject: [PATCH 46/50] bump to firesim dev that will become master --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index e64e51df..5cef02ad 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e64e51dfca00e5ad53089847a1781a73acfe8b9b +Subproject commit 5cef02ad96365d6663756c143b174afad435828c From 3a5090b65cfe3d5bdd468b3fde46a5dfbe001b81 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Sat, 14 Mar 2020 19:59:33 +0000 Subject: [PATCH 47/50] bump icenet testchipip to master --- generators/icenet | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/icenet b/generators/icenet index e235801c..f2272284 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit e235801c4c7088a303dd2136e02fb9548b4ec2f8 +Subproject commit f22722847444ecfcd5369f1b33547727d051b834 diff --git a/generators/testchipip b/generators/testchipip index 535eb6c5..3a83cd0a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 535eb6c58374b96c60e4e8217c709d60a66dab4a +Subproject commit 3a83cd0a4036bec8ea9a2bebd582539723601e73 From ece9163b023a12f834306b82cbc83255b4f710ec Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 14 Mar 2020 13:03:48 -0700 Subject: [PATCH 48/50] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 5cef02ad..3f5467ac 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 5cef02ad96365d6663756c143b174afad435828c +Subproject commit 3f5467ace1c204d45cc2cdd26773260ce09c9a8a From b63adae5d9285df79a9514e4df45e11740408449 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 14 Mar 2020 13:26:47 -0700 Subject: [PATCH 49/50] update changelog (#479) --- CHANGELOG.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 22783946..f9447b0e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -32,10 +32,10 @@ A more detailed account of everything included is included in the dev to master * GCD example bug (#465) ### Deprecated - +* N/A ### Removed - +* N/A From a3e12b96b0278c4bf6317f1f125849854126f392 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Sun, 15 Mar 2020 01:04:51 +0000 Subject: [PATCH 50/50] [skip ci] bump firesim 1.9.0 --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3f5467ac..ce0d05a1 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3f5467ace1c204d45cc2cdd26773260ce09c9a8a +Subproject commit ce0d05a10a47e58e17e1b081115429dc6328768d