diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
index 6d0ace69..a0dbe482 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -83,7 +83,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
     val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
     val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
 
-    // The order of the connections to clockSelector.clockNode configures what 
+    // The order of the connections to clockSelector.clockNode configures the inputs
+    // of the clockSelector's clockMux. Default to using the slowClockSource,
+    // software should enable the PLL, then switch to the pllClockSource
     clockSelector.clockNode := slowClockSource
     clockSelector.clockNode := pllClockSource
 
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
index 97ac5032..9e142bda 100644
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -43,7 +43,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
   val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
   val pllClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
 
-  // The order of the connections to clockSelector.clockNode configures what
+  // The order of the connections to clockSelector.clockNode configures the inputs
+  // of the clockSelector's clockMux. Default to using the slowClockSource,
+  // software should enable the PLL, then switch to the pllClockSource
   clockSelector.clockNode := slowClockSource
   clockSelector.clockNode := pllClockSource