Remove old TapeoutStage/ModelStageMain stuff

This commit is contained in:
Jerry Zhao
2024-04-22 20:13:55 -07:00
parent efacb0888d
commit 33e6272ed8
8 changed files with 0 additions and 309 deletions

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@@ -1,26 +0,0 @@
// See LICENSE for license details.
package tapeout.transforms
import firrtl.Mappers._
import firrtl._
import firrtl.annotations.{CircuitTarget, ModuleTarget, SingleTargetAnnotation}
import firrtl.ir._
import firrtl.stage.Forms
import firrtl.stage.TransformManager.TransformDependency
import firrtl.options.{Dependency}
class ExtraLowTransforms extends Transform with DependencyAPIMigration {
// this PropagatePresetAnnotations is needed to run the RemoveValidIf pass (that is removed from CIRCT).
// additionally, since that pass isn't explicitly a prereq of the LowFormEmitter it
// needs to wrapped in this xform
override def prerequisites: Seq[TransformDependency] = Forms.LowForm :+
Dependency[firrtl.transforms.PropagatePresetAnnotations]
override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized
override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
override def invalidates(a: Transform): Boolean = false
def execute(state: CircuitState): CircuitState = {
state
}
}

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package tapeout.transforms
import tapeout.transforms.stage._
import firrtl._
import firrtl.annotations._
import firrtl.ir._
import firrtl.options.{Dependency, InputAnnotationFileAnnotation, StageMain}
import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage, RunFirrtlTransformAnnotation}
import logger.LazyLogging
private class GenerateModelStageMain(annotations: AnnotationSeq) extends LazyLogging {
val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s }
val annoFiles: List[String] = annotations.flatMap {
case InputAnnotationFileAnnotation(f) => Some(f)
case _ => None
}.toList
// Dump firrtl and annotation files
// Use global param outAnno
protected def dumpAnnos(
annotations: AnnotationSeq
): Unit = {
outAnno.foreach { annoPath =>
val outputFile = new java.io.PrintWriter(annoPath)
outputFile.write(JsonProtocol.serialize(annotations.filter(_ match {
case _: DeletedAnnotation => false
case _: EmittedComponent => false
case _: EmittedAnnotation[_] => false
case _: FirrtlCircuitAnnotation => false
case _: OutAnnoAnnotation => false
case _ => true
})))
outputFile.close()
}
}
def executeStageMain(): Unit = {
val annos = new FirrtlStage().execute(Array.empty, annotations)
annos.collectFirst { case FirrtlCircuitAnnotation(circuit) => circuit } match {
case Some(circuit) =>
dumpAnnos(annos)
case _ =>
throw new Exception(s"executeStageMain failed while executing FIRRTL!\n")
}
}
}
// main run class
object GenerateModelStageMain extends StageMain(new TapeoutStage())

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@@ -1,48 +0,0 @@
// See LICENSE for license details.
package tapeout.transforms.retime
import chisel3.experimental.RunFirrtlTransform
import firrtl.annotations._
import firrtl.stage.Forms
import firrtl.stage.TransformManager.TransformDependency
import firrtl.{CircuitState, DependencyAPIMigration, Transform}
case class RetimeAnnotation(target: Named) extends SingleTargetAnnotation[Named] {
override def duplicate(n: Named): Annotation = RetimeAnnotation(n)
}
class RetimeTransform extends Transform with DependencyAPIMigration {
override def prerequisites: Seq[TransformDependency] = Forms.LowForm
override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized
override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
override def invalidates(a: Transform): Boolean = false
override def execute(state: CircuitState): CircuitState = {
state.annotations.filter(_.isInstanceOf[RetimeAnnotation]) match {
case Nil => state
case seq =>
seq.foreach {
case RetimeAnnotation(ModuleName(module, CircuitName(_))) =>
logger.info(s"Retiming module $module")
case RetimeAnnotation(ComponentName(name, ModuleName(module, CircuitName(_)))) =>
logger.info(s"Retiming instance $module.$name")
case _ =>
throw new Exception(s"There should be RetimeAnnotations, got ${seq.mkString(" -- ")}")
}
state
}
}
}
trait RetimeLib {
self: chisel3.Module =>
def retime[T <: chisel3.Module](module: T): Unit = {
chisel3.experimental.annotate(new chisel3.experimental.ChiselAnnotation with RunFirrtlTransform {
def transformClass: Class[_ <: Transform] = classOf[RetimeTransform]
def toFirrtl: Annotation = RetimeAnnotation(module.toNamed)
})
}
}

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// See LICENSE for license details.
package tapeout.transforms.stage
import tapeout.transforms.GenerateModelStageMain
import chisel3.stage.ChiselCli
import firrtl.stage.{RunFirrtlTransformAnnotation}
import firrtl.AnnotationSeq
import firrtl.annotations.{Annotation, NoTargetAnnotation}
import firrtl.options.{HasShellOptions, Shell, ShellOption, Stage, Unserializable}
import firrtl.stage.FirrtlCli
import logger.Logger
sealed trait TapeoutOption extends Unserializable {
this: Annotation =>
}
case class OutAnnoAnnotation(outAnno: String) extends NoTargetAnnotation with TapeoutOption
object OutAnnoAnnotation extends HasShellOptions {
val options: Seq[ShellOption[_]] = Seq(
new ShellOption[String](
longOption = "out-anno-file",
shortOption = Some("oaf"),
toAnnotationSeq = (s: String) => Seq(OutAnnoAnnotation(s)),
helpText = "out-anno-file"
)
)
}
trait TapeoutCli {
this: Shell =>
parser.note("Tapeout specific options")
Seq(
OutAnnoAnnotation
).foreach(_.addOptions(parser))
}
class TapeoutStage() extends Stage {
override val shell: Shell = new Shell(applicationName = "tapeout") with TapeoutCli with ChiselCli with FirrtlCli
override def run(annotations: AnnotationSeq): AnnotationSeq = {
Logger.makeScope(annotations) {
val stageMain = new GenerateModelStageMain(annotations)
stageMain.executeStageMain()
}
annotations
}
}

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@@ -1,79 +0,0 @@
// See LICENSE for license details.
package tapeout.transforms.utils
import chisel3.experimental.{annotate, ChiselAnnotation}
import firrtl._
import firrtl.annotations._
import firrtl.stage.Forms
import firrtl.stage.TransformManager.TransformDependency
import firrtl.transforms.BlackBoxTargetDirAnno
object WriteConfig {
def apply(dir: String, file: String, contents: String): Unit = {
val writer = new java.io.PrintWriter(new java.io.File(s"$dir/$file"))
writer.write(contents)
writer.close()
}
}
object GetTargetDir {
def apply(state: CircuitState): String = {
val annos = state.annotations
val destDir = annos.map {
case BlackBoxTargetDirAnno(s) => Some(s)
case _ => None
}.flatten
val loc = {
if (destDir.isEmpty) "."
else destDir.head
}
val targetDir = new java.io.File(loc)
if (!targetDir.exists()) FileUtils.makeDirectory(targetDir.getAbsolutePath)
loc
}
}
trait HasSetTechnologyLocation {
self: chisel3.Module =>
def setTechnologyLocation(dir: String) {
annotate(new ChiselAnnotation {
override def toFirrtl: Annotation = {
TechnologyLocationAnnotation(dir)
}
})
}
}
case class TechnologyLocationAnnotation(dir: String) extends SingleTargetAnnotation[CircuitName] {
val target: CircuitName = CircuitName("All")
override def duplicate(n: CircuitName): Annotation = TechnologyLocationAnnotation(dir)
}
class TechnologyLocation extends Transform with DependencyAPIMigration {
override def prerequisites: Seq[TransformDependency] = Forms.LowForm
override def optionalPrerequisites: Seq[TransformDependency] = Forms.LowFormOptimized
override def optionalPrerequisiteOf: Seq[TransformDependency] = Forms.LowEmitters
def execute(state: CircuitState): CircuitState = {
throw new Exception("Technology Location transform execution doesn't work!")
}
def get(state: CircuitState): String = {
val annos = state.annotations
val dir = annos.flatMap {
case TechnologyLocationAnnotation(dir) => Some(dir)
case _ => None
}
dir.length match {
case 0 => ""
case 1 =>
val targetDir = new java.io.File(dir.head)
if (!targetDir.exists()) throw new Exception(s"Technology yaml directory $targetDir doesn't exist!")
dir.head
case _ => throw new Exception("Only 1 tech directory annotation allowed!")
}
}
}

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package tapeout.transforms.utils
object LowerName {
def apply(s: String): String = s.replace(".", "_").replace("[", "_").replace("]", "")
}

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package tapeout.transforms.utils
import chisel3._
import scala.collection.immutable.ListMap
class CustomBundle[T <: Data](elts: (String, T)*) extends Record {
val elements = ListMap(elts.map { case (field, elt) => field -> chiselTypeOf(elt) }: _*)
def apply(elt: String): T = elements(elt)
def apply(elt: Int): T = elements(elt.toString)
}
class CustomIndexedBundle[T <: Data](elts: (Int, T)*) extends Record {
// Must be String, Data
val elements = ListMap(elts.map { case (field, elt) => field.toString -> chiselTypeOf(elt) }: _*)
// TODO: Make an equivalent to the below work publicly (or only on subclasses?)
def indexedElements = ListMap(elts.map { case (field, elt) => field -> chiselTypeOf(elt) }: _*)
def apply(elt: Int): T = elements(elt.toString)
}
object CustomIndexedBundle {
def apply[T <: Data](gen: T, idxs: Seq[Int]) = new CustomIndexedBundle(idxs.map(_ -> gen): _*)
// Allows Vecs of elements of different types/widths
def apply[T <: Data](gen: Seq[T]) = new CustomIndexedBundle(gen.zipWithIndex.map { case (elt, field) =>
field -> elt
}: _*)
}

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package tapeout.transforms.utils
import firrtl.FileUtils
import net.jcazevedo.moultingyaml._
import java.io.File
class YamlFileReader(resource: String) {
def parse[A](file: String = "")(implicit reader: YamlReader[A]): Seq[A] = {
// If the user doesn't provide a Yaml file name, use defaults
val yamlString = file match {
case f if f.isEmpty =>
// Use example config if no file is provided
val stream = FileUtils.getTextResource(resource)
stream
case f if new File(f).exists =>
FileUtils.getText(f)
case _ =>
throw new Exception("No valid Yaml file found!")
}
yamlString.parseYamls.map(x => reader.read(x))
}
}