From 33f5040b5d3961130ad18164b139ce2e228949c8 Mon Sep 17 00:00:00 2001
From: joonho hwangbo <55655504+joey0320@users.noreply.github.com>
Date: Mon, 17 Oct 2022 18:41:39 -0700
Subject: [PATCH] Integrate Mempress memory tester (#1253)

---
 .github/scripts/check-commit.sh               |  2 +-
 .github/scripts/defaults.sh                   |  3 ++-
 .github/scripts/run-tests.sh                  |  4 +++
 .github/workflows/chipyard-run-tests.yml      | 26 +++++++++++++++++++
 .gitmodules                                   |  3 +++
 build.sbt                                     |  8 +++++-
 docs/Generators/Mempress.rst                  |  8 ++++++
 docs/Generators/index.rst                     |  1 +
 .../src/main/scala/config/RocketConfigs.scala | 10 +++++++
 .../fragments/PeripheralFragments.scala       |  4 +++
 generators/mempress                           |  1 +
 scripts/tutorial-patches/build.sbt.patch      |  9 +++----
 12 files changed, 71 insertions(+), 8 deletions(-)
 create mode 100644 docs/Generators/Mempress.rst
 create mode 160000 generators/mempress

diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
index e7af368f..70dfcf62 100755
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -47,7 +47,7 @@ search () {
     done
 }
 
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress")
 dir="generators"
 branches=("master" "main" "dev")
 search
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 046dac38..bc4adfae 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -27,7 +27,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
-grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
+grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
 grouping["group-other"]="icenet testchipip constellation"
@@ -39,6 +39,7 @@ mapping["chipyard-rocket"]=""
 mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
 mapping["chipyard-lbwif"]=" CONFIG=LBWIFRocketConfig"
 mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
+mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
 mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
 mapping["chipyard-streaming-fir"]=" CONFIG=StreamingFIRRocketConfig"
 mapping["chipyard-streaming-passthrough"]=" CONFIG=StreamingPassthroughRocketConfig"
diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index b35f4472..c9e190db 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -62,6 +62,10 @@ case $1 in
         (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv
         ;;
+    chipyard-mempress)
+        (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
+        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
+        ;;
     chipyard-streaming-passthrough)
         make -C $LOCAL_CHIPYARD_DIR/tests
         make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index bee8b802..d4351a98 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -791,6 +791,31 @@ jobs:
           group-key: "group-accels"
           project-key: "chipyard-nvdla"
 
+  chipyard-mempress-run-tests:
+    name: chipyard-mempress-run-tests
+    needs: prepare-chipyard-accels
+    runs-on: self-hosted
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-accels"
+          project-key: "chipyard-mempress"
+          toolchain: "esp-tools"
+
+
   tracegen-boom-run-tests:
     name: tracegen-boom-run-tests
     needs: prepare-chipyard-tracegen
@@ -1028,6 +1053,7 @@ jobs:
             chipyard-hwacha-run-tests,
             chipyard-gemmini-run-tests,
             chipyard-nvdla-run-tests,
+            chipyard-mempress-run-tests,
             chipyard-constellation-run-tests,
             tracegen-boom-run-tests,
             tracegen-run-tests,
diff --git a/.gitmodules b/.gitmodules
index e344395c..45f0bc50 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -130,3 +130,6 @@
 [submodule "generators/constellation"]
 	path = generators/constellation
 	url = https://github.com/ucb-bar/constellation.git
+[submodule "generators/mempress"]
+	path = generators/mempress
+	url = https://github.com/ucb-bar/mempress.git
diff --git a/build.sbt b/build.sbt
index 3703ef4c..ec36a85f 100644
--- a/build.sbt
+++ b/build.sbt
@@ -149,10 +149,16 @@ lazy val chipyard = (project in file("generators/chipyard"))
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsp-utils`,
     gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-    constellation)
+    constellation, mempress)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
+lazy val mempress = (project in file("generators/mempress"))
+  .dependsOn(rocketchip, midasTargetUtils)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(chiselTestSettings)
+  .settings(commonSettings)
+
 lazy val constellation = (project in file("generators/constellation"))
   .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
diff --git a/docs/Generators/Mempress.rst b/docs/Generators/Mempress.rst
new file mode 100644
index 00000000..17197fee
--- /dev/null
+++ b/docs/Generators/Mempress.rst
@@ -0,0 +1,8 @@
+Mempress
+====================================
+
+Mempress is a RoCC accelerator that generates memory requests through TileLink. It sends out requests as hard as it can to stress test the memory hierarchy of the Chipyard/Rocketchip-based SoC.
+
+Mempress can generate multiple **streams** of memory requests. Each stream can be set up to generate read or write requests and configured to generate strided or random access patterns. Furthermore, the memory footprint of each stream is also configurable.
+
+To add the Mempress unit into the SoC, you should add the ``mempress.WithMemPress`` config fragment to the SoC configurations.
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
index b491bae6..f499d591 100644
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -33,4 +33,5 @@ so changes to the generators themselves will automatically be used when building
    fft
    NVDLA
    Sodor
+   Mempress
 
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 73e13470..a082990e 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -21,6 +21,16 @@ class TinyRocketConfig extends Config(
   new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
   new chipyard.config.AbstractConfig)
 
+class MempressRocketConfig extends Config(
+  new mempress.WithMemPress ++                                    // use Mempress (memory traffic generation) accelerator
+  new freechips.rocketchip.subsystem.WithNBanks(8) ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=16, capacityKB=2048) ++
+  new chipyard.config.WithExtMemIdBits(7) ++                      // use 7 bits for tl like request id
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
 // DOC include start: FFTRocketConfig
 class FFTRocketConfig extends Config(
   new fftgenerator.WithFFTGenerator(numPoints=8, width=16, decPt=8) ++ // add 8-point mmio fft at the default addr (0x2400) with 16bit fixed-point numbers.
diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
index 0161edcc..f35a0b0d 100644
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -72,3 +72,7 @@ class WithSerialTLBackingMemory extends Config((site, here, up) => {
   )}
 })
 
+class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
+    case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
+})
+
diff --git a/generators/mempress b/generators/mempress
new file mode 160000
index 00000000..647519c1
--- /dev/null
+++ b/generators/mempress
@@ -0,0 +1 @@
+Subproject commit 647519c15e3d7f4aeb8c2c69adc0a64fa959a530
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
index 1064bb99..b97a0def 100644
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,8 +1,8 @@
 diff --git a/build.sbt b/build.sbt
-index bbbb8251..b7adcb73 100644
+index ec36a85f..c0c2849a 100644
 --- a/build.sbt
 +++ b/build.sbt
-@@ -143,8 +143,8 @@ lazy val testchipip = (project in file("generators/testchipip"))
+@@ -146,7 +146,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
  
  lazy val chipyard = (project in file("generators/chipyard"))
    .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
@@ -10,9 +10,8 @@ index bbbb8251..b7adcb73 100644
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, `rocket-dsp-utils`,
      gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
-     constellation)
-   .settings(libraryDependencies ++= rocketLibDeps.value)
-@@ -189,11 +189,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
+     constellation, mempress)
+@@ -204,11 +204,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
    .settings(libraryDependencies ++= rocketLibDeps.value)
    .settings(commonSettings)