From a44b043a2ae3c20bd0d0b787ab86010bc5d3ffab Mon Sep 17 00:00:00 2001 From: dpgrubb13 Date: Fri, 30 Aug 2019 18:57:11 -0700 Subject: [PATCH 01/20] additions to example-vlsi for asap7 demo --- vlsi/example-vlsi | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 3f65d9a5..5d43f8c5 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -8,12 +8,41 @@ from typing import Dict, Callable, Optional, List def example_place_tap_cells(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO +# Place custom TCL here +''') + return True + +def example_add_fillers(x: hammer_vlsi.HammerTool) -> bool: + x.append(''' +# TODO +# Place custom TCL here +''') + return True + +def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: + x.append(''' +# TODO +# Place custom TCL here ''') return True class ExampleDriver(CLIDriver): def get_extra_par_hooks(self) -> List[HammerToolHookAction]: - return [hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells)] + extra_hooks = [ + + # Default set of steps can be found in the CAD tool plugin's __init__.py + + # make_pre_insertion_hook will execute the custom hook before the specified step + hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # make_post_insertion_hook will execute the custom hook after the specified step + hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), + # make_replacement_hook will replace the specified step with a custom hook + hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # make_removal_hook will remove the specified step from the flow + hammer_vlsi.HammerTool.make_removal_hook("place_bumps") + # The target step in any of the above calls may be a default step or another one of your custom hooks + ] + return extra_hooks if __name__ == '__main__': ExampleDriver().main() From 859492c2a2d5be518da552b08ddd23c0c32473c2 Mon Sep 17 00:00:00 2001 From: dpgrubb13 Date: Sat, 31 Aug 2019 00:40:25 -0700 Subject: [PATCH 02/20] added starter example.yml --- vlsi/example.yml | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 vlsi/example.yml diff --git a/vlsi/example.yml b/vlsi/example.yml new file mode 100644 index 00000000..790479c9 --- /dev/null +++ b/vlsi/example.yml @@ -0,0 +1,35 @@ +# Technology Setup +# Technology used is ASAP7 +vlsi.core.technology: asap7 +vlsi.core.node: 7 +technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL" +technology.asap7.install_dir: "SPECIFY EXTRACTED DIR HERE IF NOT USING TARBALL" + +vlsi.core.max_threads: 12 + +# General Hammer Inputs + +vlsi.inputs.supplies.VDD: "0.7 V" + +# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info +vlsi.inputs.power_spec_mode: "auto" + +# Specify the setup and hold corners for ASAP7 +vlsi.inputs.mmmc_corners: [ + {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"}, + {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"} +] + +# Specify clock signals +vlsi.inputs.clocks: [ + {name: "clock", period: "10ns", uncertainty: "0.1ns"} +] + +# Generate Make include to aid in flow +vlsi.core.build_system: make + +# Power Straps +par.power_straps_mode: generate + +# Placement Constraints +#vlsi.inputs.placement_constraints: From 6179a91a294e832f035e8e125eb450ecb04766e7 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sat, 31 Aug 2019 20:04:35 -0700 Subject: [PATCH 03/20] some plumbing but still need to remove sram generator target for asap7 --- .gitmodules | 12 ++++++-- scripts/init-vlsi.sh | 10 ++++-- vlsi/Makefile | 8 ++--- vlsi/README.md | 60 +++++++++++++++++++++++++++++++++--- vlsi/bwrc-env.yml | 7 +++++ vlsi/example.yml | 54 +++++++++++++++++++++++++++++++- vlsi/hammer | 2 +- vlsi/hammer-cad-plugins | 1 - vlsi/hammer-cadence-plugins | 1 + vlsi/hammer-mentor-plugins | 1 + vlsi/hammer-synopsys-plugins | 1 + 11 files changed, 140 insertions(+), 17 deletions(-) create mode 100644 vlsi/bwrc-env.yml delete mode 160000 vlsi/hammer-cad-plugins create mode 160000 vlsi/hammer-cadence-plugins create mode 160000 vlsi/hammer-mentor-plugins create mode 160000 vlsi/hammer-synopsys-plugins diff --git a/.gitmodules b/.gitmodules index 4bbfaa97..35addf76 100644 --- a/.gitmodules +++ b/.gitmodules @@ -43,9 +43,6 @@ [submodule "vlsi/hammer"] path = vlsi/hammer url = https://github.com/ucb-bar/hammer.git -[submodule "vlsi/hammer-cad-plugins"] - path = vlsi/hammer-cad-plugins - url = https://github.com/ucb-bar/hammer-cad-plugins.git [submodule "tools/dsptools"] path = tools/dsptools url = https://github.com/ucb-bar/dsptools.git @@ -61,3 +58,12 @@ [submodule "tools/firrtl-interpreter"] path = tools/firrtl-interpreter url = https://github.com/freechipsproject/firrtl-interpreter.git +[submodule "vlsi/hammer-cadence-plugins"] + path = vlsi/hammer-cadence-plugins + url = git@github.com:ucb-bar/hammer-cadence-plugins.git +[submodule "vlsi/hammer-synopsys-plugins"] + path = vlsi/hammer-synopsys-plugins + url = git@github.com:ucb-bar/hammer-synopsys-plugins.git +[submodule "vlsi/hammer-mentor-plugins"] + path = vlsi/hammer-mentor-plugins + url = git@github.com:ucb-bar/hammer-mentor-plugins.git diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh index 89f9ac56..aaf015ca 100755 --- a/scripts/init-vlsi.sh +++ b/scripts/init-vlsi.sh @@ -1,11 +1,15 @@ #!/usr/bin/env bash -# exit script if any command fails +# exit script if any command fails set -e set -o pipefail # Initialize HAMMER and CAD-plugins git submodule update --init --recursive vlsi/hammer -git submodule update --init --recursive vlsi/hammer-cad-plugins +git submodule update --init --recursive vlsi/hammer-cadence-plugins +git submodule update --init --recursive vlsi/hammer-synopsys-plugins +git submodule update --init --recursive vlsi/hammer-mentor-plugins # Initialize HAMMER tech plugin -git submodule update --init --recursive vlsi/hammer-"$1"-plugin +if [[ $1 != *asap7* ]] && [[ $1 != *saed32* ]]; then + git submodule update --init --recursive vlsi/hammer-$1-plugin +fi diff --git a/vlsi/Makefile b/vlsi/Makefile index 519d1448..6fcedd62 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -18,15 +18,15 @@ include $(base_dir)/variables.mk # vlsi types and rules ######################################################################################### sim_name ?= vcs # needed for GenerateSimFiles, but is unused -tech_name ?= -tech_dir ?= $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name) +tech_name ?= asap7 +tech_dir ?= $(if $(filter $(tech_name), asap7 saed32), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json -SMEMS_CACHE ?= $(tech_dir)/sram-cache.json +cMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) OBJ_DIR ?= $(vlsi_dir)/build ENV_YML ?= $(vlsi_dir)/bwrc-env.yml -INPUT_CONFS ?= example.yml $(dir $(tech_dir))/bwrc.yml +INPUT_CONFS ?= example.yml HAMMER_EXEC ?= ./example-vlsi ######################################################################################### diff --git a/vlsi/README.md b/vlsi/README.md index aa07dd0f..0ee8978d 100644 --- a/vlsi/README.md +++ b/vlsi/README.md @@ -2,8 +2,60 @@ This is the starting point for a vlsi flow from this repository. This flow will not work without the necessary CAD and technology plugins for HAMMER. -If you are a UCB-affiliate, you may be able to acquire access to the tech-plugins. +If you are a UCB-affiliate, you may be able to acquire access to the tool & tech plugins. -# Initial Setup Instructions (For All technologies) -Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-cad-plugins, and the hammer-tech-plugins -```scripts/init-vlsi.sh TECH_NAME``` \ No newline at end of file +# Initial Setup Instructions (For all technologies) +Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the included technology 'asap7' is already included and will not submodule a tech plugin. +```shell +scripts/init-vlsi.sh TECH_NAME +``` + +An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment. + +Finally, set up all prerequisites for the build system: +```shell +make buildfile +``` + +# Example design +In this example, you will be running a SHA-3 accelerator through the VLSI flow. It is assumed that you have already run through the flow to elaborate the Chisel into Verilog. + +HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself. + +We start by pulling the HAMMER environment into the shell: + +```shell +export HAMMER_HOME=$PWD/hammer +source $HAMMER_HOME/sourceme.sh +``` + +The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks. + +To synthesize a design: + +```shell +make syn +``` + +The outputs are written to a log file with a timestamp and the post-synthesis results are in `build/syn-rundir`. + +Raw QoR data is available at `build/syn-rundir/reports`, and work is planned to extract this information in a more programmatic manner. + +To run place and route: +```shell +make par +``` + +If successful, the resulting chip can be opened via `./build/par-rundir/generated-scripts/open_chip`. + +To run DRC and view violations: +```shell +make drc +./build/drc-rundir/generated-scripts/view-drc +``` + +To run LVS and view violations: +```shell +make lvs +./build/lvs-rundir/generated-scripts/view-lvs +``` diff --git a/vlsi/bwrc-env.yml b/vlsi/bwrc-env.yml new file mode 100644 index 00000000..f68eab24 --- /dev/null +++ b/vlsi/bwrc-env.yml @@ -0,0 +1,7 @@ +mentor.mentor_home: "/tools/mentor" +mentor.MGLS_LICENSE_FILE: "1717@bwrcflex-1.eecs.berkeley.edu:1717@bwrcflex-2.eecs.berkeley.edu" +cadence.cadence_home: "/tools/cadence" +cadence.CDS_LIC_FILE: "5280@bwrcflex-1.eecs.berkeley.edu:5280@bwrcflex-2.eecs.berkeley.edu" +synopsys.synopsys_home: "/tools/synopsys" +synopsys.SNPSLMD_LICENSE_FILE: "1701@bwrcflex-1.eecs.berkeley.edu:1701@bwrcflex-2.eecs.berkeley.edu" +synopsys.MGLS_LICENSE_FILE: "1717@bwrcflex-1.eecs.berkeley.edu:1717@bwrcflex-2.eecs.berkeley.edu" diff --git a/vlsi/example.yml b/vlsi/example.yml index 790479c9..5711e71a 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -30,6 +30,58 @@ vlsi.core.build_system: make # Power Straps par.power_straps_mode: generate +par.generate_power_straps_method: by_tracks +par.blockage_spacing: 2.0 +par.generate_power_straps_options: + by_tracks: + strap_layers: + - M3 + - M4 + - M5 + - M6 + - M7 + - M8 + - M9 + track_width: 6 + track_spacing: 0 + power_utilization: 0.05 + power_utilization_M8: 1.0 + power_utilization_M9: 1.0 # Placement Constraints -#vlsi.inputs.placement_constraints: +vlsi.inputs.placement_constraints: + - path: "ExampleTop" + type: "toplevel" + x: 0 + y: 0 + width: 50 + height: 50 + margins: + left: 0 + right: 0 + top: 0 + bottom: 0 + +# SRAM Compiler compiler options +vlsi.core.sram_generator_tool: "sram_compiler" +vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"] +vlsi.core.sram_generator_tool_path_meta: "append" + +# Tool options. Replace with your tool plugin of choice. +# Genus options +vlsi.core.synthesis_tool: "genus" +vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"] +vlsi.core.synthesis_tool_path_meta: "append" +synthesis.genus.version: "181" +# Innovus options +vlsi.core.par_tool: "innovus" +vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] +vlsi.core.par_tool_path_meta: "append" +par.innovus.version: "181" +par.innovus.design_flow_effort: "standard" +par.inputs.gds_merge: true +# Calibre options +vlsi.core.drc_tool: "calibre" +vlsi.core.drc_tool_path: ["hammer-cad-plugins/drc"] +vlsi.core.lvs_tool: "calibre" +vlsi.core.lvs_tool_path: ["hammer-cad-plugins/lvs"] diff --git a/vlsi/hammer b/vlsi/hammer index a27886fb..6c31fbe7 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 +Subproject commit 6c31fbe7eb57df98c5815ae4f7ba2ba904f74b0f diff --git a/vlsi/hammer-cad-plugins b/vlsi/hammer-cad-plugins deleted file mode 160000 index 72809f53..00000000 --- a/vlsi/hammer-cad-plugins +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 72809f538c4bbe91c103de52e92baad9df6d8f9a diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins new file mode 160000 index 00000000..a0741281 --- /dev/null +++ b/vlsi/hammer-cadence-plugins @@ -0,0 +1 @@ +Subproject commit a07412814b878c67d79f7aada598848bcb4c197c diff --git a/vlsi/hammer-mentor-plugins b/vlsi/hammer-mentor-plugins new file mode 160000 index 00000000..4daaea36 --- /dev/null +++ b/vlsi/hammer-mentor-plugins @@ -0,0 +1 @@ +Subproject commit 4daaea36f805ba71b55ceb7f5579229eac935045 diff --git a/vlsi/hammer-synopsys-plugins b/vlsi/hammer-synopsys-plugins new file mode 160000 index 00000000..e0ace734 --- /dev/null +++ b/vlsi/hammer-synopsys-plugins @@ -0,0 +1 @@ +Subproject commit e0ace7345e98e11b17ce550550c902782010e032 From fb357828415d513e36a410259cdefdd707a23f07 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 1 Sep 2019 10:42:49 -0700 Subject: [PATCH 04/20] fix incorrect block for syn/par, but still have timing violations --- vlsi/README.md | 10 +++++++++- vlsi/example.yml | 30 ++++++++++++++++++++---------- 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/vlsi/README.md b/vlsi/README.md index 0ee8978d..05179ca6 100644 --- a/vlsi/README.md +++ b/vlsi/README.md @@ -18,7 +18,15 @@ make buildfile ``` # Example design -In this example, you will be running a SHA-3 accelerator through the VLSI flow. It is assumed that you have already run through the flow to elaborate the Chisel into Verilog. +In this example, you will be running a SHA-3 accelerator through the VLSI flow. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system: +```shell +export MACROCOMPILER_MODE=' --mode synflops' +export CONFIG=Sha3RocketConfig +export TOP=Sha3Accel +make buildfile +``` +Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. +>>>>>>> fix incorrect block for syn/par, but still have timing violations HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself. diff --git a/vlsi/example.yml b/vlsi/example.yml index 5711e71a..ffa7e732 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -2,8 +2,10 @@ # Technology used is ASAP7 vlsi.core.technology: asap7 vlsi.core.node: 7 -technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL" -technology.asap7.install_dir: "SPECIFY EXTRACTED DIR HERE IF NOT USING TARBALL" +# Specify dir with ASAP7 tarball +technology.asap7.tarball_dir: "/tools/B/asap7" +# Specify extracted dir here if not using tarball +technology.asap7.install_dir: "/tools/B/asap7" vlsi.core.max_threads: 12 @@ -13,16 +15,17 @@ vlsi.inputs.supplies.VDD: "0.7 V" # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info vlsi.inputs.power_spec_mode: "auto" +vlsi.inputs.power_spec_type: "cpf" # Specify the setup and hold corners for ASAP7 vlsi.inputs.mmmc_corners: [ - {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"}, - {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"} + {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"}, + {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"} ] # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "10ns", uncertainty: "0.1ns"} + {name: "clock", period: "20ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow @@ -50,18 +53,25 @@ par.generate_power_straps_options: # Placement Constraints vlsi.inputs.placement_constraints: - - path: "ExampleTop" + - path: "Sha3Accel" type: "toplevel" x: 0 y: 0 - width: 50 - height: 50 + width: 500 + height: 500 margins: left: 0 right: 0 top: 0 bottom: 0 +# Pin placement constraints +vlsi.inputs.pin_mode: generated +vlsi.inputs.pin.generate_mode: semi_auto +vlsi.inputs.pin.assignments: [ + {pins: "*", layers: ["M5", "M7"], side: "bottom"} +] + # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"] @@ -82,6 +92,6 @@ par.innovus.design_flow_effort: "standard" par.inputs.gds_merge: true # Calibre options vlsi.core.drc_tool: "calibre" -vlsi.core.drc_tool_path: ["hammer-cad-plugins/drc"] +vlsi.core.drc_tool_path: ["hammer-mentor-plugins/drc"] vlsi.core.lvs_tool: "calibre" -vlsi.core.lvs_tool_path: ["hammer-cad-plugins/lvs"] +vlsi.core.lvs_tool_path: ["hammer-mentor-plugins/lvs"] From 6bc91680cddcefcd0922a086ea5c457fedf94bbb Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 1 Sep 2019 14:12:49 -0700 Subject: [PATCH 05/20] rebased on dev --- vlsi/README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/vlsi/README.md b/vlsi/README.md index 05179ca6..7df19a12 100644 --- a/vlsi/README.md +++ b/vlsi/README.md @@ -18,7 +18,7 @@ make buildfile ``` # Example design -In this example, you will be running a SHA-3 accelerator through the VLSI flow. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system: +In this example, you will be running a SHA-3 accelerator through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system: ```shell export MACROCOMPILER_MODE=' --mode synflops' export CONFIG=Sha3RocketConfig @@ -26,7 +26,6 @@ export TOP=Sha3Accel make buildfile ``` Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. ->>>>>>> fix incorrect block for syn/par, but still have timing violations HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself. @@ -39,6 +38,8 @@ source $HAMMER_HOME/sourceme.sh The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks. +In order to install the process, edit the keys `vlsi.technology.asap7.tarball_dir` if you already have the ASAP7 tarball downloaded and `vlsi.technology.asap7.install_dir` if you have already extracted it. If omitted, Hammer will automatically download and extract the tarballs into the `build/asap7-tech-cache` directory when you first run synthesis. + To synthesize a design: ```shell From 6ad433d5c72d69a917ff8fa0c50de752b993d46d Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 1 Sep 2019 18:09:38 -0700 Subject: [PATCH 06/20] power straps fixes, sha3 w/ dco skeleton --- vlsi/Makefile | 4 +- vlsi/README.md | 11 +- vlsi/example.v | 154 +++++++++++++ vlsi/example.yml | 41 +++- vlsi/extra_libraries/dco/dco.gds | Bin 0 -> 10240 bytes vlsi/extra_libraries/dco/dco.lef | 376 +++++++++++++++++++++++++++++++ vlsi/hammer-cadence-plugins | 2 +- 7 files changed, 575 insertions(+), 13 deletions(-) create mode 100644 vlsi/example.v create mode 100644 vlsi/extra_libraries/dco/dco.gds create mode 100644 vlsi/extra_libraries/dco/dco.lef diff --git a/vlsi/Makefile b/vlsi/Makefile index 6fcedd62..f4697a9b 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -33,7 +33,7 @@ HAMMER_EXEC ?= ./example-vlsi # general rules ######################################################################################### ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes) -extra_v_includes = $(build_dir)/EICG_wrapper.v +extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v .PHONY: default verilog default: all @@ -74,7 +74,7 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) $(SRAM_CONF) +GENERATED_CONFS = $(SYN_CONF) $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) $(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes) mkdir -p $(dir $@) diff --git a/vlsi/README.md b/vlsi/README.md index 7df19a12..12cb6fd9 100644 --- a/vlsi/README.md +++ b/vlsi/README.md @@ -7,22 +7,17 @@ If you are a UCB-affiliate, you may be able to acquire access to the tool & tech # Initial Setup Instructions (For all technologies) Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the included technology 'asap7' is already included and will not submodule a tech plugin. ```shell -scripts/init-vlsi.sh TECH_NAME +./scripts/init-vlsi.sh TECH_NAME ``` An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment. -Finally, set up all prerequisites for the build system: -```shell -make buildfile -``` - # Example design -In this example, you will be running a SHA-3 accelerator through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system: +In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system: ```shell export MACROCOMPILER_MODE=' --mode synflops' export CONFIG=Sha3RocketConfig -export TOP=Sha3Accel +export TOP=Sha3AccelwBB make buildfile ``` Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. diff --git a/vlsi/example.v b/vlsi/example.v new file mode 100644 index 00000000..bd0d3f9d --- /dev/null +++ b/vlsi/example.v @@ -0,0 +1,154 @@ +// Extracted Sha3Accel w/ a blackbox (a dummy DCO) included inside + +module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] + input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4] + input reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4] + output io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input [6:0] io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + output io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + output [7:0] io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + output [4:0] io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input [7:0] io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + output io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4] + input [13:0] col_sel_b, + input [15:0] row_sel_b, + input [7:0] code_regulator, + input dither, + input sleep_b, + output dco_clock +); + wire clock; // from dummy DCO + wire ctrl_clock; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_reset; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_rocc_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_rocc_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [1:0] ctrl_io_rocc_funct; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [63:0] ctrl_io_rocc_rs1; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [63:0] ctrl_io_rocc_rs2; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_busy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_dmem_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_dmem_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [6:0] ctrl_io_dmem_req_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [31:0] ctrl_io_dmem_req_addr; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [4:0] ctrl_io_dmem_req_cmd; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_dmem_resp_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [6:0] ctrl_io_dmem_resp_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [63:0] ctrl_io_dmem_resp_data; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [4:0] ctrl_io_round; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_absorb; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [4:0] ctrl_io_aindex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_init; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire ctrl_io_write; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [2:0] ctrl_io_windex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire [63:0] ctrl_io_buffer_out; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + wire dpath_clock; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire dpath_reset; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire dpath_io_absorb; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire dpath_io_init; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire dpath_io_write; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [4:0] dpath_io_round; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [4:0] dpath_io_aindex; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [63:0] dpath_io_message_in; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [63:0] dpath_io_hash_out_0; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [63:0] dpath_io_hash_out_1; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [63:0] dpath_io_hash_out_2; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [63:0] dpath_io_hash_out_3; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + wire [1:0] _T; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4] + wire [63:0] _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + wire [63:0] _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + wire [63:0] _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + CtrlModule ctrl ( // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] + .clock(ctrl_clock), + .reset(ctrl_reset), + .io_rocc_req_val(ctrl_io_rocc_req_val), + .io_rocc_req_rdy(ctrl_io_rocc_req_rdy), + .io_rocc_funct(ctrl_io_rocc_funct), + .io_rocc_rs1(ctrl_io_rocc_rs1), + .io_rocc_rs2(ctrl_io_rocc_rs2), + .io_busy(ctrl_io_busy), + .io_dmem_req_val(ctrl_io_dmem_req_val), + .io_dmem_req_rdy(ctrl_io_dmem_req_rdy), + .io_dmem_req_tag(ctrl_io_dmem_req_tag), + .io_dmem_req_addr(ctrl_io_dmem_req_addr), + .io_dmem_req_cmd(ctrl_io_dmem_req_cmd), + .io_dmem_resp_val(ctrl_io_dmem_resp_val), + .io_dmem_resp_tag(ctrl_io_dmem_resp_tag), + .io_dmem_resp_data(ctrl_io_dmem_resp_data), + .io_round(ctrl_io_round), + .io_absorb(ctrl_io_absorb), + .io_aindex(ctrl_io_aindex), + .io_init(ctrl_io_init), + .io_write(ctrl_io_write), + .io_windex(ctrl_io_windex), + .io_buffer_out(ctrl_io_buffer_out) + ); + DpathModule dpath ( // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] + .clock(dpath_clock), + .reset(dpath_reset), + .io_absorb(dpath_io_absorb), + .io_init(dpath_io_init), + .io_write(dpath_io_write), + .io_round(dpath_io_round), + .io_aindex(dpath_io_aindex), + .io_message_in(dpath_io_message_in), + .io_hash_out_0(dpath_io_hash_out_0), + .io_hash_out_1(dpath_io_hash_out_1), + .io_hash_out_2(dpath_io_hash_out_2), + .io_hash_out_3(dpath_io_hash_out_3) + ); + ExampleDCO dco ( + .col_sel_b(col_sel_b), + .row_sel_b(row_sel_b), + .code_regulator(code_regulator), + .dither(dither), + .sleep_b(sleep_b), + .clock(dco_clock) + ); + assign _T = ctrl_io_windex[1:0]; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4] + assign _GEN_0 = dpath_io_hash_out_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + assign _GEN_1 = 2'h1 == _T ? dpath_io_hash_out_1 : _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + assign _GEN_2 = 2'h2 == _T ? dpath_io_hash_out_2 : _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + assign io_cmd_ready = ctrl_io_rocc_req_rdy; // @[sha3.scala 64:16:example.TestHarness.Sha3RocketConfig.fir@135921.4] + assign io_mem_req_valid = ctrl_io_dmem_req_val; // @[sha3.scala 71:20:example.TestHarness.Sha3RocketConfig.fir@135927.4] + assign io_mem_req_bits_addr = {{8'd0}, ctrl_io_dmem_req_addr}; // @[sha3.scala 74:24:example.TestHarness.Sha3RocketConfig.fir@135930.4] + assign io_mem_req_bits_tag = {{1'd0}, ctrl_io_dmem_req_tag}; // @[sha3.scala 73:23:example.TestHarness.Sha3RocketConfig.fir@135929.4] + assign io_mem_req_bits_cmd = ctrl_io_dmem_req_cmd; // @[sha3.scala 75:23:example.TestHarness.Sha3RocketConfig.fir@135931.4] + assign io_mem_req_bits_data = 2'h3 == _T ? dpath_io_hash_out_3 : _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] + assign io_busy = ctrl_io_busy; // @[sha3.scala 69:11:example.TestHarness.Sha3RocketConfig.fir@135926.4] + assign ctrl_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135918.4] + assign ctrl_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135919.4] + assign ctrl_io_rocc_req_val = io_cmd_valid; // @[sha3.scala 63:26:example.TestHarness.Sha3RocketConfig.fir@135920.4] + assign ctrl_io_rocc_funct = io_cmd_bits_inst_funct[1:0]; // @[sha3.scala 65:26:example.TestHarness.Sha3RocketConfig.fir@135922.4] + assign ctrl_io_rocc_rs1 = io_cmd_bits_rs1; // @[sha3.scala 66:26:example.TestHarness.Sha3RocketConfig.fir@135923.4] + assign ctrl_io_rocc_rs2 = io_cmd_bits_rs2; // @[sha3.scala 67:26:example.TestHarness.Sha3RocketConfig.fir@135924.4] + assign ctrl_io_dmem_req_rdy = io_mem_req_ready; // @[sha3.scala 72:26:example.TestHarness.Sha3RocketConfig.fir@135928.4] + assign ctrl_io_dmem_resp_val = io_mem_resp_valid; // @[sha3.scala 78:26:example.TestHarness.Sha3RocketConfig.fir@135933.4] + assign ctrl_io_dmem_resp_tag = io_mem_resp_bits_tag[6:0]; // @[sha3.scala 79:26:example.TestHarness.Sha3RocketConfig.fir@135934.4] + assign ctrl_io_dmem_resp_data = io_mem_resp_bits_data; // @[sha3.scala 80:26:example.TestHarness.Sha3RocketConfig.fir@135935.4] + assign dpath_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135938.4] + assign dpath_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135939.4] + assign dpath_io_absorb = ctrl_io_absorb; // @[sha3.scala 88:19:example.TestHarness.Sha3RocketConfig.fir@135943.4] + assign dpath_io_init = ctrl_io_init; // @[sha3.scala 89:17:example.TestHarness.Sha3RocketConfig.fir@135944.4] + assign dpath_io_write = ctrl_io_write; // @[sha3.scala 90:18:example.TestHarness.Sha3RocketConfig.fir@135945.4] + assign dpath_io_round = ctrl_io_round; // @[sha3.scala 91:18:example.TestHarness.Sha3RocketConfig.fir@135946.4] + assign dpath_io_aindex = ctrl_io_aindex; // @[sha3.scala 93:19:example.TestHarness.Sha3RocketConfig.fir@135948.4] + assign dpath_io_message_in = ctrl_io_buffer_out; // @[sha3.scala 84:23:example.TestHarness.Sha3RocketConfig.fir@135940.4] +endmodule + +module ExampleDCO ( + input [13:0] col_sel_b, + input [15:0] row_sel_b, + input [7:0] code_regulator, + input dither, + input sleep_b, + output clock +); +endmodule diff --git a/vlsi/example.yml b/vlsi/example.yml index ffa7e732..8616fa33 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -45,7 +45,11 @@ par.generate_power_straps_options: - M7 - M8 - M9 - track_width: 6 + track_width: 14 + track_width_M3: 7 + track_width_M5: 24 + track_width_M8: 6 + track_width_M9: 6 track_spacing: 0 power_utilization: 0.05 power_utilization_M8: 1.0 @@ -53,7 +57,7 @@ par.generate_power_straps_options: # Placement Constraints vlsi.inputs.placement_constraints: - - path: "Sha3Accel" + - path: "Sha3AccelwBB" type: "toplevel" x: 0 y: 0 @@ -64,6 +68,13 @@ vlsi.inputs.placement_constraints: right: 0 top: 0 bottom: 0 + - path: "Sha3AccelwBB/dco" + type: "hardmacro" + x: 400 + y: 400 + width: 32 + height: 32 + orientation: "r0" # Pin placement constraints vlsi.inputs.pin_mode: generated @@ -72,6 +83,32 @@ vlsi.inputs.pin.assignments: [ {pins: "*", layers: ["M5", "M7"], side: "bottom"} ] +# Paths to extra libraries +vlsi.technology.extra_libraries_meta: "append" +vlsi.technology.extra_libraries: + - library: + nldm liberty file: "extra_libraries/dco/dco_SS.lib" + lef file: "extra_libraries/dco/dco.lef" + gds file: "extra_libraries/dco/dco.gds" + corner: + nmos: "slow" + pmos: "slow" + temperature: "100 C" + supplies: + VDD: "0.63 V" + GND: "0 V" + - library: + nldm liberty file: "extra_libraries/dco/dco_FF.lib" + lef file: "extra_libraries/dco/dco.lef" + gds file: "extra_libraries/dco/dco.gds" + corner: + nmos: "fast" + pmos: "fast" + temperature: "0 C" + supplies: + VDD: "0.77 V" + GND: "0 V" + # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"] diff --git a/vlsi/extra_libraries/dco/dco.gds b/vlsi/extra_libraries/dco/dco.gds new file mode 100644 index 0000000000000000000000000000000000000000..e5cb24a3df152a78dc21db0693f32454f1c25e9d GIT binary patch literal 10240 zcmeI1Pi$009LIlC+SgSoY>{9K#c*oZ1WhTRB@wzN#8kkf2>}|3>GsdY8W*-H5DH$J z2-q7%V^aS>dh6CxgJ^of<<qz~Y zA{Cz^wM<2BYL+<2-&fX>)hCLP+C5LSF<0c?PQDM0gZ%x!`}|+Gjv-&_(Oyfq*`$Z@BCJ10JvPlyk4 z-09y7U^LuKN${92OtsxYIw}E8) z`j1A$2Y-)=4|3e}pAXl6mErnNKX>@-ybc8Qnh>Ayz3Fc*(|@r{U)Hbw_uo=x`|p(L zzh0*QW|@9RnZEQtmAQWqUk}vPx{ErDx(izCuiU~RU6A9>{zKgbQFlRW{WaQ0-33v1L2Lar{KM^X{~+ov z$Z_ZWqwa#JyP&oHqJ7`}JA8hBQMW+{hLeTgV^_i9C!K?t>S~&cY_>v`q=k_*!P3h z{lC$FS7)Ss5a$jc$DQrt+ylHkD*X>y&p(Xzaqa@*+y%6rzZiaIT<#ylxev&3=l$c{ z3GC^Y`v}V z8KX`0!C>}$*O_#ttLNmdz3=*D;&*aer+%Kk_s{mH2iM-C{4CTIr!Cwg*}inwVEVmt zneMaM!IRCt_tP?C$+pWk+ks(Awie%PhgvP!cKc>Kwq(h+$2VJd&XUc0RGdm#vc2ki zZx`w;*Cf zlvkeb`=fbyFnQ&V=Xg|C z#-n*W-w$O?-8$8&yFM`F=Dp7Xs*c0}`d)*qEv z&~JvZhV!lcYI~w2llKh5tJ~;3dCwqK( Date: Sun, 1 Sep 2019 18:13:11 -0700 Subject: [PATCH 07/20] shouldn't have tools/B --- vlsi/example.yml | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/vlsi/example.yml b/vlsi/example.yml index 8616fa33..d4251ad2 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -2,10 +2,8 @@ # Technology used is ASAP7 vlsi.core.technology: asap7 vlsi.core.node: 7 -# Specify dir with ASAP7 tarball -technology.asap7.tarball_dir: "/tools/B/asap7" -# Specify extracted dir here if not using tarball -technology.asap7.install_dir: "/tools/B/asap7" +technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL" +technology.asap7.install_dir: "SPECIFY EXTRACTED DIR HERE IF NOT USING TARBALL" vlsi.core.max_threads: 12 From d28077ff0b71939a501dafc74e7ec45039951df6 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Mon, 2 Sep 2019 16:59:14 -0700 Subject: [PATCH 08/20] updated DCO collateral --- vlsi/README.md | 17 ++- vlsi/example.yml | 20 ++- vlsi/extra_libraries/dco/ExampleDCO.gds | Bin 0 -> 10240 bytes .../dco/{dco.lef => ExampleDCO.lef} | 100 ++++++------ .../dco/ExampleDCO_PVT_0P63V_100C.lib | 142 ++++++++++++++++++ .../dco/ExampleDCO_PVT_0P77V_0C.lib | 142 ++++++++++++++++++ vlsi/extra_libraries/dco/dco.gds | Bin 10240 -> 0 bytes 7 files changed, 359 insertions(+), 62 deletions(-) create mode 100644 vlsi/extra_libraries/dco/ExampleDCO.gds rename vlsi/extra_libraries/dco/{dco.lef => ExampleDCO.lef} (76%) create mode 100644 vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib create mode 100644 vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib delete mode 100644 vlsi/extra_libraries/dco/dco.gds diff --git a/vlsi/README.md b/vlsi/README.md index 12cb6fd9..29fd2bc7 100644 --- a/vlsi/README.md +++ b/vlsi/README.md @@ -1,3 +1,4 @@ +# HAMMER VLSI flow This is the starting point for a vlsi flow from this repository. This flow will not work without the necessary CAD and technology plugins for HAMMER. @@ -5,7 +6,7 @@ This flow will not work without the necessary CAD and technology plugins for HAM If you are a UCB-affiliate, you may be able to acquire access to the tool & tech plugins. # Initial Setup Instructions (For all technologies) -Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the included technology 'asap7' is already included and will not submodule a tech plugin. +Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the technologies `asap7` and `saed32` are already included and will not submodule a tech plugin. ```shell ./scripts/init-vlsi.sh TECH_NAME ``` @@ -13,15 +14,16 @@ Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_V An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment. # Example design -In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system: +## Building the design +In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system: ```shell export MACROCOMPILER_MODE=' --mode synflops' export CONFIG=Sha3RocketConfig -export TOP=Sha3AccelwBB make buildfile ``` Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. +## Using HAMMER HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself. We start by pulling the HAMMER environment into the shell: @@ -33,10 +35,15 @@ source $HAMMER_HOME/sourceme.sh The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks. -In order to install the process, edit the keys `vlsi.technology.asap7.tarball_dir` if you already have the ASAP7 tarball downloaded and `vlsi.technology.asap7.install_dir` if you have already extracted it. If omitted, Hammer will automatically download and extract the tarballs into the `build/asap7-tech-cache` directory when you first run synthesis. +In order to install the process, download (and optionally extract) the ASAP7 PDK tarball. Then, edit the key `vlsi.technology.asap7.tarball_dir` if you want Hammer to extract for you or `vlsi.technology.asap7.install_dir` if you have already extracted it. -To synthesize a design: +To synthesize the just the SHA-3 accelerator with the hard macro we have to change the physical top module (this step is not necessary if you are pushing the entire Rocket-chip through the VLSI flow): +```shell +export TOP=Sha3AccelwBB +rm build/inputs.yml +``` +Then, to run synthesis: ```shell make syn ``` diff --git a/vlsi/example.yml b/vlsi/example.yml index d4251ad2..1c92731e 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -82,12 +82,15 @@ vlsi.inputs.pin.assignments: [ ] # Paths to extra libraries -vlsi.technology.extra_libraries_meta: "append" +vlsi.technology.extra_libraries_meta: ["append", "deepsubst"] vlsi.technology.extra_libraries: - library: - nldm liberty file: "extra_libraries/dco/dco_SS.lib" - lef file: "extra_libraries/dco/dco.lef" - gds file: "extra_libraries/dco/dco.gds" + nldm liberty file_deepsubst_meta: "local" + nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib" + lef file_deepsubst_meta: "local" + lef file: "extra_libraries/dco/ExampleDCO.lef" + gds file_deepsubst_meta: "local" + gds file: "extra_libraries/dco/ExampleDCO.gds" corner: nmos: "slow" pmos: "slow" @@ -96,9 +99,12 @@ vlsi.technology.extra_libraries: VDD: "0.63 V" GND: "0 V" - library: - nldm liberty file: "extra_libraries/dco/dco_FF.lib" - lef file: "extra_libraries/dco/dco.lef" - gds file: "extra_libraries/dco/dco.gds" + nldm liberty file_deepsubst_meta: "local" + nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib" + lef file_deepsubst_meta: "local" + lef file: "extra_libraries/dco/ExampleDCO.lef" + gds file_deepsubst_meta: "local" + gds file: "extra_libraries/dco/ExampleDCO.gds" corner: nmos: "fast" pmos: "fast" diff --git a/vlsi/extra_libraries/dco/ExampleDCO.gds b/vlsi/extra_libraries/dco/ExampleDCO.gds new file mode 100644 index 0000000000000000000000000000000000000000..843e5dffde0888fed5ae34c73a086f90c1f56936 GIT binary patch literal 10240 zcmeI1O>9(E7>2)7+6%&1ia=q2D9WFSPzx$hF=m9)xDY8J@uy%~+Ky-_whkCjBx%GS zRtgdq{76`!*p-T|RFoyMBBCyp1q*-Jm{d2K=y&gV-_G@V^TnQ7xRAT(GkK@ackbLd zbG~zDB$7I5ka@07_Q(zTxJho2#?<5K(o`3f_io!cG*DjF-!~{SV?x9IO}!hw`eo#g zwrMR>epvkNTQaYq>d%#hDZfz~qiDVN+t+QB`bi?ujdgOnM2&UwyDV**Ant09xEYtk zjY^fxojxb^`TA*+>x&+4{;d3`fc#ZHSkHzO}`yJ*#V!_-1IlXCpW<-H8=e(_~cgjq~@kyhEHyXPik)Z zL-5H8d{T4M-v^)E51-WB^k0Qf9)wS7Zu*DelSkl_nw$O!_~c3Wq~@l720l3gpVZv+ z&%!4^hEHm4`sd)2U%)3dH~kCn$&2tw%}xI@eDWLkq~@0IKJoq-Kl8pL^?B2OA3pgZ zd{T4MKMkLJ7e1-E=^uqp9*0kAZu+moClA3VH8=eO@X1%;lbW0UUijn-@JY>0e`!!Yq~@moD17p9_@w5h{}6ogVfduxrvCtZavgk9bJJf5pIi-} z)ZFy%fKM)iPik)ZGvSl7;FFr0{$%)M0Y0g@<;$PmC!K>2#<}T_!Y6<8zL1)m{*Um< zpW&05oBnt3$t&W8hwBLrN;XQ?~5K|eV2WheV5GbzbT)6mt@~1HBZmq^!X>_pC0z} zon+r7H8*|sU6Os5%_3J&GFfHN%mb*bJJ(vCE0gL%}t+umt@~1bNg@V z^|SAi?7O7q=J@QpB>OIz+kaEzv+t7ZyJT+vP5JD*B>OI@xq1HVyCnNAncII;nGO=@oX?As*!HmSMgvu~6Cu76jrpRjL}?AxT~=J@Q} zB>Oh0x#_cSlUKwaq~@l7c{o|Wgyek>sk!N2fKOiZ!wado>7Rp7^1hGM-1N`FCwbpV zYHs>x;FBXbe^PVPKLMXS37^#5^bf-)kH9B2H+_EZKpuooYHs@bFh02-KB>9s55XrZ z@JY>0pWpkC+u@U%n|>F@C%3{UH8=f@@X1Z^NzF~a9X{CspVZv++u)OH;FFr0ehYlE z6+WrC=`Vm!E`m>LZu+y~lXKvcnx}ogf5!T`xa9wN$@wa$o)U?3QlI&!@4tUe{x3Gi z;rso!AK&db@4u^lrc~vq?kVG(yxQ}(@zcHxdtVNCKcRX_PUiYJ|NqzzdHwy#{y)|K z^yRwI`uJT)7+*L4*fai{ynhA%`@s~6n(H)+W;y-+BAVm$aba#lsdzL#j!9u&!`iM` z(xafiG000=_gXFO{c@&G;QQ~M&(sN=k4|@tx}H^ESK#Nv z^=0Y=eqP;UnL2^%hue^;6S$tawV67B>#JLpsS~)~yQP^rf&IrdC!dVe9xk-^yD8a9 z!7GSlD}}Bg@@uwI=n5h~Wh;fOAZ};8_is)1{+l;ruRKxdZ#R;AgzJB{9K#c*oZ1WhTRB@wzN#8kkf2>}|3>GsdY8W*-H5DH$J z2-q7%V^aS>dh6CxgJ^of<<qz~Y zA{Cz^wM<2BYL+<2-&fX>)hCLP+C5LSF<0c?PQDM0gZ%x!`}|+Gjv-&_(Oyfq*`$Z@BCJ10JvPlyk4 z-09y7U^LuKN${92OtsxYIw}E8) z`j1A$2Y-)=4|3e}pAXl6mErnNKX>@-ybc8Qnh>Ayz3Fc*(|@r{U)Hbw_uo=x`|p(L zzh0*QW|@9RnZEQtmAQWqUk}vPx{ErDx(izCuiU~RU6A9>{zKgbQFlRW{WaQ0-33v1L2Lar{KM^X{~+ov z$Z_ZWqwa#JyP&oHqJ7`}JA8hBQMW+{hLeTgV^_i9C!K?t>S~&cY_>v`q=k_*!P3h z{lC$FS7)Ss5a$jc$DQrt+ylHkD*X>y&p(Xzaqa@*+y%6rzZiaIT<#ylxev&3=l$c{ z3GC^Y`v}V z8KX`0!C>}$*O_#ttLNmdz3=*D;&*aer+%Kk_s{mH2iM-C{4CTIr!Cwg*}inwVEVmt zneMaM!IRCt_tP?C$+pWk+ks(Awie%PhgvP!cKc>Kwq(h+$2VJd&XUc0RGdm#vc2ki zZx`w;*Cf zlvkeb`=fbyFnQ&V=Xg|C z#-n*W-w$O?-8$8&yFM`F=Dp7Xs*c0}`d)*qEv z&~JvZhV!lcYI~w2llKh5tJ~;3dCwqK( Date: Mon, 2 Sep 2019 23:27:48 -0700 Subject: [PATCH 09/20] margins for M2 DRCs --- vlsi/example.yml | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/vlsi/example.yml b/vlsi/example.yml index 1c92731e..7e434cb6 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -22,8 +22,9 @@ vlsi.inputs.mmmc_corners: [ ] # Specify clock signals +# ASAP7 bug: period value should actually be in ps vlsi.inputs.clocks: [ - {name: "clock", period: "20ns", uncertainty: "0.1ns"} + {name: "clock", period: "1000ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow @@ -59,17 +60,17 @@ vlsi.inputs.placement_constraints: type: "toplevel" x: 0 y: 0 - width: 500 - height: 500 + width: 300 + height: 300 margins: - left: 0 - right: 0 - top: 0 - bottom: 0 + left: 10 + right: 10 + top: 10 + bottom: 10 - path: "Sha3AccelwBB/dco" type: "hardmacro" - x: 400 - y: 400 + x: 100 + y: 100 width: 32 height: 32 orientation: "r0" From e6027677b3f36707b418c33a78f490f4fb52a5bd Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Mon, 2 Sep 2019 23:35:52 -0700 Subject: [PATCH 10/20] accidentally changed a make variable --- vlsi/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index f4697a9b..52d5b947 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -21,7 +21,7 @@ sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 tech_dir ?= $(if $(filter $(tech_name), asap7 saed32), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json -cMEMS_CACHE ?= $(tech_dir)/sram-cache.json +SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) OBJ_DIR ?= $(vlsi_dir)/build From 971809a546f266b45e85a2188978a9377bf7eb85 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Tue, 3 Sep 2019 09:32:57 -0700 Subject: [PATCH 11/20] update submodules script --- scripts/init-submodules-no-riscv-tools.sh | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 8cd6ced3..627c9285 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -16,14 +16,18 @@ git config submodule.toolchains/esp-tools.update none git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none -# Disable updates to the hammer-cad-plugins repo -git config submodule.vlsi/hammer-cad-plugins.update none +# Disable updates to the hammer tool plugins repos +git config submodule.vlsi/hammer-cadence-plugins.update none +git config submodule.vlsi/hammer-synopsys-plugins.update none +git config submodule.vlsi/hammer-mentor-plugins.update none git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --unset submodule.toolchains/riscv-tools.update git config --unset submodule.toolchains/esp-tools.update git config --global --unset submodule.experimental-blocks.update -git config --unset submodule.vlsi/hammer-cad-plugins.update +git config --unset submodule.vlsi/hammer-cadence-plugins.update +git config --unset submodule.vlsi/hammer-synopsys-plugins.update +git config --unset submodule.vlsi/hammer-mentor-plugins.update # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup From cfba37afc93a66922dcd745e1d3274a84206d6a4 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 19 Sep 2019 22:43:18 -0700 Subject: [PATCH 12/20] bump hammer, remove saed32 --- scripts/init-vlsi.sh | 2 +- vlsi/Makefile | 2 +- vlsi/example.yml | 16 +++++++++------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- vlsi/hammer-mentor-plugins | 2 +- 6 files changed, 14 insertions(+), 12 deletions(-) diff --git a/scripts/init-vlsi.sh b/scripts/init-vlsi.sh index aaf015ca..bbc562d4 100755 --- a/scripts/init-vlsi.sh +++ b/scripts/init-vlsi.sh @@ -10,6 +10,6 @@ git submodule update --init --recursive vlsi/hammer-synopsys-plugins git submodule update --init --recursive vlsi/hammer-mentor-plugins # Initialize HAMMER tech plugin -if [[ $1 != *asap7* ]] && [[ $1 != *saed32* ]]; then +if [[ $1 != *asap7* ]]; then git submodule update --init --recursive vlsi/hammer-$1-plugin fi diff --git a/vlsi/Makefile b/vlsi/Makefile index 52d5b947..d3f3d45f 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -19,7 +19,7 @@ include $(base_dir)/variables.mk ######################################################################################### sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 -tech_dir ?= $(if $(filter $(tech_name), asap7 saed32), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) +tech_dir ?= $(if $(filter $(tech_name), asap7), $(vlsi_dir)/hammer/src/hammer-vlsi/technology/$(tech_name), $(vlsi_dir)/hammer-$(tech_name)-plugin/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json diff --git a/vlsi/example.yml b/vlsi/example.yml index 7e434cb6..bf6d135d 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -1,9 +1,8 @@ # Technology Setup # Technology used is ASAP7 vlsi.core.technology: asap7 -vlsi.core.node: 7 +# Specify dir with ASAP7 tarball technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL" -technology.asap7.install_dir: "SPECIFY EXTRACTED DIR HERE IF NOT USING TARBALL" vlsi.core.max_threads: 12 @@ -22,9 +21,8 @@ vlsi.inputs.mmmc_corners: [ ] # Specify clock signals -# ASAP7 bug: period value should actually be in ps vlsi.inputs.clocks: [ - {name: "clock", period: "1000ns", uncertainty: "0.1ns"} + {name: "clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow @@ -44,12 +42,11 @@ par.generate_power_straps_options: - M7 - M8 - M9 - track_width: 14 - track_width_M3: 7 - track_width_M5: 24 + track_width: 5 track_width_M8: 6 track_width_M9: 6 track_spacing: 0 + track_start: 10 power_utilization: 0.05 power_utilization_M8: 1.0 power_utilization_M9: 1.0 @@ -114,6 +111,11 @@ vlsi.technology.extra_libraries: VDD: "0.77 V" GND: "0 V" +# Because the DCO is a dummy layout, we treat it as a physical-only cell +par.inputs.physical_only_cells_mode: append +par.inputs.physical_only_cells_list: + - ExampleDCO + # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"] diff --git a/vlsi/hammer b/vlsi/hammer index 6c31fbe7..4f06ceef 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 6c31fbe7eb57df98c5815ae4f7ba2ba904f74b0f +Subproject commit 4f06ceef41c0e3d4a9a5f000cf5a120729edc85d diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index a9762c34..06ce365b 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit a9762c344ea247eb2174e720bf8507daf3226933 +Subproject commit 06ce365b36e4b8520372968a5ef2a301afe8d5d6 diff --git a/vlsi/hammer-mentor-plugins b/vlsi/hammer-mentor-plugins index 4daaea36..33ccdccf 160000 --- a/vlsi/hammer-mentor-plugins +++ b/vlsi/hammer-mentor-plugins @@ -1 +1 @@ -Subproject commit 4daaea36f805ba71b55ceb7f5579229eac935045 +Subproject commit 33ccdccf2c04a26cceeeb03a29b9cfad38908328 From 29898bb677581f79a0ff8c94c7539cd4f63f7f76 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Mon, 23 Sep 2019 10:20:42 -0700 Subject: [PATCH 13/20] move documentation to docs/ and new Makefile plumbing --- docs/VLSI/HAMMER.rst | 70 ++++++++++++++++++++++++++++++++++++++++-- vlsi/Makefile | 21 ++++++++++--- vlsi/README.md | 72 -------------------------------------------- vlsi/example.yml | 10 +++--- vlsi/hammer | 2 +- 5 files changed, 88 insertions(+), 87 deletions(-) delete mode 100644 vlsi/README.md diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index c0c77824..c472b167 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -24,8 +24,8 @@ Hooks are modifications to steps or actions that are programmatically defined in Tool Plugins ============ -Hammer supports separately managed plugins for different CAD tool vendors. -The types of tools (in there hammer names) supported currently include: +Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor Graphics plugins with permission from the respective CAD tool vendor. +The types of tools (by HAMMER names) supported currently include: * synthesis * par @@ -48,7 +48,11 @@ This class should be a subclass of ``HammerTool``, which will be a su Technology Plugins ================== -Hammer supports separately managed plugins for different technologies. +Hammer supports separately managed plugins for different technologies. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run. Refer to the ASAP7 plugin and associated documentation for more information. + +In order to configure your technology of choice, you will need to set several configuration variables. +First, you need to choose the technology, for example ``vlsi.core.technology: asap7`` and point to the location with the PDK tarball with ``technology..tarball_dir`` or pre-installed directory with ``technology..install_dir``. +Technology-specific options such as supplies, MMMC corners, metal layers, etc. will need to be matched to the technology in their respective ``vlsi.inputs...`` configurations. Configuration ============= @@ -56,3 +60,63 @@ Configuration To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. You can see the current set of all available Hammer APIs `here `__. + +ASAP7 Tutorial +============== +The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is tested with the Cadence and Mentor tool plugins. + +Initial Setup +------------- +Run ``./scripts/init-vlsi.sh TECH_HAME`` to pull the HAMMER & plugin submodules. Note that for technologies other than ASAP7, the tech submodule must be added in the ``vlsi`` folder first. + +An example of tool environment configuration for BWRC affiliates is given in ``bwrc-env.yml``. Replace paths as necessary for your build environment. + +Pull the HAMMER environment into the shell: + +:: + export HAMMER_HOME=$PWD/hammer + source $HAMMER_HOME/sourceme.sh + +Building the Design +------------------- +To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: + +:: + export MACROCOMPILER_MODE=' --mode synflops' + export CONFIG=Sha3RocketConfig + export VLSI_TOP=Sha3AccelwBB + make buildfile + +Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. + +Running the VLSI Flow +--------------------- +The configuration for this example is contained in ``example.yml`` and the entry script with placeholders for hooks is contained in ``example-vlsi``. Before continuing, ensure you have the `ASAP7 PDK `__ tarball downloaded (but not extracted) and point the ``technology.asap7.tarball_dir`` to the tarball directory. + +To synthesize, type ``make syn``. + +Post-synthesis results are in ``build/syn-rundir``. Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. + +To place and route, type ``make par``. + +If successful, the resulting chip can be opened via ``./build/par-rundir/generated-scripts/open_chip``. + +Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. Compressed timing reports are found in ``build/par-rundir/timingReports``. + +To run DRC & LVS, and view the results: + +:: + make drc + ./build/drc-rundir/generated-scripts/view-drc + make lvs + ./build/lvs-rundir/generated-scripts/view-lvs + +Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__ + +Alternative RTL Flows +--------------------- +The Make-based build system provided supports using HAMMER without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. + +:: + export CUSTOM_VLOG= + export VLSI_TOP= diff --git a/vlsi/Makefile b/vlsi/Makefile index d3f3d45f..3f493c6e 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -28,12 +28,20 @@ OBJ_DIR ?= $(vlsi_dir)/build ENV_YML ?= $(vlsi_dir)/bwrc-env.yml INPUT_CONFS ?= example.yml HAMMER_EXEC ?= ./example-vlsi +VLSI_TOP ?= $(TOP) ######################################################################################### # general rules ######################################################################################### -ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes) +ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v +ifneq ($(CUSTOM_VLOG), ) + VLSI_RTL = $(CUSTOM_VLOG) + VLSI_BB = /dev/null +else + VLSI_RTL = $(ALL_RTL) $(extra_v_includes) + VLSI_BB = $(sim_top_blackboxes) +endif .PHONY: default verilog default: all @@ -74,14 +82,17 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) # synthesis input configuration ######################################################################################### SYN_CONF = $(OBJ_DIR)/inputs.yml -GENERATED_CONFS = $(SYN_CONF) $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) +GENERATED_CONFS = $(SYN_CONF) +ifeq ($(CUSTOM_VLOG), ) + GENERATED_CONFS += $(if $(filter $(tech_name), asap7), , $(SRAM_CONF)) +endif -$(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes) +$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) mkdir -p $(dir $@) echo "synthesis.inputs:" > $@ - echo " top_module: $(TOP)" >> $@ + echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(ALL_RTL) $(extra_v_includes) `cat $(sim_top_blackboxes)`; do \ + for x in $(VLSI_RTL) `cat $(VLSI_BB)`; do \ echo ' - "'$$x'"' >> $@; \ done diff --git a/vlsi/README.md b/vlsi/README.md deleted file mode 100644 index 29fd2bc7..00000000 --- a/vlsi/README.md +++ /dev/null @@ -1,72 +0,0 @@ -# HAMMER VLSI flow -This is the starting point for a vlsi flow from this repository. - -This flow will not work without the necessary CAD and technology plugins for HAMMER. - -If you are a UCB-affiliate, you may be able to acquire access to the tool & tech plugins. - -# Initial Setup Instructions (For all technologies) -Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the technologies `asap7` and `saed32` are already included and will not submodule a tech plugin. -```shell -./scripts/init-vlsi.sh TECH_NAME -``` - -An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment. - -# Example design -## Building the design -In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system: -```shell -export MACROCOMPILER_MODE=' --mode synflops' -export CONFIG=Sha3RocketConfig -make buildfile -``` -Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. - -## Using HAMMER -HAMMER's configuration is driven by a JSON/YAML format. For HAMMER, JSON and YAML files are equivalent - you can use either one since HAMMER will convert them to the same representation for itself. - -We start by pulling the HAMMER environment into the shell: - -```shell -export HAMMER_HOME=$PWD/hammer -source $HAMMER_HOME/sourceme.sh -``` - -The configuration for the example design is contained in `example.yml` and the entry script with hooks is contained in `example-vlsi`. You may go through Hammer's readme to learn about the supported configuration options and how to write hooks. - -In order to install the process, download (and optionally extract) the ASAP7 PDK tarball. Then, edit the key `vlsi.technology.asap7.tarball_dir` if you want Hammer to extract for you or `vlsi.technology.asap7.install_dir` if you have already extracted it. - -To synthesize the just the SHA-3 accelerator with the hard macro we have to change the physical top module (this step is not necessary if you are pushing the entire Rocket-chip through the VLSI flow): -```shell -export TOP=Sha3AccelwBB -rm build/inputs.yml -``` - -Then, to run synthesis: -```shell -make syn -``` - -The outputs are written to a log file with a timestamp and the post-synthesis results are in `build/syn-rundir`. - -Raw QoR data is available at `build/syn-rundir/reports`, and work is planned to extract this information in a more programmatic manner. - -To run place and route: -```shell -make par -``` - -If successful, the resulting chip can be opened via `./build/par-rundir/generated-scripts/open_chip`. - -To run DRC and view violations: -```shell -make drc -./build/drc-rundir/generated-scripts/view-drc -``` - -To run LVS and view violations: -```shell -make lvs -./build/lvs-rundir/generated-scripts/view-lvs -``` diff --git a/vlsi/example.yml b/vlsi/example.yml index bf6d135d..f68bbd12 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -43,8 +43,6 @@ par.generate_power_straps_options: - M8 - M9 track_width: 5 - track_width_M8: 6 - track_width_M9: 6 track_spacing: 0 track_start: 10 power_utilization: 0.05 @@ -60,10 +58,10 @@ vlsi.inputs.placement_constraints: width: 300 height: 300 margins: - left: 10 - right: 10 - top: 10 - bottom: 10 + left: 0 + right: 0 + top: 0 + bottom: 1.08 #must be at least this number - path: "Sha3AccelwBB/dco" type: "hardmacro" x: 100 diff --git a/vlsi/hammer b/vlsi/hammer index 4f06ceef..b837b3fa 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 4f06ceef41c0e3d4a9a5f000cf5a120729edc85d +Subproject commit b837b3fa321cce78998811d3bc842463e58e5745 From 17578ddc93d575cdedce610cce23710db44dab4e Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 25 Sep 2019 15:11:41 -0700 Subject: [PATCH 14/20] [skip ci] docs bump for review --- docs/VLSI/HAMMER.rst | 189 ++++++++++++++---- vlsi/example.yml | 33 ++- vlsi/extra_libraries/dco/ExampleDCO.gds | Bin 10240 -> 9472 bytes vlsi/extra_libraries/dco/ExampleDCO.lef | 115 +++++------ .../dco/ExampleDCO_PVT_0P63V_100C.lib | 10 +- .../dco/ExampleDCO_PVT_0P77V_0C.lib | 10 +- 6 files changed, 233 insertions(+), 124 deletions(-) diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index c472b167..28de651f 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -4,7 +4,9 @@ Core HAMMER `HAMMER `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. -For more information, read the `HAMMER paper `__ and see the `GitHub repository `__. +For more information, read the `HAMMER paper `__ and see the `GitHub repository `__ and associated documentation. + +Hammer implements a VLSI flow using the following high-level constructs: Actions ------- @@ -21,11 +23,18 @@ Hooks Hooks are modifications to steps or actions that are programmatically defined in a Hammer configuration. +Configuration (Hammer IR) +========================= + +To configure a Hammer flow, supply a set yaml or json configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions. + +The current set of all available Hammer APIs is codified `here `__. + Tool Plugins ============ -Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor Graphics plugins with permission from the respective CAD tool vendor. -The types of tools (by HAMMER names) supported currently include: +Hammer supports separately managed plugins for different CAD tool vendors. You may be able to acquire access to the included Cadence, Synopsys, and Mentor plugins repositories with permission from the respective CAD tool vendor. +The types of tools (by Hammer names) supported currently include: * synthesis * par @@ -34,46 +43,103 @@ The types of tools (by HAMMER names) supported currently include: * sram_generator * pcb -In order to configure your tool plugin of choice, you will need to set several configuration variables. -First, you should select which specific tool you want to use by setting ``vlsi.core._tool`` to the name of your tool. -For example ``vlsi.core.par_tool: "innovus"``. -You will also need to point hammer to the folder that contains your tool plugin by setting ``vlsi.core._tool_path``. -This directory should include a folder with the name of the tool as specified previously, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml`` specifying the default values for any tool specific variables. -In addition you can also customize the version of the tools you use by setting ``..version`` to a tool specific string. -Looking at the tools ``defaults.yml`` will inform you if there are other variables you would like to set for your use of this tool. +Several configuration variables are needed to configure your tool plugin of choice. -The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tools Hammer support. -This class should be a subclass of ``HammerTool``, which will be a subclass of ``HammerTool``. +First, select which tool to use for each action by setting ``vlsi.core._tool`` to the name of your tool, e.g. ``vlsi.core.par_tool: "innovus"``. + +Then, point Hammer to the folder that contains your tool plugin by setting ``vlsi.core._tool_path``. +This directory should include a folder with the name of the tool, which itself includes a python file ``__init__.py`` and a yaml file ``defaults.yml``. Customize the version of the tool by setting ``..version`` to a tool specific string. + +The ``__init__.py`` file should contain a variable, ``tool``, that points to the class implementing this tool. +This class should be a subclass of ``HammerTool``, which will be a subclass of ``HammerTool``. The class should implement methods for all the tool's steps. + +The ``defaults.yml`` file contains tool-specific configuration variables. The defaults may be overridden as necessary. Technology Plugins ================== -Hammer supports separately managed plugins for different technologies. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run. Refer to the ASAP7 plugin and associated documentation for more information. +Hammer supports separately managed technology plugins to satisfy NDAs. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run. -In order to configure your technology of choice, you will need to set several configuration variables. -First, you need to choose the technology, for example ``vlsi.core.technology: asap7`` and point to the location with the PDK tarball with ``technology..tarball_dir`` or pre-installed directory with ``technology..install_dir``. -Technology-specific options such as supplies, MMMC corners, metal layers, etc. will need to be matched to the technology in their respective ``vlsi.inputs...`` configurations. +The `ASAP7 plugin `__ is a good starting point for setting up a technology plugin. Refer to Hammer's documentation for the schema and setup instructions. -Configuration -============= +Several configuration variables are needed to configure your technology of choice. -To configure a hammer flow the user needs to supply a yaml or json configuration file the chooses the tool and technology plugins and versions as well as any design specific configuration APIs. +First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology..tarball_dir`` or pre-installed directory with ``technology..install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``. -You can see the current set of all available Hammer APIs `here `__. +Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user. ASAP7 Tutorial ============== -The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is tested with the Cadence and Mentor tool plugins. +The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins. + +Project Structure +----------------- + +This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: + +* Makefile + + * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. + +* build + + * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. + * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. + +* bwrc-env.yml + + * An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment. + +* example-vlsi + + * Entry point to Hammer. Contains example placeholders for hooks. + +* example.v + + * Verilog wrapper around the accelerator and dummy hard macro. + +* example.yml + + * Hammer IR for this tutorial. + +* extra_libraries + + * Contains collateral for the dummy hard macro. + +* generated-src + + * All of the elaborated Chisel and FIRRTL. + +* hammer, hammer--plugins, hammer--plugin + + * Core, tool, tech repositories. + +Prerequisites +------------- + +* Python 3.4+ +* numpy and gdspy packages +* Genus, Innovus, and Calibre licenses +* For ASAP7 specifically: + + * Download the `ASAP7 PDK `__ tarball and do not extract it + * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision Initial Setup ------------- -Run ``./scripts/init-vlsi.sh TECH_HAME`` to pull the HAMMER & plugin submodules. Note that for technologies other than ASAP7, the tech submodule must be added in the ``vlsi`` folder first. +In the Chipyard root, run: -An example of tool environment configuration for BWRC affiliates is given in ``bwrc-env.yml``. Replace paths as necessary for your build environment. +.. code-block:: shell -Pull the HAMMER environment into the shell: + ``./scripts/init-vlsi.sh asap7`` + +to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. -:: +Pull the Hammer environment into the shell: + +.. code-block:: shell + + cd vlsi export HAMMER_HOME=$PWD/hammer source $HAMMER_HOME/sourceme.sh @@ -81,42 +147,87 @@ Building the Design ------------------- To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: -:: - export MACROCOMPILER_MODE=' --mode synflops' +.. code-block:: shell + + export MACROCOMPILER_MODE='--mode synflops' export CONFIG=Sha3RocketConfig export VLSI_TOP=Sha3AccelwBB make buildfile -Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead. +Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead. + +For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed. Running the VLSI Flow --------------------- -The configuration for this example is contained in ``example.yml`` and the entry script with placeholders for hooks is contained in ``example-vlsi``. Before continuing, ensure you have the `ASAP7 PDK `__ tarball downloaded (but not extracted) and point the ``technology.asap7.tarball_dir`` to the tarball directory. -To synthesize, type ``make syn``. +example-vlsi +^^^^^^^^^^^^ +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods. -Post-synthesis results are in ``build/syn-rundir``. Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. +example.yml +^^^^^^^^^^^ +This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. -To place and route, type ``make par``. +First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK. -If successful, the resulting chip can be opened via ``./build/par-rundir/generated-scripts/open_chip``. +Synthesis +^^^^^^^^^ +.. code-block:: shell -Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. Compressed timing reports are found in ``build/par-rundir/timingReports``. + ``make syn`` -To run DRC & LVS, and view the results: +Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. + +Place-and-Route +^^^^^^^^^^^^^^^ +.. code-block:: shell + + ``make par`` + +After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``. + +Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. + +Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. + +DRC & LVS +^^^^^^^^^ +To run DRC & LVS, and view the results in Calibre: + +.. code-block:: shell -:: make drc ./build/drc-rundir/generated-scripts/view-drc make lvs ./build/lvs-rundir/generated-scripts/view-lvs -Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__ +Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. + +Advanced Usage +============== Alternative RTL Flows --------------------- -The Make-based build system provided supports using HAMMER without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. +The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. + +.. code-block:: shell -:: export CUSTOM_VLOG= export VLSI_TOP= + +Manual Step Execution & Dependency Tracking +------------------------------------------- +It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed. + +Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``. + +Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings: + +.. code-block:: shell + + make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' + +Simulation +---------- +With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. diff --git a/vlsi/example.yml b/vlsi/example.yml index f68bbd12..e641f8c2 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -2,24 +2,16 @@ # Technology used is ASAP7 vlsi.core.technology: asap7 # Specify dir with ASAP7 tarball -technology.asap7.tarball_dir: "SPECIFY DIR WITH ASAP7 TARBALL" +technology.asap7.tarball_dir: "" vlsi.core.max_threads: 12 # General Hammer Inputs -vlsi.inputs.supplies.VDD: "0.7 V" - # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info vlsi.inputs.power_spec_mode: "auto" vlsi.inputs.power_spec_type: "cpf" -# Specify the setup and hold corners for ASAP7 -vlsi.inputs.mmmc_corners: [ - {name: "PVT_0P63V_100C", type: "setup", voltage: "0.63 V", temp: "100 C"}, - {name: "PVT_0P77V_0C", type: "hold", voltage: "0.77 V", temp: "0 C"} -] - # Specify clock signals vlsi.inputs.clocks: [ {name: "clock", period: "1ns", uncertainty: "0.1ns"} @@ -50,9 +42,10 @@ par.generate_power_straps_options: power_utilization_M9: 1.0 # Placement Constraints +# For ASAP7, all numbers must be 4x larger than final GDS vlsi.inputs.placement_constraints: - path: "Sha3AccelwBB" - type: "toplevel" + type: toplevel x: 0 y: 0 width: 300 @@ -63,12 +56,13 @@ vlsi.inputs.placement_constraints: top: 0 bottom: 1.08 #must be at least this number - path: "Sha3AccelwBB/dco" - type: "hardmacro" - x: 100 - y: 100 - width: 32 - height: 32 - orientation: "r0" + type: hardmacro + x: 108 + y: 108 + width: 128 + height: 128 + orientation: r0 + top_layer: M9 # Pin placement constraints vlsi.inputs.pin_mode: generated @@ -116,7 +110,8 @@ par.inputs.physical_only_cells_list: # SRAM Compiler compiler options vlsi.core.sram_generator_tool: "sram_compiler" -vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"] +# You should specify a location for the SRAM generator in the tech plugin +vlsi.core.sram_generator_tool_path: [] vlsi.core.sram_generator_tool_path_meta: "append" # Tool options. Replace with your tool plugin of choice. @@ -124,12 +119,12 @@ vlsi.core.sram_generator_tool_path_meta: "append" vlsi.core.synthesis_tool: "genus" vlsi.core.synthesis_tool_path: ["hammer-cadence-plugins/synthesis"] vlsi.core.synthesis_tool_path_meta: "append" -synthesis.genus.version: "181" +synthesis.genus.version: "1813" # Innovus options vlsi.core.par_tool: "innovus" vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] vlsi.core.par_tool_path_meta: "append" -par.innovus.version: "181" +par.innovus.version: "191" par.innovus.design_flow_effort: "standard" par.inputs.gds_merge: true # Calibre options diff --git a/vlsi/extra_libraries/dco/ExampleDCO.gds b/vlsi/extra_libraries/dco/ExampleDCO.gds index 843e5dffde0888fed5ae34c73a086f90c1f56936..e60564bc3734d73f354e96ff65b354214ddee5f4 100644 GIT binary patch delta 813 zcmZ{i&1(};6va=b=}UuYn3P&F$)ss%Kq-|<{pd$pX{HGji})Z?f&pWjj3ADt*oD$A znys!z@6wI95!}^<=u!|7bTRk`xbYw8!j&tN`(6eOxOi~5_jk`b_whQibM*)UhEanZ zF=9UvM;a+CA@{e2X$bf6&iy^lJ=bcsf$^c?E2SrkTc2N_ESKNUzkG4?2JGSg&nJbb zsQL27bwo!1F>2r}MAE?V(Y>^o>HvpBbdp|<;V=PIT6Er8O~tpJ!HC#Z7WDn=DTS4%mnNpo2RjGJ_z8v)4l3NUq40t-ddPu#3EV#ixTA^+}w7K54mbQnH|`Ym#bOuK4t-u#rW5 Wz55dr7_r25wF*R2-4pAcDE9(E7>2)7+6%&1ia=q2D9WFSPzx$hF=m9)xDY8J@uy%~+Ky-_whkCjBx%GS zRtgdq{76`!*p-T|RFoyMBBCyp1q*-Jm{d2K=y&gV-_G@V^TnQ7xRAT(GkK@ackbLd zbG~zDB$7I5ka@07_Q(zTxJho2#?<5K(o`3f_io!cG*DjF-!~{SV?x9IO}!hw`eo#g zwrMR>epvkNTQaYq>d%#hDZfz~qiDVN+t+QB`bi?ujdgOnM2&UwyDV**Ant09xEYtk zjY^fxojxb^`TA*+>x&+4{;d3`fc#ZHSkHzO}`yJ*#V!_-1IlXCpW<-H8=e(_~cgjq~@kyhEHyXPik)Z zL-5H8d{T4M-v^)E51-WB^k0Qf9)wS7Zu*DelSkl_nw$O!_~c3Wq~@l720l3gpVZv+ z&%!4^hEHm4`sd)2U%)3dH~kCn$&2tw%}xI@eDWLkq~@0IKJoq-Kl8pL^?B2OA3pgZ zd{T4MKMkLJ7e1-E=^uqp9*0kAZu+moClA3VH8=eO@X1%;lbW0UUijn-@JY>0e`!!Yq~@moD17p9_@w5h{}6ogVfduxrvCtZavgk9bJJf5pIi-} z)ZFy%fKM)iPik)ZGvSl7;FFr0{$%)M0Y0g@<;$PmC!K>2#<}T_!Y6<8zL1)m{*Um< zpW&05oBnt3$t&W8hwBLrN;XQ?~5K|eV2WheV5GbzbT)6mt@~1HBZmq^!X>_pC0z} zon+r7H8*|sU6Os5%_3J&GFfHN%mb*bJJ(vCE0gL%}t+umt@~1bNg@V z^|SAi?7O7q=J@QpB>OIz+kaEzv+t7ZyJT+vP5JD*B>OI@xq1HVyCnNAncII;nGO=@oX?As*!HmSMgvu~6Cu76jrpRjL}?AxT~=J@Q} zB>Oh0x#_cSlUKwaq~@l7c{o|Wgyek>sk!N2fKOiZ!wado>7Rp7^1hGM-1N`FCwbpV zYHs>x;FBXbe^PVPKLMXS37^#5^bf-)kH9B2H+_EZKpuooYHs@bFh02-KB>9s55XrZ z@JY>0pWpkC+u@U%n|>F@C%3{UH8=f@@X1Z^NzF~a9X{CspVZv++u)OH;FFr0ehYlE z6+WrC=`Vm!E`m>LZu+y~lXKvcnx}ogf5!T`xa9wN$@wa$o)U?3QlI&!@4tUe{x3Gi z;rso!AK&db@4u^lrc~vq?kVG(yxQ}(@zcHxdtVNCKcRX_PUiYJ|NqzzdHwy#{y)|K z^yRwI`uJT)7+*L4*fai{ynhA%`@s~6n(H)+W;y-+BAVm$aba#lsdzL#j!9u&!`iM` z(xafiG000=_gXFO{c@&G;QQ~M&(sN=k4|@tx}H^ESK#Nv z^=0Y=eqP;UnL2^%hue^;6S$tawV67B>#JLpsS~)~yQP^rf&IrdC!dVe9xk-^yD8a9 z!7GSlD}}Bg@@uwI=n5h~Wh;fOAZ};8_is)1{+l;ruRKxdZ#R;AgzJB Date: Thu, 26 Sep 2019 13:23:55 -0700 Subject: [PATCH 15/20] split Hammer doc into multiple files --- docs/VLSI/Advanced-Usage.rst | 29 ++++++ docs/VLSI/HAMMER.rst | 166 +---------------------------------- docs/VLSI/Tutorial.rst | 137 +++++++++++++++++++++++++++++ docs/VLSI/index.rst | 2 + 4 files changed, 170 insertions(+), 164 deletions(-) create mode 100644 docs/VLSI/Advanced-Usage.rst create mode 100644 docs/VLSI/Tutorial.rst diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst new file mode 100644 index 00000000..163339d4 --- /dev/null +++ b/docs/VLSI/Advanced-Usage.rst @@ -0,0 +1,29 @@ +.. _advanced-usage: + +Advanced Usage +============== + +Alternative RTL Flows +--------------------- +The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. + +.. code-block:: shell + + export CUSTOM_VLOG= + export VLSI_TOP= + +Manual Step Execution & Dependency Tracking +------------------------------------------- +It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed. + +Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``. + +Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings: + +.. code-block:: shell + + make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' + +Simulation +---------- +With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index 28de651f..805a4d48 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -1,3 +1,5 @@ +.. _hammer: + Core HAMMER ================================ @@ -67,167 +69,3 @@ Several configuration variables are needed to configure your technology of choic First, choose the technology, e.g. ``vlsi.core.technology: asap7``, then point to the location with the PDK tarball with ``technology..tarball_dir`` or pre-installed directory with ``technology..install_dir`` and (if applicable) the plugin repository with ``vlsi.core.technology_path``. Technology-specific options such as supplies, MMMC corners, etc. are defined in their respective ``vlsi.inputs...`` configurations. Options for the most common use case are already defined in the technology's ``defaults.yml`` and can be overridden by the user. - -ASAP7 Tutorial -============== -The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins. - -Project Structure ------------------ - -This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: - -* Makefile - - * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. - -* build - - * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. - * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. - -* bwrc-env.yml - - * An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment. - -* example-vlsi - - * Entry point to Hammer. Contains example placeholders for hooks. - -* example.v - - * Verilog wrapper around the accelerator and dummy hard macro. - -* example.yml - - * Hammer IR for this tutorial. - -* extra_libraries - - * Contains collateral for the dummy hard macro. - -* generated-src - - * All of the elaborated Chisel and FIRRTL. - -* hammer, hammer--plugins, hammer--plugin - - * Core, tool, tech repositories. - -Prerequisites -------------- - -* Python 3.4+ -* numpy and gdspy packages -* Genus, Innovus, and Calibre licenses -* For ASAP7 specifically: - - * Download the `ASAP7 PDK `__ tarball and do not extract it - * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision - -Initial Setup -------------- -In the Chipyard root, run: - -.. code-block:: shell - - ``./scripts/init-vlsi.sh asap7`` - -to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. - -Pull the Hammer environment into the shell: - -.. code-block:: shell - - cd vlsi - export HAMMER_HOME=$PWD/hammer - source $HAMMER_HOME/sourceme.sh - -Building the Design -------------------- -To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: - -.. code-block:: shell - - export MACROCOMPILER_MODE='--mode synflops' - export CONFIG=Sha3RocketConfig - export VLSI_TOP=Sha3AccelwBB - make buildfile - -Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead. - -For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed. - -Running the VLSI Flow ---------------------- - -example-vlsi -^^^^^^^^^^^^ -This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods. - -example.yml -^^^^^^^^^^^ -This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. - -First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK. - -Synthesis -^^^^^^^^^ -.. code-block:: shell - - ``make syn`` - -Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. - -Place-and-Route -^^^^^^^^^^^^^^^ -.. code-block:: shell - - ``make par`` - -After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``. - -Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. - -Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. - -DRC & LVS -^^^^^^^^^ -To run DRC & LVS, and view the results in Calibre: - -.. code-block:: shell - - make drc - ./build/drc-rundir/generated-scripts/view-drc - make lvs - ./build/lvs-rundir/generated-scripts/view-lvs - -Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. - -Advanced Usage -============== - -Alternative RTL Flows ---------------------- -The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. - -.. code-block:: shell - - export CUSTOM_VLOG= - export VLSI_TOP= - -Manual Step Execution & Dependency Tracking -------------------------------------------- -It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed. - -Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``. - -Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings: - -.. code-block:: shell - - make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' - -Simulation ----------- -With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst new file mode 100644 index 00000000..9f4262d2 --- /dev/null +++ b/docs/VLSI/Tutorial.rst @@ -0,0 +1,137 @@ +.. _tutorial: + +ASAP7 Tutorial +============== +The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins. + +Project Structure +----------------- + +This example gives a suggested file structure and build system. The ``vlsi/`` folder will eventually contain the following files and folders: + +* Makefile + + * Integration of Hammer's build system into Chipyard and abstracts away some Hammer commands. + +* build + + * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. + * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. + +* bwrc-env.yml + + * An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment. + +* example-vlsi + + * Entry point to Hammer. Contains example placeholders for hooks. + +* example.v + + * Verilog wrapper around the accelerator and dummy hard macro. + +* example.yml + + * Hammer IR for this tutorial. + +* extra_libraries + + * Contains collateral for the dummy hard macro. + +* generated-src + + * All of the elaborated Chisel and FIRRTL. + +* hammer, hammer--plugins, hammer--plugin + + * Core, tool, tech repositories. + +Prerequisites +------------- + +* Python 3.4+ +* numpy and gdspy packages +* Genus, Innovus, and Calibre licenses +* For ASAP7 specifically: + + * Download the `ASAP7 PDK `__ tarball and do not extract it + * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision + +Initial Setup +------------- +In the Chipyard root, run: + +.. code-block:: shell + + ``./scripts/init-vlsi.sh asap7`` + +to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. + +Pull the Hammer environment into the shell: + +.. code-block:: shell + + cd vlsi + export HAMMER_HOME=$PWD/hammer + source $HAMMER_HOME/sourceme.sh + +Building the Design +------------------- +To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: + +.. code-block:: shell + + export MACROCOMPILER_MODE='--mode synflops' + export CONFIG=Sha3RocketConfig + export VLSI_TOP=Sha3AccelwBB + make buildfile + +Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead. + +For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed. + +Running the VLSI Flow +--------------------- + +example-vlsi +^^^^^^^^^^^^ +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods. + +example.yml +^^^^^^^^^^^ +This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. + +First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK. + +Synthesis +^^^^^^^^^ +.. code-block:: shell + + ``make syn`` + +Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. + +Place-and-Route +^^^^^^^^^^^^^^^ +.. code-block:: shell + + ``make par`` + +After completion, the final database can be opened in an interactive Innovus session via ``./build/par-rundir/generated-scripts/open_chip``. + +Intermediate database are written in ``build/par-rundir`` between each step of the ``par`` action, and can be restored in an interactive Innovus session as desired for debugging purposes. + +Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. + +DRC & LVS +^^^^^^^^^ +To run DRC & LVS, and view the results in Calibre: + +.. code-block:: shell + + make drc + ./build/drc-rundir/generated-scripts/view-drc + make lvs + ./build/lvs-rundir/generated-scripts/view-lvs + +Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 44303769..8bc98b60 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -10,3 +10,5 @@ In particular, we aim to support the HAMMER physical design generator flow. Building-A-Chip HAMMER + Tutorial + Advanced-Usage From e7e229a416053c13cffdb48501fdb76fadcdb102 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 26 Sep 2019 15:40:22 -0700 Subject: [PATCH 16/20] [skip ci] address comments, remove bwrc env vars, bump hammer --- docs/VLSI/Advanced-Usage.rst | 27 +++++++++++++++++++++++- docs/VLSI/HAMMER.rst | 2 +- docs/VLSI/Tutorial.rst | 14 +++++++----- vlsi/Makefile | 2 +- vlsi/bwrc-env.yml | 7 ------ vlsi/env.yml | 13 ++++++++++++ vlsi/extra_libraries/dco/ExampleDCO.gds | Bin 9472 -> 9536 bytes vlsi/hammer | 2 +- 8 files changed, 51 insertions(+), 16 deletions(-) delete mode 100644 vlsi/bwrc-env.yml create mode 100644 vlsi/env.yml diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index 163339d4..ba038f28 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -12,11 +12,36 @@ The Make-based build system provided supports using Hammer without using RTL gen export CUSTOM_VLOG= export VLSI_TOP= +``CUSTOM_VLOG`` breaks the dependency on the rest of the + +Under the Hood +-------------- +To uncover what is happening under the hood, here are the commands that are executed: + +For ``make syn``: + +.. code-block:: shell + + ./example-vlsi -e /path/to/env.yml -p /path/to/example.yml -p /path/to/inputs.yml --obj_dir /path/to/build syn + +``example-vlsi`` is the entry script as explained before, ``-e`` provides the environment yml, ``-p`` points to configuration yml/jsons, ``--obj_dir`` speficies the destination directory, and ``syn`` is the action. + +For ``make par``: + +.. code-block:: shell + + ./example-vlsi -e /path/to/env.yml -p /path/to/syn-output-full.json -o /path/to/par-input.json --obj_dir /path/to/build syn-to-par + ./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json --obj_dir /path/to/build par + +A ``syn-to-par`` action translates the synthesis output configuration into an input configuration given by ``-o``. Then, this is passed to the ``par`` action. + +For more information about all the options that can be passed to the Hammer command-line driver, please see the Hammer documentation. + Manual Step Execution & Dependency Tracking ------------------------------------------- It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--to_step``, ``--from_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed. -Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par``. +Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command. Say you need to update some power straps settings in ``example.yml`` and want to try out the new settings: diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/HAMMER.rst index 805a4d48..3a7def4b 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/HAMMER.rst @@ -62,7 +62,7 @@ Technology Plugins Hammer supports separately managed technology plugins to satisfy NDAs. You may be able to acquire access to certain pre-built technology plugins with permission from the technology vendor. Or, to build your own tech plugin, you need at least a ``.tech.json`` and ``defaults.yml``. An ``__init__.py`` is optional if there are any technology-specific methods or hooks to run. -The `ASAP7 plugin `__ is a good starting point for setting up a technology plugin. Refer to Hammer's documentation for the schema and setup instructions. +The `ASAP7 plugin `__ is a good starting point for setting up a technology plugin because it is an open-source example that is not suitable for taping out a chip. Refer to Hammer's documentation for the schema and detailed setup instructions. Several configuration variables are needed to configure your technology of choice. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 9f4262d2..c16d85d6 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -18,9 +18,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * Hammer output directory. Can be changed with the ``OBJ_DIR`` variable. * Will contain subdirectories such as ``syn-rundir`` and ``par-rundir`` and the ``inputs.yml`` denoting the top module and input Verilog files. -* bwrc-env.yml +* env.yml - * An example of tool environment configuration for BWRC affiliates. Replace as necessary for your environment. + * A template file for tool environment configuration. Fill in the install and license server paths for your environment. * example-vlsi @@ -86,9 +86,13 @@ To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all export VLSI_TOP=Sha3AccelwBB make buildfile -Note that because the ASAP7 process does not yet have a memory compiler, flip-flop arrays are used instead. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. -For the curious, Hammer generates a set of Make targets in ``build/hammer.d``. ``make buildfile`` needs to be re-run if Make variables are changed. +The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. + +The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. + +For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. Running the VLSI Flow --------------------- @@ -101,7 +105,7 @@ example.yml ^^^^^^^^^^^ This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. -First, set ``technology.asap7.tarball_dir`` to where you downloaded the ASAP7 PDK. +First, set ``technology.asap7.tarball_dir`` to the absolute path of where the downloaded the ASAP7 PDK tarball lives. Synthesis ^^^^^^^^^ diff --git a/vlsi/Makefile b/vlsi/Makefile index 3f493c6e..cc61b957 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -25,7 +25,7 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) OBJ_DIR ?= $(vlsi_dir)/build -ENV_YML ?= $(vlsi_dir)/bwrc-env.yml +ENV_YML ?= $(vlsi_dir)/env.yml INPUT_CONFS ?= example.yml HAMMER_EXEC ?= ./example-vlsi VLSI_TOP ?= $(TOP) diff --git a/vlsi/bwrc-env.yml b/vlsi/bwrc-env.yml deleted file mode 100644 index f68eab24..00000000 --- a/vlsi/bwrc-env.yml +++ /dev/null @@ -1,7 +0,0 @@ -mentor.mentor_home: "/tools/mentor" -mentor.MGLS_LICENSE_FILE: "1717@bwrcflex-1.eecs.berkeley.edu:1717@bwrcflex-2.eecs.berkeley.edu" -cadence.cadence_home: "/tools/cadence" -cadence.CDS_LIC_FILE: "5280@bwrcflex-1.eecs.berkeley.edu:5280@bwrcflex-2.eecs.berkeley.edu" -synopsys.synopsys_home: "/tools/synopsys" -synopsys.SNPSLMD_LICENSE_FILE: "1701@bwrcflex-1.eecs.berkeley.edu:1701@bwrcflex-2.eecs.berkeley.edu" -synopsys.MGLS_LICENSE_FILE: "1717@bwrcflex-1.eecs.berkeley.edu:1717@bwrcflex-2.eecs.berkeley.edu" diff --git a/vlsi/env.yml b/vlsi/env.yml new file mode 100644 index 00000000..c4e63038 --- /dev/null +++ b/vlsi/env.yml @@ -0,0 +1,13 @@ +# Base path to where Mentor tools are installed +mentor.mentor_home: "" +# Mentor license server/file +mentor.MGLS_LICENSE_FILE: "" +# Base path to where Cadence tools are installed +cadence.cadence_home: "" +# Cadence license server/file +cadence.CDS_LIC_FILE: "" +# Base path to where Synopsys tools are installed +synopsys.synopsys_home: "" +# Synopsys license server/files +synopsys.SNPSLMD_LICENSE_FILE: "" +synopsys.MGLS_LICENSE_FILE: "" diff --git a/vlsi/extra_libraries/dco/ExampleDCO.gds b/vlsi/extra_libraries/dco/ExampleDCO.gds index e60564bc3734d73f354e96ff65b354214ddee5f4..9990b41cb9422c5e429e78f59005ab44cd04acc0 100644 GIT binary patch literal 9536 zcmc(kUx-vy9LLYxx%bYR( zBtA%*ipF9uA_Y<}{Xq#?WFJI&SbPXE0x1v?kqyL`r23wFe&4&7+w{Xd^U#Hz&z&W&G^Hb>CR|@J zrAaf*ck$fjB-+EdXm8*fY~cYs^x}B(piPmJ$Ti;#;9&SEcUT)6iFVaLjAN}&9R%C`#8_arfJCnP_i-@#e?UG+bQ6%sHNUvX`6-t;zeu88 z_1B3{ZV;bDuKDq8=ck-Tj%;*-cVKl;u2DQ`JHBGIn;--}QFC_af?^$&?pekwkRT=ln#PY#JsB3J!x z@yQ@i%*utCy{G@c-{FaZ#X|B(XRSmi%)(lK8alQH;PYg5uZe^`b)(pmx)gz z*ZksN&L_iAe4))%|El=pHRl&eFKyZ;Sg-0S+{i8V8`sB$(H!+D^^|y;p*2E`~ ztNtqS$%^L`ze*YrO&-VN&Id79_SI>V)e3J7v ziCp!!icb#VIkt#IuKL|L*j_)`ljtTQk*j_zK3Nu@M6UViynWr(N$2ewu8wV2eaz4H z`a_cQHi=yI4~S15l=G6vRiE=d$$6hduKG*m{3Pdn61nDc-X|Y!{-5r@#jEc8DX+QL zuh0J(|E&1rIq^y4>h$W^~fd~%`qBy!C!+;x7+ zd(JPAXjlD9;**!fCy}fE3GvA>@k!*Wzf*j2SbP$>>i3FI_K8m-SN(SJ$@$`w$TdIx z-SDQXW9~RVC34ljARaj`K8alQ4~tJ86Q4w``UB#VJH#iEXMMMRmhtbD9Q#Fvy`#q1 zoW$sTPEj;u4ch(Pz&I{&b2rtRWhQ7Q0 z|J(O@{X@z6e|rA1x4$&mW|7eTFTw3Q+Q;Pnm9eJA{~uass(@6*p!KOO`1nK{#cihC8Skl8tHb^5(GUBIa23{%&Q?r&XFO8>xPMQz)<3X$`AhG4Tn#FjPb&8H z41KV7M|EVzcf?+c`L1H-;f~aYs{JF?_dlv_+gl&myv+A{?lh{l+_PHYsYcbheXDJ1 zRP6=dYDXGXd(pSruGeha8tP9nbkEswba}%o@&j?vHx%m3&8#sF1JZJA#B)@|Ao?knpp7C7%(b^rT(;PbF*r M_3LG=TmnP$4-bSh761SM literal 9472 zcmc(kPi$0G6voe+whs!mOtqG_Rz(pp%AZn&wxXs$+nAs-qz17?`)|fd7?`GDBsL^X zhz2*NgcU+a7sQ5@k+?8MA}d2!H4?Xm#BPim7mXVidft2A*Li(DPwbtAZ^3W!4Zm~W z+_`hlovHYe$sCn7FSF(ssg-7FkS=*N{#ddZzi@W+LR2*Z~B|zlUv}Enw$O(_+&eL zQghSqhEMK=Pik)Zz3|C?_@w5he+WK#7(S`F=?}sukHIH3H~j*9asoc7x#>^BC#T?( znw$PKeDWN8QghS)1U`8IKB>9sUxZIyf=_C0`d8tT*WiGpZpp= zsk!Ojf=_-ApVZv+@4zST!Y4I1{d@4qpWu_4TfX;gd{T4M-v^&O0H4&{^!LCgyWo?WoBng~ z$?fn-%}xJd_~b_Tq~@l-4nA22pVZv)<*&#mJr6z@}`qBJLh2I|{U-Vk;yX?d4yJTwrjrr`mB>OI@d3^oG?>`*>`b@OmN%mb* zbJJ(vCE0h$)cza0fA(FHeV5eS9G`ucWZxw>;FEWw;f2)P^l!l@`Mr0g9TUV=|*Zu9sPr@gs;FFr0 zK7aQiC*YHsoBkliCy&7=H8=f3@X5pQNzF~a7e3h!pVZv+yWx|2;gg!1{tozLJA6`e z)87oA+ybA}-1M8_ldbSc&EtM_e#ZX!bWil3x85#u!<EeHR88=`nc|qnx2-+!S%V+wbkq&3?#kk z^luEJ=LeatlC>@Vk>1`_)(ZS-9k?$q>stKrVrl$@LxtKOgO?_CE&l0Zp)ff-=1?P; zmRED~V2eLh`f&Jkp*TD?v}^Y}j+Oje@Otvc&%9rlTHWjhGZNfOZC09eMoRg@@Kj;q zgW~9!($rA9>;0@>NU65VwOajbO0^ExY7M!RYR|h?YfPKB7hJ0~rOli3s%S}@w>_@+ z)|NJJovzg$&q_AF_I0VPYFFU8ePUr{9bIHjb)K4CSx1+bQ=P53m34GsIn{YKF+aMb zoa$^#%#SW6r#d?m^P|hisZK{?eslpj)!ChxpDxEbor(GBcC2%1A=t~uOGWPG&O1sm zo2cZx(;W}{OYEMUci{JC6ZhoY8OFo;F5i>ue2<3jf4Pq9`~Pk(_`H_uxUR>c*_Cx% zKOaXE^W*w?J(8Fo*ZpH4F+Z;RSuQa@uKVljiTQEe?++&C$F=|Tg`bSr8P2))?_Wrq r2Ay}1o@}C$^A7TIE>X#O2YE3$Pfk0?P)~S%56=Dr12`+MQC7>}JmjyZ diff --git a/vlsi/hammer b/vlsi/hammer index b837b3fa..946c4f41 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit b837b3fa321cce78998811d3bc842463e58e5745 +Subproject commit 946c4f416709663651580f7c4c1be2e2652dff6f From 8fffc1c67069081e1a9da29727cee098df552c70 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 26 Sep 2019 22:47:17 -0700 Subject: [PATCH 17/20] [skip ci] make dco libs in example folder for consistency --- vlsi/example.yml | 12 ++++++------ .../extra_libraries/{dco => example}/ExampleDCO.gds | Bin .../extra_libraries/{dco => example}/ExampleDCO.lef | 0 .../{dco => example}/ExampleDCO_PVT_0P63V_100C.lib | 0 .../{dco => example}/ExampleDCO_PVT_0P77V_0C.lib | 0 5 files changed, 6 insertions(+), 6 deletions(-) rename vlsi/extra_libraries/{dco => example}/ExampleDCO.gds (100%) rename vlsi/extra_libraries/{dco => example}/ExampleDCO.lef (100%) rename vlsi/extra_libraries/{dco => example}/ExampleDCO_PVT_0P63V_100C.lib (100%) rename vlsi/extra_libraries/{dco => example}/ExampleDCO_PVT_0P77V_0C.lib (100%) diff --git a/vlsi/example.yml b/vlsi/example.yml index e641f8c2..d8ca594b 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -76,11 +76,11 @@ vlsi.technology.extra_libraries_meta: ["append", "deepsubst"] vlsi.technology.extra_libraries: - library: nldm liberty file_deepsubst_meta: "local" - nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib" + nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib" lef file_deepsubst_meta: "local" - lef file: "extra_libraries/dco/ExampleDCO.lef" + lef file: "extra_libraries/example/ExampleDCO.lef" gds file_deepsubst_meta: "local" - gds file: "extra_libraries/dco/ExampleDCO.gds" + gds file: "extra_libraries/example/ExampleDCO.gds" corner: nmos: "slow" pmos: "slow" @@ -90,11 +90,11 @@ vlsi.technology.extra_libraries: GND: "0 V" - library: nldm liberty file_deepsubst_meta: "local" - nldm liberty file: "extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib" + nldm liberty file: "extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib" lef file_deepsubst_meta: "local" - lef file: "extra_libraries/dco/ExampleDCO.lef" + lef file: "extra_libraries/example/ExampleDCO.lef" gds file_deepsubst_meta: "local" - gds file: "extra_libraries/dco/ExampleDCO.gds" + gds file: "extra_libraries/example/ExampleDCO.gds" corner: nmos: "fast" pmos: "fast" diff --git a/vlsi/extra_libraries/dco/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds similarity index 100% rename from vlsi/extra_libraries/dco/ExampleDCO.gds rename to vlsi/extra_libraries/example/ExampleDCO.gds diff --git a/vlsi/extra_libraries/dco/ExampleDCO.lef b/vlsi/extra_libraries/example/ExampleDCO.lef similarity index 100% rename from vlsi/extra_libraries/dco/ExampleDCO.lef rename to vlsi/extra_libraries/example/ExampleDCO.lef diff --git a/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib b/vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib similarity index 100% rename from vlsi/extra_libraries/dco/ExampleDCO_PVT_0P63V_100C.lib rename to vlsi/extra_libraries/example/ExampleDCO_PVT_0P63V_100C.lib diff --git a/vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib b/vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib similarity index 100% rename from vlsi/extra_libraries/dco/ExampleDCO_PVT_0P77V_0C.lib rename to vlsi/extra_libraries/example/ExampleDCO_PVT_0P77V_0C.lib From 35566195dbbca8cc7b724769aae949757f3c87aa Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 27 Sep 2019 09:37:27 -0700 Subject: [PATCH 18/20] [skip ci] address comments, instantiate Sha3Accel module --- docs/VLSI/Advanced-Usage.rst | 8 +-- docs/VLSI/Tutorial.rst | 13 ++-- vlsi/example.v | 127 ++++++----------------------------- 3 files changed, 28 insertions(+), 120 deletions(-) diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index ba038f28..9d0afd76 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -5,14 +5,14 @@ Advanced Usage Alternative RTL Flows --------------------- -The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. +The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to give the following environment variables ``make buildfile`` (or edit them directly in the Makefile). .. code-block:: shell - export CUSTOM_VLOG= - export VLSI_TOP= + CUSTOM_VLOG= + VLSI_TOP= -``CUSTOM_VLOG`` breaks the dependency on the rest of the +``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files. Under the Hood -------------- diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index c16d85d6..bab71d4a 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -2,7 +2,7 @@ ASAP7 Tutorial ============== -The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins. +The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. Project Structure ----------------- @@ -81,18 +81,15 @@ To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all .. code-block:: shell - export MACROCOMPILER_MODE='--mode synflops' - export CONFIG=Sha3RocketConfig - export VLSI_TOP=Sha3AccelwBB - make buildfile + make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. -The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. +The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket-chip with the Sha3Accel module. -The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. +The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. Note that you should not set the ``TOP`` variable because it is used during Chisel elaboration. -For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. +For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. Running the VLSI Flow --------------------- diff --git a/vlsi/example.v b/vlsi/example.v index bd0d3f9d..dbc7bec5 100644 --- a/vlsi/example.v +++ b/vlsi/example.v @@ -1,4 +1,4 @@ -// Extracted Sha3Accel w/ a blackbox (a dummy DCO) included inside +// Sha3Accel w/ a blackbox (a dummy DCO) included inside module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4] @@ -25,84 +25,24 @@ module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] input sleep_b, output dco_clock ); - wire clock; // from dummy DCO - wire ctrl_clock; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_reset; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_rocc_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_rocc_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [1:0] ctrl_io_rocc_funct; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_rocc_rs1; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_rocc_rs2; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_busy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_dmem_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_dmem_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [6:0] ctrl_io_dmem_req_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [31:0] ctrl_io_dmem_req_addr; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [4:0] ctrl_io_dmem_req_cmd; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_dmem_resp_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [6:0] ctrl_io_dmem_resp_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_dmem_resp_data; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [4:0] ctrl_io_round; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_absorb; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [4:0] ctrl_io_aindex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_init; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_write; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [2:0] ctrl_io_windex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_buffer_out; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire dpath_clock; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_reset; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_io_absorb; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_io_init; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_io_write; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [4:0] dpath_io_round; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [4:0] dpath_io_aindex; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_message_in; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_0; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_1; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_2; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_3; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [1:0] _T; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4] - wire [63:0] _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - wire [63:0] _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - wire [63:0] _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - CtrlModule ctrl ( // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - .clock(ctrl_clock), - .reset(ctrl_reset), - .io_rocc_req_val(ctrl_io_rocc_req_val), - .io_rocc_req_rdy(ctrl_io_rocc_req_rdy), - .io_rocc_funct(ctrl_io_rocc_funct), - .io_rocc_rs1(ctrl_io_rocc_rs1), - .io_rocc_rs2(ctrl_io_rocc_rs2), - .io_busy(ctrl_io_busy), - .io_dmem_req_val(ctrl_io_dmem_req_val), - .io_dmem_req_rdy(ctrl_io_dmem_req_rdy), - .io_dmem_req_tag(ctrl_io_dmem_req_tag), - .io_dmem_req_addr(ctrl_io_dmem_req_addr), - .io_dmem_req_cmd(ctrl_io_dmem_req_cmd), - .io_dmem_resp_val(ctrl_io_dmem_resp_val), - .io_dmem_resp_tag(ctrl_io_dmem_resp_tag), - .io_dmem_resp_data(ctrl_io_dmem_resp_data), - .io_round(ctrl_io_round), - .io_absorb(ctrl_io_absorb), - .io_aindex(ctrl_io_aindex), - .io_init(ctrl_io_init), - .io_write(ctrl_io_write), - .io_windex(ctrl_io_windex), - .io_buffer_out(ctrl_io_buffer_out) - ); - DpathModule dpath ( // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - .clock(dpath_clock), - .reset(dpath_reset), - .io_absorb(dpath_io_absorb), - .io_init(dpath_io_init), - .io_write(dpath_io_write), - .io_round(dpath_io_round), - .io_aindex(dpath_io_aindex), - .io_message_in(dpath_io_message_in), - .io_hash_out_0(dpath_io_hash_out_0), - .io_hash_out_1(dpath_io_hash_out_1), - .io_hash_out_2(dpath_io_hash_out_2), - .io_hash_out_3(dpath_io_hash_out_3) + Sha3Accel sha3 ( + .clock(clock), + .reset(reset), + .io_cmd_ready(io_cmd_ready), + .io_cmd_valid(io_cmd_valid), + .io_cmd_bits_inst_funct(io_cmd_bits_inst_funct), + .io_cmd_bits_rs1(io_cmd_bits_rs1), + .io_cmd_bits_rs2(io_cmd_bits_rs2), + .io_mem_req_ready(io_mem_req_ready), + .io_mem_req_valid(io_mem_req_valid), + .io_mem_req_bits_addr(io_mem_req_bits_addr), + .io_mem_req_bits_tag(io_mem_req_bits_tag), + .io_mem_req_bits_cmd(io_mem_req_bits_cmd), + .io_mem_req_bits_data(io_mem_req_bits_data), + .io_mem_resp_valid(io_mem_resp_valid), + .io_mem_resp_bits_tag(io_mem_resp_bits_tag), + .io_mem_resp_bits_data(io_mem_resp_bits_data), + .io_busy(io_busy) ); ExampleDCO dco ( .col_sel_b(col_sel_b), @@ -112,35 +52,6 @@ module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] .sleep_b(sleep_b), .clock(dco_clock) ); - assign _T = ctrl_io_windex[1:0]; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4] - assign _GEN_0 = dpath_io_hash_out_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign _GEN_1 = 2'h1 == _T ? dpath_io_hash_out_1 : _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign _GEN_2 = 2'h2 == _T ? dpath_io_hash_out_2 : _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign io_cmd_ready = ctrl_io_rocc_req_rdy; // @[sha3.scala 64:16:example.TestHarness.Sha3RocketConfig.fir@135921.4] - assign io_mem_req_valid = ctrl_io_dmem_req_val; // @[sha3.scala 71:20:example.TestHarness.Sha3RocketConfig.fir@135927.4] - assign io_mem_req_bits_addr = {{8'd0}, ctrl_io_dmem_req_addr}; // @[sha3.scala 74:24:example.TestHarness.Sha3RocketConfig.fir@135930.4] - assign io_mem_req_bits_tag = {{1'd0}, ctrl_io_dmem_req_tag}; // @[sha3.scala 73:23:example.TestHarness.Sha3RocketConfig.fir@135929.4] - assign io_mem_req_bits_cmd = ctrl_io_dmem_req_cmd; // @[sha3.scala 75:23:example.TestHarness.Sha3RocketConfig.fir@135931.4] - assign io_mem_req_bits_data = 2'h3 == _T ? dpath_io_hash_out_3 : _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign io_busy = ctrl_io_busy; // @[sha3.scala 69:11:example.TestHarness.Sha3RocketConfig.fir@135926.4] - assign ctrl_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135918.4] - assign ctrl_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135919.4] - assign ctrl_io_rocc_req_val = io_cmd_valid; // @[sha3.scala 63:26:example.TestHarness.Sha3RocketConfig.fir@135920.4] - assign ctrl_io_rocc_funct = io_cmd_bits_inst_funct[1:0]; // @[sha3.scala 65:26:example.TestHarness.Sha3RocketConfig.fir@135922.4] - assign ctrl_io_rocc_rs1 = io_cmd_bits_rs1; // @[sha3.scala 66:26:example.TestHarness.Sha3RocketConfig.fir@135923.4] - assign ctrl_io_rocc_rs2 = io_cmd_bits_rs2; // @[sha3.scala 67:26:example.TestHarness.Sha3RocketConfig.fir@135924.4] - assign ctrl_io_dmem_req_rdy = io_mem_req_ready; // @[sha3.scala 72:26:example.TestHarness.Sha3RocketConfig.fir@135928.4] - assign ctrl_io_dmem_resp_val = io_mem_resp_valid; // @[sha3.scala 78:26:example.TestHarness.Sha3RocketConfig.fir@135933.4] - assign ctrl_io_dmem_resp_tag = io_mem_resp_bits_tag[6:0]; // @[sha3.scala 79:26:example.TestHarness.Sha3RocketConfig.fir@135934.4] - assign ctrl_io_dmem_resp_data = io_mem_resp_bits_data; // @[sha3.scala 80:26:example.TestHarness.Sha3RocketConfig.fir@135935.4] - assign dpath_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135938.4] - assign dpath_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135939.4] - assign dpath_io_absorb = ctrl_io_absorb; // @[sha3.scala 88:19:example.TestHarness.Sha3RocketConfig.fir@135943.4] - assign dpath_io_init = ctrl_io_init; // @[sha3.scala 89:17:example.TestHarness.Sha3RocketConfig.fir@135944.4] - assign dpath_io_write = ctrl_io_write; // @[sha3.scala 90:18:example.TestHarness.Sha3RocketConfig.fir@135945.4] - assign dpath_io_round = ctrl_io_round; // @[sha3.scala 91:18:example.TestHarness.Sha3RocketConfig.fir@135946.4] - assign dpath_io_aindex = ctrl_io_aindex; // @[sha3.scala 93:19:example.TestHarness.Sha3RocketConfig.fir@135948.4] - assign dpath_io_message_in = ctrl_io_buffer_out; // @[sha3.scala 84:23:example.TestHarness.Sha3RocketConfig.fir@135940.4] endmodule module ExampleDCO ( From f8a0e5047550f31ab83e39e11f50a74be2bb8245 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 27 Sep 2019 11:56:13 -0700 Subject: [PATCH 19/20] [skip ci] address Abe's comments --- docs/VLSI/Advanced-Usage.rst | 2 +- docs/VLSI/{HAMMER.rst => Hammer.rst} | 10 +++++----- docs/VLSI/Tutorial.rst | 16 ++++++++-------- docs/VLSI/index.rst | 4 ++-- 4 files changed, 16 insertions(+), 16 deletions(-) rename docs/VLSI/{HAMMER.rst => Hammer.rst} (88%) diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index 9d0afd76..c7e1bae2 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -5,7 +5,7 @@ Advanced Usage Alternative RTL Flows --------------------- -The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to give the following environment variables ``make buildfile`` (or edit them directly in the Makefile). +The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile). .. code-block:: shell diff --git a/docs/VLSI/HAMMER.rst b/docs/VLSI/Hammer.rst similarity index 88% rename from docs/VLSI/HAMMER.rst rename to docs/VLSI/Hammer.rst index 3a7def4b..11d80a07 100644 --- a/docs/VLSI/HAMMER.rst +++ b/docs/VLSI/Hammer.rst @@ -1,12 +1,12 @@ .. _hammer: -Core HAMMER +Core Hammer ================================ -`HAMMER `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. -HAMMER allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. +`Hammer `__ is a physical design generator that wraps around vendor specific technologies and tools to provide a single API to create ASICs. +Hammer allows for reusability in ASIC design while still providing the designers leeway to make their own modifications. -For more information, read the `HAMMER paper `__ and see the `GitHub repository `__ and associated documentation. +For more information, read the `Hammer paper `__ and see the `GitHub repository `__ and associated documentation. Hammer implements a VLSI flow using the following high-level constructs: @@ -28,7 +28,7 @@ Hooks are modifications to steps or actions that are programmatically defined in Configuration (Hammer IR) ========================= -To configure a Hammer flow, supply a set yaml or json configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions. +To configure a Hammer flow, supply a set ``yaml`` or ``json`` configuration files that chooses the tool and technology plugins and versions as well as any design specific configuration options. Collectively, this configuration API is referred to as Hammer IR and can be generated from higher-level abstractions. The current set of all available Hammer APIs is codified `here `__. diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index bab71d4a..40ce3abd 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -2,7 +2,7 @@ ASAP7 Tutorial ============== -The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. +The ``vlsi`` folder of this repository contains an example Hammer flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. Project Structure ----------------- @@ -54,8 +54,8 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball and do not extract it - * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it + * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. Initial Setup ------------- @@ -65,7 +65,7 @@ In the Chipyard root, run: ``./scripts/init-vlsi.sh asap7`` -to pull the HAMMER & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. +to pull the Hammer & plugin submodules. Note that for technologies other than ``asap7``, the tech submodule must be added in the ``vlsi`` folder first. Pull the Hammer environment into the shell: @@ -77,7 +77,7 @@ Pull the Hammer environment into the shell: Building the Design ------------------- -To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: +To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set up all prerequisites for the build system to push just the accelerator + hard macro through the flow: .. code-block:: shell @@ -85,7 +85,7 @@ To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. -The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket-chip with the Sha3Accel module. +The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. Note that you should not set the ``TOP`` variable because it is used during Chisel elaboration. @@ -96,7 +96,7 @@ Running the VLSI Flow example-vlsi ^^^^^^^^^^^^ -This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods. +This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. example.yml ^^^^^^^^^^^ @@ -110,7 +110,7 @@ Synthesis ``make syn`` -Post-synthesis logs and collateral are in ``build/syn-rundir``. The Raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. +Post-synthesis logs and collateral are in ``build/syn-rundir``. The raw QoR data is available at ``build/syn-rundir/reports``, and methods to extract this information for design space exploration are a WIP. Place-and-Route ^^^^^^^^^^^^^^^ diff --git a/docs/VLSI/index.rst b/docs/VLSI/index.rst index 8bc98b60..0f5d32d5 100644 --- a/docs/VLSI/index.rst +++ b/docs/VLSI/index.rst @@ -2,13 +2,13 @@ VLSI Flow ================================ The Chipyard framework aims to provide wrappers for a general VLSI flow. -In particular, we aim to support the HAMMER physical design generator flow. +In particular, we aim to support the Hammer physical design generator flow. .. toctree:: :maxdepth: 2 :caption: VLSI Flow: Building-A-Chip - HAMMER + Hammer Tutorial Advanced-Usage From bbe457d14dc9540d735c54edceeca5c4052e0edd Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 27 Sep 2019 17:42:35 -0700 Subject: [PATCH 20/20] Turn the GDS scaling into a new hook --- docs/VLSI/Tutorial.rst | 2 ++ vlsi/example-vlsi | 22 +++++++++++++++++++++- vlsi/hammer | 2 +- 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 40ce3abd..7c2e0d2f 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -98,6 +98,8 @@ example-vlsi ^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. +The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4. + example.yml ^^^^^^^^^^^ This contains the Hammer configuration for this example project. Example clock constraints, power straps definitions, placement constraints, and pin constraints are given. Additional configuration for the extra libraries and tools are at the bottom. diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 5d43f8c5..a17f4f0c 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -1,4 +1,5 @@ #!/usr/bin/env python3 +import os import hammer_vlsi from hammer_vlsi import CLIDriver, HammerToolHookAction @@ -26,6 +27,22 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: ''') return True +def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: + """ + Scale the final GDS by a factor of 4 + """ + x.append(''' +# Write script out to a temporary file and execute it +set fp [open "{script_file}" "w"] +puts -nonewline $fp "{script_text}" +close $fp +if {{ [catch {{ exec python3 {script_file} }} msg] }} {{ + puts "$::errorInfo" +}} +'''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) + return True + + class ExampleDriver(CLIDriver): def get_extra_par_hooks(self) -> List[HammerToolHookAction]: extra_hooks = [ @@ -39,8 +56,11 @@ class ExampleDriver(CLIDriver): # make_replacement_hook will replace the specified step with a custom hook hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), # make_removal_hook will remove the specified step from the flow - hammer_vlsi.HammerTool.make_removal_hook("place_bumps") + hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), # The target step in any of the above calls may be a default step or another one of your custom hooks + + # This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py) + hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds) ] return extra_hooks diff --git a/vlsi/hammer b/vlsi/hammer index 946c4f41..1b07b9a3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 946c4f416709663651580f7c4c1be2e2652dff6f +Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2