diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index ba038f28..9d0afd76 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -5,14 +5,14 @@ Advanced Usage Alternative RTL Flows --------------------- -The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to export the following environment variables before ``make buildfile``. +The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom verilog module through, one only needs to give the following environment variables ``make buildfile`` (or edit them directly in the Makefile). .. code-block:: shell - export CUSTOM_VLOG= - export VLSI_TOP= + CUSTOM_VLOG= + VLSI_TOP= -``CUSTOM_VLOG`` breaks the dependency on the rest of the +``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files. Under the Hood -------------- diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index c16d85d6..bab71d4a 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -2,7 +2,7 @@ ASAP7 Tutorial ============== -The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro in the ASAP7 PDK. It is intended for use with the Cadence and Mentor tool plugins. +The ``vlsi`` folder of this repository contains an example HAMMER flow with the SHA-3 accelerator and a dummy hard macro. This example tutorial uses the built-in ASAP7 technology plugin and requires access to the included Cadence and Mentor tool plugin submodules. Cadence is necessary for synthesis & place-and-route, while Mentor is needed for DRC & LVS. Project Structure ----------------- @@ -81,18 +81,15 @@ To elaborate the Sha3RocketConfig (Rocketchip w/ the accelerator) and set up all .. code-block:: shell - export MACROCOMPILER_MODE='--mode synflops' - export CONFIG=Sha3RocketConfig - export VLSI_TOP=Sha3AccelwBB - make buildfile + make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. -The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. +The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket-chip with the Sha3Accel module. -The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. +The ``VLSI_TOP=Sha3AccelwBB`` indicates that we are only interested in physical design of the accelerator block. If this variable is not set, the entire SoC will be pushed through physical design. Note that you should not set the ``TOP`` variable because it is used during Chisel elaboration. -For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. +For the curious, ``make buildfile`` generates a set of Make targets in ``build/hammer.d``. It needs to be re-run if environment variables are changed. It is recommended that you edit these variables directly in the Makefile rather than exporting them to your shell environment. Running the VLSI Flow --------------------- diff --git a/vlsi/example.v b/vlsi/example.v index bd0d3f9d..dbc7bec5 100644 --- a/vlsi/example.v +++ b/vlsi/example.v @@ -1,4 +1,4 @@ -// Extracted Sha3Accel w/ a blackbox (a dummy DCO) included inside +// Sha3Accel w/ a blackbox (a dummy DCO) included inside module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4] @@ -25,84 +25,24 @@ module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] input sleep_b, output dco_clock ); - wire clock; // from dummy DCO - wire ctrl_clock; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_reset; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_rocc_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_rocc_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [1:0] ctrl_io_rocc_funct; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_rocc_rs1; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_rocc_rs2; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_busy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_dmem_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_dmem_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [6:0] ctrl_io_dmem_req_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [31:0] ctrl_io_dmem_req_addr; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [4:0] ctrl_io_dmem_req_cmd; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_dmem_resp_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [6:0] ctrl_io_dmem_resp_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_dmem_resp_data; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [4:0] ctrl_io_round; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_absorb; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [4:0] ctrl_io_aindex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_init; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire ctrl_io_write; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [2:0] ctrl_io_windex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire [63:0] ctrl_io_buffer_out; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - wire dpath_clock; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_reset; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_io_absorb; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_io_init; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire dpath_io_write; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [4:0] dpath_io_round; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [4:0] dpath_io_aindex; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_message_in; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_0; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_1; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_2; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [63:0] dpath_io_hash_out_3; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - wire [1:0] _T; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4] - wire [63:0] _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - wire [63:0] _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - wire [63:0] _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - CtrlModule ctrl ( // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4] - .clock(ctrl_clock), - .reset(ctrl_reset), - .io_rocc_req_val(ctrl_io_rocc_req_val), - .io_rocc_req_rdy(ctrl_io_rocc_req_rdy), - .io_rocc_funct(ctrl_io_rocc_funct), - .io_rocc_rs1(ctrl_io_rocc_rs1), - .io_rocc_rs2(ctrl_io_rocc_rs2), - .io_busy(ctrl_io_busy), - .io_dmem_req_val(ctrl_io_dmem_req_val), - .io_dmem_req_rdy(ctrl_io_dmem_req_rdy), - .io_dmem_req_tag(ctrl_io_dmem_req_tag), - .io_dmem_req_addr(ctrl_io_dmem_req_addr), - .io_dmem_req_cmd(ctrl_io_dmem_req_cmd), - .io_dmem_resp_val(ctrl_io_dmem_resp_val), - .io_dmem_resp_tag(ctrl_io_dmem_resp_tag), - .io_dmem_resp_data(ctrl_io_dmem_resp_data), - .io_round(ctrl_io_round), - .io_absorb(ctrl_io_absorb), - .io_aindex(ctrl_io_aindex), - .io_init(ctrl_io_init), - .io_write(ctrl_io_write), - .io_windex(ctrl_io_windex), - .io_buffer_out(ctrl_io_buffer_out) - ); - DpathModule dpath ( // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4] - .clock(dpath_clock), - .reset(dpath_reset), - .io_absorb(dpath_io_absorb), - .io_init(dpath_io_init), - .io_write(dpath_io_write), - .io_round(dpath_io_round), - .io_aindex(dpath_io_aindex), - .io_message_in(dpath_io_message_in), - .io_hash_out_0(dpath_io_hash_out_0), - .io_hash_out_1(dpath_io_hash_out_1), - .io_hash_out_2(dpath_io_hash_out_2), - .io_hash_out_3(dpath_io_hash_out_3) + Sha3Accel sha3 ( + .clock(clock), + .reset(reset), + .io_cmd_ready(io_cmd_ready), + .io_cmd_valid(io_cmd_valid), + .io_cmd_bits_inst_funct(io_cmd_bits_inst_funct), + .io_cmd_bits_rs1(io_cmd_bits_rs1), + .io_cmd_bits_rs2(io_cmd_bits_rs2), + .io_mem_req_ready(io_mem_req_ready), + .io_mem_req_valid(io_mem_req_valid), + .io_mem_req_bits_addr(io_mem_req_bits_addr), + .io_mem_req_bits_tag(io_mem_req_bits_tag), + .io_mem_req_bits_cmd(io_mem_req_bits_cmd), + .io_mem_req_bits_data(io_mem_req_bits_data), + .io_mem_resp_valid(io_mem_resp_valid), + .io_mem_resp_bits_tag(io_mem_resp_bits_tag), + .io_mem_resp_bits_data(io_mem_resp_bits_data), + .io_busy(io_busy) ); ExampleDCO dco ( .col_sel_b(col_sel_b), @@ -112,35 +52,6 @@ module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2] .sleep_b(sleep_b), .clock(dco_clock) ); - assign _T = ctrl_io_windex[1:0]; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4] - assign _GEN_0 = dpath_io_hash_out_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign _GEN_1 = 2'h1 == _T ? dpath_io_hash_out_1 : _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign _GEN_2 = 2'h2 == _T ? dpath_io_hash_out_2 : _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign io_cmd_ready = ctrl_io_rocc_req_rdy; // @[sha3.scala 64:16:example.TestHarness.Sha3RocketConfig.fir@135921.4] - assign io_mem_req_valid = ctrl_io_dmem_req_val; // @[sha3.scala 71:20:example.TestHarness.Sha3RocketConfig.fir@135927.4] - assign io_mem_req_bits_addr = {{8'd0}, ctrl_io_dmem_req_addr}; // @[sha3.scala 74:24:example.TestHarness.Sha3RocketConfig.fir@135930.4] - assign io_mem_req_bits_tag = {{1'd0}, ctrl_io_dmem_req_tag}; // @[sha3.scala 73:23:example.TestHarness.Sha3RocketConfig.fir@135929.4] - assign io_mem_req_bits_cmd = ctrl_io_dmem_req_cmd; // @[sha3.scala 75:23:example.TestHarness.Sha3RocketConfig.fir@135931.4] - assign io_mem_req_bits_data = 2'h3 == _T ? dpath_io_hash_out_3 : _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4] - assign io_busy = ctrl_io_busy; // @[sha3.scala 69:11:example.TestHarness.Sha3RocketConfig.fir@135926.4] - assign ctrl_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135918.4] - assign ctrl_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135919.4] - assign ctrl_io_rocc_req_val = io_cmd_valid; // @[sha3.scala 63:26:example.TestHarness.Sha3RocketConfig.fir@135920.4] - assign ctrl_io_rocc_funct = io_cmd_bits_inst_funct[1:0]; // @[sha3.scala 65:26:example.TestHarness.Sha3RocketConfig.fir@135922.4] - assign ctrl_io_rocc_rs1 = io_cmd_bits_rs1; // @[sha3.scala 66:26:example.TestHarness.Sha3RocketConfig.fir@135923.4] - assign ctrl_io_rocc_rs2 = io_cmd_bits_rs2; // @[sha3.scala 67:26:example.TestHarness.Sha3RocketConfig.fir@135924.4] - assign ctrl_io_dmem_req_rdy = io_mem_req_ready; // @[sha3.scala 72:26:example.TestHarness.Sha3RocketConfig.fir@135928.4] - assign ctrl_io_dmem_resp_val = io_mem_resp_valid; // @[sha3.scala 78:26:example.TestHarness.Sha3RocketConfig.fir@135933.4] - assign ctrl_io_dmem_resp_tag = io_mem_resp_bits_tag[6:0]; // @[sha3.scala 79:26:example.TestHarness.Sha3RocketConfig.fir@135934.4] - assign ctrl_io_dmem_resp_data = io_mem_resp_bits_data; // @[sha3.scala 80:26:example.TestHarness.Sha3RocketConfig.fir@135935.4] - assign dpath_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135938.4] - assign dpath_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135939.4] - assign dpath_io_absorb = ctrl_io_absorb; // @[sha3.scala 88:19:example.TestHarness.Sha3RocketConfig.fir@135943.4] - assign dpath_io_init = ctrl_io_init; // @[sha3.scala 89:17:example.TestHarness.Sha3RocketConfig.fir@135944.4] - assign dpath_io_write = ctrl_io_write; // @[sha3.scala 90:18:example.TestHarness.Sha3RocketConfig.fir@135945.4] - assign dpath_io_round = ctrl_io_round; // @[sha3.scala 91:18:example.TestHarness.Sha3RocketConfig.fir@135946.4] - assign dpath_io_aindex = ctrl_io_aindex; // @[sha3.scala 93:19:example.TestHarness.Sha3RocketConfig.fir@135948.4] - assign dpath_io_message_in = ctrl_io_buffer_out; // @[sha3.scala 84:23:example.TestHarness.Sha3RocketConfig.fir@135940.4] endmodule module ExampleDCO (