From 5bda60063a2992df9832237faa11416ba13d8d74 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 5 Sep 2019 00:14:21 +0000 Subject: [PATCH 1/3] [firesim] Initial Golden Gate support --- .../firechip/src/main/scala/SimConfigs.scala | 4 +++ .../src/main/scala/TargetMixins.scala | 27 ++++++++++++++++++- .../firechip/src/main/scala/Targets.scala | 4 +++ .../src/test/scala/ScalaTestSuite.scala | 7 ++--- sims/firesim | 2 +- 5 files changed, 39 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 1118fe07..937c2877 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -52,3 +52,7 @@ class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( new FRFCFS16GBQuadRankLLC4MB3Div ++ new FireSimConfig) +class Midas2Config extends Config( + new WithMultiCycleRamModels ++ + new FireSimConfig) + diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 199a22cc..76dc224e 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -1,6 +1,7 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ @@ -12,7 +13,7 @@ import freechips.rocketchip.rocket.TracedInstruction import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.models.AXI4BundleWithEdge -import midas.targetutils.ExcludeInstanceAsserts +import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges * associated with each port. This drives FASED functional model sizing @@ -103,3 +104,27 @@ trait HasTraceIOImp extends LazyModuleImp { trait ExcludeInvalidBoomAssertions extends LazyModuleImp { ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb")) } + +trait CanHaveBoomMultiCycleRegfileImp { + val outer: boom.system.BoomRocketSubsystem + val cores = outer.boomTiles.map(tile => tile.module.core) + cores.foreach({ core => + core.iregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + + if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + + }) +} +trait CanHaveRocketMultiCycleRegfileImp { + val outer: RocketSubsystem + outer.rocketTiles.foreach({ tile => + annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf)) + tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + }) +} diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index ba966fac..33a25da2 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -55,6 +55,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasPeripheryIceNICModuleImpValidOnly with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with CanHaveRocketMultiCycleRegfileImp class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem @@ -79,6 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with CanHaveRocketMultiCycleRegfileImp class FireBoom(implicit p: Parameters) extends Subsystem @@ -106,6 +108,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l) with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions + with CanHaveBoomMultiCycleRegfileImp class FireBoomNoNIC(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -130,6 +133,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleI with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions + with CanHaveBoomMultiCycleRegfileImp case object NumNodes extends Field[Int] diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 54848ac8..44c4bff0 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,9 +109,9 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 50 + val resetLength = 51 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1) + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { @@ -131,8 +131,9 @@ abstract class FireSimTestSuite( } class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig") -class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig") class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") { runSuite("verilator")(NICLoopbackTests) } +class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config") +class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config") diff --git a/sims/firesim b/sims/firesim index 4cd75833..a3d48a43 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4cd75833dfc1f9f796a1c5505ece6937fd253189 +Subproject commit a3d48a43a972e663e45a2ce4617a798a940d6a2b From 9bf174afb37baf66804a4b67dbca14bf3ee54f0d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 9 Sep 2019 06:41:15 +0000 Subject: [PATCH 2/3] [firechip] Update regfile optimization mixins --- .../firechip/src/main/scala/TargetMixins.scala | 13 +++++-------- generators/firechip/src/main/scala/Targets.scala | 16 ++++++++-------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 76dc224e..f36cf021 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -105,10 +105,10 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp { ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb")) } -trait CanHaveBoomMultiCycleRegfileImp { - val outer: boom.system.BoomRocketSubsystem - val cores = outer.boomTiles.map(tile => tile.module.core) - cores.foreach({ core => +trait CanHaveMultiCycleRegfileImp { + val outer: utilities.HasBoomAndRocketTiles + val boomCores = outer.boomTiles.map(tile => tile.module.core) + boomCores.foreach({ core => core.iregfile match { case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) case _ => Nil @@ -118,11 +118,8 @@ trait CanHaveBoomMultiCycleRegfileImp { case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) case _ => Nil } + }) - }) -} -trait CanHaveRocketMultiCycleRegfileImp { - val outer: RocketSubsystem outer.rocketTiles.foreach({ tile => annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf)) tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 33a25da2..37c1f2b1 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -31,7 +31,7 @@ import java.io.File * determine which driver to build. *******************************************************************************/ -class FireSim(implicit p: Parameters) extends RocketSubsystem +class FireSim(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -45,7 +45,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimModuleImp(this) } -class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) +class FireSimModuleImp[+L <: FireSim](l: L) extends SubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -55,10 +55,10 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasPeripheryIceNICModuleImpValidOnly with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp - with CanHaveRocketMultiCycleRegfileImp + with CanHaveMultiCycleRegfileImp -class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem +class FireSimNoNIC(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -71,7 +71,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimNoNICModuleImp(this) } -class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l) +class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends SubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -80,7 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp - with CanHaveRocketMultiCycleRegfileImp + with CanHaveMultiCycleRegfileImp class FireBoom(implicit p: Parameters) extends Subsystem @@ -108,7 +108,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l) with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions - with CanHaveBoomMultiCycleRegfileImp + with CanHaveMultiCycleRegfileImp class FireBoomNoNIC(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -133,7 +133,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleI with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions - with CanHaveBoomMultiCycleRegfileImp + with CanHaveMultiCycleRegfileImp case object NumNodes extends Field[Int] From 6b4ea0fd61c42b9110fb9a0e79e8798fa2d54565 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 10 Sep 2019 04:26:28 +0000 Subject: [PATCH 3/3] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index c4b24a41..92fe0e4d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c4b24a410b63dbd89c6921b1aef2252727cd29f3 +Subproject commit 92fe0e4def4d9bde0c5c36cd9090ef8c60fd0d45