From 38588b67efcaefe6e9c23184fd981ab65cdf8ffb Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Thu, 19 Sep 2019 15:21:08 -0700
Subject: [PATCH] Bump FireSim, update reset delay in ScalaTests

---
 generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +-
 sims/firesim                                            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala
index 44c4bff0..7a07e950 100644
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -109,7 +109,7 @@ abstract class FireSimTestSuite(
         val lines = Source.fromFile(file).getLines.toList
         lines.filter(_.startsWith("TRACEPORT")).drop(dropLines)
       }
-      val resetLength = 51
+      val resetLength = 50
       val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"))
       val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
       assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
diff --git a/sims/firesim b/sims/firesim
index 92fe0e4d..9eaa0dc8 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 92fe0e4def4d9bde0c5c36cd9090ef8c60fd0d45
+Subproject commit 9eaa0dc85081a06ad25b3ed21ebf63942f6c061b