From 4d7cf6ec0ef00f252ba3cfe1781a43e190d220d1 Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Fri, 10 Mar 2023 14:16:41 -0800 Subject: [PATCH 1/3] adding hammer paper to main readme --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 7e44cc11..a21b142e 100644 --- a/README.md +++ b/README.md @@ -84,6 +84,7 @@ These additional publications cover many of the internal components used in Chip * **FireMarshal**: N. Pemberton, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408192). * **VLSI** * **Hammer**: E. Wang, et al., *ISQED'20*. [PDF](https://www.isqed.org/English/Archives/2020/Technical_Sessions/113.html). + * **Hammer**: H. Liew, et al., *DAC'22*. [PDF](https://dl.acm.org/doi/abs/10.1145/3489517.3530672). ## Acknowledgements From 81e11ee8e0a18fc56ab263588b7a17637888846b Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Fri, 10 Mar 2023 15:09:15 -0800 Subject: [PATCH 2/3] updating macro paths for asap7 tutorial to match new SRAM paths after rocket/chisel bump --- vlsi/example-asap7.yml | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 8aafe8c0..dbcadab0 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -37,54 +37,47 @@ vlsi.inputs.placement_constraints: right: 0 top: 0 bottom: 0 - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" type: hardmacro x: 550 y: 25 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_1" type: hardmacro x: 550 y: 270 orientation: "r0" top_layer: "M4" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_2" type: hardmacro x: 675 y: 25 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_3" type: hardmacro x: 675 y: 270 orientation: "r0" top_layer: "M4" master: "SRAM1RW4096x8" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" type: hardmacro x: 125 y: 150 orientation: "my" top_layer: "M4" master: "SRAM1RW64x21" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" + - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" type: hardmacro x: 0 y: 25 orientation: "my" top_layer: "M4" master: "SRAM1RW1024x32" - - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" - type: hardmacro - x: 0 - y: 260 - orientation: "my" - top_layer: "M4" - master: "SRAM1RW1024x37" # Pin placement constraints vlsi.inputs.pin_mode: generated From 89a23faa006b410fff93e3b3d7efa68be735057d Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Fri, 10 Mar 2023 15:09:56 -0800 Subject: [PATCH 3/3] updating docs to include correct build path [skip ci] --- docs/VLSI/ASAP7-Tutorial.rst | 4 ++-- docs/VLSI/Sky130-Commercial-Tutorial.rst | 4 ++-- docs/VLSI/Sky130-OpenROAD-Tutorial.rst | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/docs/VLSI/ASAP7-Tutorial.rst b/docs/VLSI/ASAP7-Tutorial.rst index ddeda299..5544a4ae 100644 --- a/docs/VLSI/ASAP7-Tutorial.rst +++ b/docs/VLSI/ASAP7-Tutorial.rst @@ -126,9 +126,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc CONFIG=TinyRocketConfig - ./build/drc-rundir/generated-scripts/view-drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view-drc make lvs CONFIG=TinyRocketConfig - ./build/lvs-rundir/generated-scripts/view-lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view-lvs Some DRC errors are expected from this PDK, as explained in the `ASAP7 plugin readme `__. Furthermore, the dummy SRAMs that are provided in this tutorial and PDK do not have any geometry inside, so will certainly cause DRC errors. diff --git a/docs/VLSI/Sky130-Commercial-Tutorial.rst b/docs/VLSI/Sky130-Commercial-Tutorial.rst index 0b371c26..ccbdc157 100644 --- a/docs/VLSI/Sky130-Commercial-Tutorial.rst +++ b/docs/VLSI/Sky130-Commercial-Tutorial.rst @@ -161,9 +161,9 @@ To run DRC & LVS, and view the results in Calibre: .. code-block:: shell make drc tutorial=sky130-commercial - ./build/drc-rundir/generated-scripts/view_drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-commercial - ./build/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 7a7a9aa3..e4f5f80a 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -184,7 +184,7 @@ Hammer generates a convenient script to launch these sessions .. code-block:: shell - cd ./build/par-rundir + cd ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated-scripts/open_chip Note that the conda OpenROAD package was compiled with the GUI disabled, so in order to view the layout, @@ -199,7 +199,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin .. code-block:: shell - cd build/par-rundir + cd build/chipyard.TestHarness.TinyRocketConfig-ChipTop/par-rundir ./generated_scripts/open_chip -h " Usage: ./generated-scripts/open_chip [-t] [openroad_db_name] @@ -215,7 +215,7 @@ These databases can be restored using the same ``open_chip`` script for debuggin # load post-clock tree database with timing inforamtion ./generated_scripts/open_chip -t post_clock_tree -.. Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. +Various reports, including timing reports, are found in ``build/par-rundir/reports``. See the `OpenROAD tool plugin `__ for the full list of OpenROAD tool steps and their implementations. @@ -232,9 +232,9 @@ To run DRC & LVS in Magic & Netgen, respectively: .. code-block:: shell make drc tutorial=sky130-openroad - ./build/drc-rundir/generated-scripts/view_drc + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/drc-rundir/generated-scripts/view_drc make lvs tutorial=sky130-openroad - ./build/lvs-rundir/generated-scripts/view_lvs + ./build/chipyard.TestHarness.TinyRocketConfig-ChipTop/lvs-rundir/generated-scripts/view_lvs Note that in ``sky130-openroad.yml`` we have set the following YAML keys: