Fix clock name and macro paths for Sky130 VLSI flow (#1882)

2024-05-19 17:54:47 -07:00
parent ef71dfd40a
commit 3a6677bc30
7 changed files with 20 additions and 28 deletions
--- a/vlsi/example-designs/sky130-commercial.yml
+++ b/vlsi/example-designs/sky130-commercial.yml
@@ -2,7 +2,7 @@

 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"}
+  {name: "clock_uncore", period: "30ns", uncertainty: "2ns"}
 ]

 # Placement Constraints