wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fix clock name and macro paths for Sky130 VLSI flow (#1882)

Browse Source
This commit is contained in:
Nayiri
2024-05-19 17:54:47 -07:00
committed by GitHub
parent ef71dfd40a
commit 3a6677bc30
7 changed files with 20 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
vlsi/example-asap7.yml
View File

@@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "1ns", uncertainty: "0.1ns"}
{name: "clock_uncore", period: "1ns", uncertainty: "0.1ns"}
]
# Generate Make include to aid in flow

2
vlsi/example-design.yml
View File

@@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "2ns", uncertainty: "0.1ns"}
{name: "clock_uncore", period: "2ns", uncertainty: "0.1ns"}
]
# Specify pin properties

2
vlsi/example-designs/sky130-commercial.yml
View File

@@ -2,7 +2,7 @@
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "30ns", uncertainty: "2ns"}
{name: "clock_uncore", period: "30ns", uncertainty: "2ns"}
]
# Placement Constraints

5
vlsi/example-designs/sky130-openroad-rockettile.yml
View File

@@ -1,7 +1,7 @@
# Override configurations in ../example-sky130.yml and example-designs
# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore"
vlsi.inputs.clocks: [
{name: "clock", period: "30ns", uncertainty: "3ns"}
]
@@ -22,7 +22,7 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
# data cache
# data cache
- path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
@@ -47,3 +47,4 @@ vlsi.inputs.placement_constraints:
x: 50
y: 2100
orientation: r90

23
vlsi/example-designs/sky130-openroad.yml
View File

@@ -3,7 +3,7 @@
# Specify clock signals
# Relax the clock period for OpenROAD to meet timing
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "50ns", uncertainty: "2ns"}
{name: "clock_uncore", period: "50ns", uncertainty: "2ns"}
]
# Flow parameters that yield a routable design with reasonable timing
@@ -54,36 +54,27 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
# data cache
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 450
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 850
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1250
y: 800
orientation: r90
# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1600
orientation: r90
# instruction cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100

2
vlsi/example-designs/sky130-rocket.yml
View File

@@ -1,7 +1,7 @@
# Override configurations in ../example-sky130.yml and example-designs
# Specify clock signals
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore"
vlsi.inputs.clocks: [
{name: "clock", period: "5ns", uncertainty: "1ns"}
]

12
vlsi/example-sky130.yml
View File

@@ -20,7 +20,7 @@ vlsi.inputs.power_spec_type: "cpf"
# Specify clock signals
vlsi.inputs.clocks: [
{name: "clock_uncore_clock", period: "20ns", uncertainty: "1ns"}
{name: "clock_uncore", period: "20ns", uncertainty: "1ns"}
]
# Generate Make include to aid in flow
@@ -42,27 +42,27 @@ vlsi.inputs.placement_constraints:
bottom: 10
# Place SRAM memory instances
# data cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
# data cache
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 50
orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 800
orientation: r90
# tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1600
orientation: r90
# instruction cache
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
- path: "ChipTop/system/tile_prci_domain/element_reset_domain_rockettile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 2100