wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

fix

Browse Source
This commit is contained in:
joey0320
2023-03-11 20:02:53 -08:00
parent d7574084c1
commit 3b79de660f
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
docs/Tools/FIRRTL.rst
View File

@@ -7,6 +7,6 @@ Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which
An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
Once the transformations are done, a Verilog file is emitted and the build process is done.
To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`Customization/Firrtl-Transforms` section.
To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section.
For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.