From 3c42e2cae7a903d4d3e914d90405274e247cbbb1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 26 Oct 2020 18:15:58 -0700 Subject: [PATCH] Fixed BootROM | Updated HarnessBinders --- fpga/src/main/resources/vcu118/sdboot/head.S | 3 ++- .../vcu118/sdboot/linker/sdboot.elf.lds | 1 + .../main/scala/vcu118/bringup/Configs.scala | 19 +++++++------- .../scala/vcu118/bringup/HarnessBinders.scala | 13 +++++----- .../main/scala/vcu118/bringup/IOBinders.scala | 25 +++++++++++++------ .../scala/vcu118/bringup/TestHarness.scala | 5 +++- .../chipyard/src/main/scala/ChipTop.scala | 4 +-- generators/sifive-blocks | 2 +- 8 files changed, 43 insertions(+), 29 deletions(-) diff --git a/fpga/src/main/resources/vcu118/sdboot/head.S b/fpga/src/main/resources/vcu118/sdboot/head.S index 662a6fd2..d871b824 100644 --- a/fpga/src/main/resources/vcu118/sdboot/head.S +++ b/fpga/src/main/resources/vcu118/sdboot/head.S @@ -16,5 +16,6 @@ _prog_start: li s1, PAYLOAD_DEST jr s1 - .section .rodata + .section .dtb + .align 3 dtb: diff --git a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds index 34610c94..7a0a42fe 100644 --- a/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds +++ b/fpga/src/main/resources/vcu118/sdboot/linker/sdboot.elf.lds @@ -47,6 +47,7 @@ SECTIONS .rodata ALIGN((ADDR(.sdata) + SIZEOF(.sdata)), 8) : AT(ALIGN((LOADADDR(.sdata) + SIZEOF(.sdata)), 8)) ALIGN_WITH_INPUT { *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.dtb) } >bootrom_mem :data PROVIDE(_data = ADDR(.rodata)); diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala index 8db731ed..79dbf6db 100644 --- a/fpga/src/main/scala/vcu118/bringup/Configs.scala +++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala @@ -18,7 +18,7 @@ import sifive.blocks.devices.uart._ import sifive.blocks.devices.i2c._ import sifive.fpgashells.shell.{DesignKey} -import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD} +import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize} import chipyard.{BuildTop} @@ -29,12 +29,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { UARTParams(address = BigInt(0x64000000L)), UARTParams(address = BigInt(0x64003000L))) case PeripherySPIKey => List( - SPIParams(rAddress = BigInt(0x64001000L), - injectFunc = Some((spi: TLSPI) => { - ResourceBinding { - Resource(new MMCDevice(spi.device, 1), "reg").bind(ResourceAddress(0)) - } - })), + SPIParams(rAddress = BigInt(0x64001000L)), SPIParams(rAddress = BigInt(0x64004000L))) case VCU118ShellPMOD => "SDIO" case PeripheryI2CKey => List( @@ -56,6 +51,7 @@ class WithBringupPeripherals extends Config((site, here, up) => { class SmallModifications extends Config((site, here, up) => { case DebugModuleKey => None // disable debug module + case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS case SystemBusKey => up(SystemBusKey).copy( errorDevice = Some(DevNullParams( Seq(AddressSet(0x3000, 0xfff)), @@ -79,6 +75,10 @@ class WithBootROM extends Config((site, here, up) => { } }) +class WithExtMemSetToDDR extends Config((site, here, up) => { + case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) +}) + class FakeBringupConfig extends Config( new SmallModifications ++ new WithBringupUART ++ @@ -92,6 +92,7 @@ class FakeBringupConfig extends Config( new WithGPIOIOPassthrough ++ new WithTLIOPassthrough ++ new WithBringupPeripherals ++ + new WithExtMemSetToDDR ++ // set the external mem port size properly new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new chipyard.config.WithNoSubsystemDrivenClocks ++ new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ @@ -100,8 +101,8 @@ class FakeBringupConfig extends Config( new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + //new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new chipyard.WithMulticlockCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala index efe805cd..79f602dc 100644 --- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala @@ -1,7 +1,7 @@ package chipyard.fpga.vcu118.bringup import chisel3._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.{Analog, IO, BaseModule} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.config.{Parameters, Field} @@ -19,13 +19,12 @@ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ import sifive.blocks.devices.gpio._ -import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer} import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences} import chipyard.harness._ /*** UART ***/ class WithBringupUART extends OverrideHarnessBinder({ - (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { + (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) @@ -39,7 +38,7 @@ class WithBringupUART extends OverrideHarnessBinder({ /*** SPI ***/ class WithBringupSPI extends OverrideHarnessBinder({ - (system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { + (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 2) @@ -53,7 +52,7 @@ class WithBringupSPI extends OverrideHarnessBinder({ /*** I2C ***/ class WithBringupI2C extends OverrideHarnessBinder({ - (system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => { + (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) @@ -66,7 +65,7 @@ class WithBringupI2C extends OverrideHarnessBinder({ /*** GPIO ***/ class WithBringupGPIO extends OverrideHarnessBinder({ - (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { + (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) => bb_io.bundle <> dut_io @@ -79,7 +78,7 @@ class WithBringupGPIO extends OverrideHarnessBinder({ /*** Experimental DDR ***/ class WithBringupDDR extends OverrideHarnessBinder({ - (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { + (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => { th match { case vcu118th: BringupVCU118FPGATestHarnessImp => { require(ports.size == 1) diff --git a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala index ece212bb..558b074f 100644 --- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala +++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala @@ -5,7 +5,7 @@ import chisel3.util.experimental.{BoringUtils} import chisel3.experimental.{Analog, IO, DataMirror} import freechips.rocketchip.config._ -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress, InModuleBody} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.jtag.{JTAGIO} import freechips.rocketchip.subsystem._ @@ -27,7 +27,7 @@ import testchipip._ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly} import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort} -import chipyard.iobinders.{OverrideIOBinder} +import chipyard.iobinders.{OverrideIOBinder, OverrideLazyIOBinder} class WithUARTIOPassthrough extends OverrideIOBinder({ (system: HasPeripheryUARTModuleImp) => { @@ -49,13 +49,22 @@ class WithGPIOIOPassthrough extends OverrideIOBinder({ } }) -class WithSPIIOPassthrough extends OverrideIOBinder({ - (system: HasPeripherySPIModuleImp) => { - val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } - (io_spi_pins_temp zip system.spi).map { case (io, sysio) => - io <> sysio +class WithSPIIOPassthrough extends OverrideLazyIOBinder({ + (system: HasPeripherySPI) => { + // attach resource to 1st SPI + ResourceBinding { + Resource(new MMCDevice(system.tlSpiNodes.head.device, 1), "reg").bind(ResourceAddress(0)) + } + + InModuleBody { + system.asInstanceOf[BaseSubsystem].module match { case system: HasPeripherySPIModuleImp => { + val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") } + (io_spi_pins_temp zip system.spi).map { case (io, sysio) => + io <> sysio + } + (io_spi_pins_temp, Nil) + } } } - (io_spi_pins_temp, Nil) } }) diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala index 4eaea05b..9f51d2aa 100644 --- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala @@ -20,6 +20,7 @@ import sifive.blocks.devices.gpio._ import chipyard.harness._ import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop} +import chipyard.iobinders.{HasIOBinders} case object DUTFrequencyKey extends Field[Double](100.0) @@ -186,6 +187,8 @@ class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) exte // harness binders are non-lazy _outer.topDesign match { case d: HasTestHarnessFunctions => d.harnessFunctions.foreach(_(this)) - ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap) + } + _outer.topDesign match { case d: HasIOBinders => + ApplyHarnessBinders(this, d.lazySystem, d.portMap) } } diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index bf07bcee..61a043b6 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -23,8 +23,8 @@ case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) * drive clock and reset generation */ -class ChipTop(implicit p: Parameters) extends LazyModule - with HasTestHarnessFunctions with HasIOBinders with BindingScope { +class ChipTop(implicit p: Parameters) extends LazyModule with BindingScope + with HasTestHarnessFunctions with HasIOBinders { // The system module specified by BuildSystem lazy val lazySystem = LazyModule(p(BuildSystem)(p)).suggestName("system") diff --git a/generators/sifive-blocks b/generators/sifive-blocks index c160544e..25eae85e 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit c160544e74db4f33d51f23c8a41c07a1ec16b7b7 +Subproject commit 25eae85e711d650a305eb1cd923421a2872fcc56