Merge pull request #186 from ucb-bar/dsptools

Add dsptools

.gitmodules

@@ -46,3 +46,12 @@
 [submodule "vlsi/hammer-cad-plugins"]
 	path = vlsi/hammer-cad-plugins
 	url = https://github.com/ucb-bar/hammer-cad-plugins.git
+[submodule "tools/dsptools"]
+	path = tools/dsptools
+	url = https://github.com/ucb-bar/dsptools.git
+[submodule "tools/chisel-testers"]
+	path = tools/chisel-testers
+	url = https://github.com/freechipsproject/chisel-testers.git
+[submodule "tools/treadle"]
+	path = tools/treadle
+	url = https://github.com/freechipsproject/treadle.git

build.sbt

@@ -43,6 +43,22 @@ def conditionalDependsOn(prj: Project): Project = {
   }
 }
 
+/**
+  * It has been a struggle for us to override settings in subprojects.
+  * An example would be adding a dependency to rocketchip on midas's targetutils library,
+  * or replacing dsptools's maven dependency on chisel with the local chisel project.
+  *
+  * This function works around this by specifying the project's root at src/ and overriding
+  * scalaSource and resourceDirectory.
+  */
+def freshProject(name: String, dir: File): Project = {
+  Project(id = name, base = dir / "src")
+    .settings(
+      scalaSource in Compile := baseDirectory.value / "main" / "scala",
+      resourceDirectory in Compile := baseDirectory.value / "main" / "resources"
+    )
+}
+
 // Fork each scala test for now, to work around persistent mutable state
 // in Rocket-Chip based generators
 def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
@@ -55,6 +71,21 @@ def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
 // NB: FIRRTL dependency is unmanaged (and dropped in sim/lib)
 lazy val chisel  = (project in rocketChipDir / "chisel3")
 
+lazy val treadle = freshProject("treadle", file("tools/treadle"))
+  .settings(commonSettings)
+
+lazy val `chisel-testers` = freshProject("chisel-testers", file("./tools/chisel-testers"))
+  .dependsOn(treadle, chisel)
+  .settings(
+      commonSettings,
+      libraryDependencies ++= Seq(
+        "junit" % "junit" % "4.12",
+        "org.scalatest" %% "scalatest" % "3.0.5",
+        "org.scalacheck" %% "scalacheck" % "1.14.0",
+        "com.github.scopt" %% "scopt" % "3.7.0"
+      )
+    )
+
  // Contains annotations & firrtl passes you may wish to use in rocket-chip without
 // introducing a circular dependency between RC and MIDAS
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
@@ -66,14 +97,8 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
 lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(commonSettings)
 
-// HACK: I'm strugging to override settings in rocket-chip's build.sbt (i want
+lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-// the subproject to register a new library dependendency on midas's targetutils library)
+  .settings(commonSettings)
-// So instead, avoid the existing build.sbt altogether and specify the project's root at src/
-lazy val rocketchip = (project in rocketChipDir / "src")
-  .settings(
-    commonSettings,
-    scalaSource in Compile := baseDirectory.value / "main" / "scala",
-    resourceDirectory in Compile := baseDirectory.value / "main" / "resources")
   .dependsOn(chisel, hardfloat, rocketMacros)
 
 lazy val testchipip = (project in file("generators/testchipip"))
@@ -110,6 +135,22 @@ lazy val barstoolsMacros = (project in file("./tools/barstools/macros/"))
   .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
+lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
+  .dependsOn(chisel, `chisel-testers`)
+  .settings(
+      commonSettings,
+      libraryDependencies ++= Seq(
+        "org.typelevel" %% "spire" % "0.14.1",
+        "org.scalanlp" %% "breeze" % "0.13.2",
+        "junit" % "junit" % "4.12" % "test",
+        "org.scalatest" %% "scalatest" % "3.0.5" % "test",
+        "org.scalacheck" %% "scalacheck" % "1.14.0" % "test"
+  ))
+
+lazy val `rocket-dsptools` = (project in file("./tools/dsptools/rocket"))
+  .dependsOn(rocketchip, dsptools)
+  .settings(commonSettings)
+
 lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
   .dependsOn(rocketchip)
   .settings(commonSettings)

docs/Tools/Chisel-Testers.rst

@@ -0,0 +1,6 @@
+Chisel Testers
+==============================
+
+`Chisel testers <https://github.com/freechipsproject/chisel-testers>`__ is a library for writing tests for Chisel designs.
+It provides a Scala API for interacting with a DUT.
+It can use multiple backends, including :ref:`Treadle` and Verilator.

docs/Tools/Dsptools.rst

@@ -0,0 +1,15 @@
+Dsptools
+===============================
+
+`Dsptools <https://github.com/ucb-bar/dsptools/>`__ is a Chisel library for writing custom signal processing hardware.
+Additionally, dsptools is useful for integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
+
+Some features:
+
+* Complex type
+* Typeclasses for writing polymorphic hardware generators
+  * For example, write one FIR filter generator that works for real or complex inputs
+* Extensions to Chisel testers for fixed point and floating point types
+* A diplomatic implementation of AXI4-Stream
+* Models for verifying APB, AXI-4, and TileLink interfaces with chisel-testers
+* DSP building blocks

docs/Tools/Treadle.rst

@@ -0,0 +1,5 @@
+Treadle
+==============================
+
+`Treadle <https://github.com/freechipsproject/treadle>`__ is a circuit simulator that directly executes FIRRTL.
+It is especially useful for interactive debugging and small unit tests that benefit from a low-overhead simulator.

docs/Tools/index.rst

@@ -10,5 +10,8 @@ The following pages will introduce them, and how we can use them in order to gen
 
    Chisel
    FIRRTL
+   Treadle
+   Chisel-Testers
+   Dsptools
    Barstools