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Fix TSIBridge loadmem param

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This commit is contained in:
Jerry Zhao
2023-10-11 15:01:39 -07:00
parent 894ee63061
commit 3cbcf6b6e8
1 changed files with 7 additions and 2 deletions
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9
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -72,8 +72,13 @@ class WithTSIBridgeAndHarnessRAMOverSerialTL extends HarnessBinder({
val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty)) val ram = LazyModule(new SerialRAM(port.serdesser)(Parameters.empty))
Module(ram.module) Module(ram.module)
ram.module.io.ser <> port.io.bits ram.module.io.ser <> port.io.bits
TSIBridge(th.harnessBinderClock, ram.module.io.tsi,
port.params.serialTLManagerParams.map(_ => MainMemoryConsts.globalName(th.p(MultiChipIdx))), th.harnessBinderReset.asBool)(th.p) // This assumes that:
// If ExtMem for the target is defined, then FASED bridge will be attached
// If FASED bridge is attached, loadmem widget is present
val hasMainMemory = th.chipParameters(th.p(MultiChipIdx))(ExtMem).isDefined
val mainMemoryName = Option.when(hasMainMemory)(MainMemoryConsts.globalName(th.p(MultiChipIdx)))
TSIBridge(th.harnessBinderClock, ram.module.io.tsi, mainMemoryName, th.harnessBinderReset.asBool)(th.p)
} }
}) })