diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 11bf9c4f..612b7ae6 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -214,40 +214,7 @@ class LBWIFRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) -//// DEBUG: To check if UART works (with everything default but serdes slow and ramp up to 1GHz) -//class DebugOffchipConfig extends Config( -// new testchipip.WithSerialTLWidth(64) ++ -// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // SerDes <-async-> mbus. Remember SerDes master tied to fbus -// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast -// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ // controls SerDes freq. -// -// new chipyard.config.WithPeripheryBusFrequencyAsDefault ++ // everything default to 3.2GHz -// new chipyard.config.WithPeripheryBusFrequency(3200) ++ -// new chipyard.config.WithMemoryBusFrequency(3200) ++ -// -// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores -// new chipyard.config.AbstractOffChipConfig) // new offchip network where AXI is in harness -// -//// have pbus=3.2GHz,/1, but others are different (fbus=/4, other=/2) -//class DebugOffchip2Config extends Config( -// new chipyard.config.WithCbusToPbusCrossingType(RationalCrossing(SlowToFast)) ++ -// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ -// -// new chipyard.config.WithSystemBusFrequencyAsDefault ++ -// new chipyard.config.WithSystemBusFrequency(3200 / 2) ++ -// -// new chipyard.config.WithFrontBusFrequency(3200 / 4) ++ -// new chipyard.config.WithPeripheryBusFrequency(3200) ++ -// new chipyard.config.WithMemoryBusFrequency(3200) ++ -// -// new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ // fbus slow -> sbus fast -// new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS -// -// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add 1 rocket cores -// new chipyard.config.AbstractOffChipConfig) - -// fbus=/2, other=/1 -class DebugOffchip3Config extends Config( +class MulticlockAXIOverSerialConfig extends Config( new chipyard.config.WithFbusToSbusCrossingType(RationalCrossing(SlowToFast)) ++ new chipyard.config.WithSystemBusFrequencyAsDefault ++ @@ -262,8 +229,10 @@ class DebugOffchip3Config extends Config( new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled new chipyard.iobinders.WithSerialTLAndPassthroughClockPunchthrough ++ // add new clock for axi domain over serdes and passthrough ios - //new testchipip.WithAXIDomainFreq(1000.0) ++ // set offchip axi domain clock freq (match FireSim DRAM) new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory + new testchipip.WithBlockDeviceLocations( + freechips.rocketchip.subsystem.PBUS, + freechips.rocketchip.subsystem.PBUS) ++ // put block device fully on PBUS to avoid clock crossings new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new chipyard.config.AbstractConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 58c28de1..a7626f32 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -204,6 +204,14 @@ class FireSimMulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore new FireSimRocketConfig) +class FireSimMulticlockAXIOverSerialConfig extends Config( + new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking + new chipyard.MulticlockAXIOverSerialConfig +) + //********************************************************************************** // System with 16 LargeBOOMs that can be simulated with Golden Gate optimizations // - Requires MTModels and MCRams mixins as prefixes to the platform config @@ -216,34 +224,3 @@ class FireSim16LargeBoomConfig extends Config( new boom.common.WithNLargeBooms(16) ++ new chipyard.config.AbstractConfig) -// unsure if this needs to scale -//new chipyard.config.WithUART((pbusFreqMHz / 100) * BigInt(115200L)) ++ - -//class FireSimDebugOffchipConfig extends Config( -// new WithTracerV ++ -// new WithOffchipAXINoClksSetup(3200) ++ -// new chipyard.DebugOffchipConfig -//) - -//class FireSimDebugOffchip2Config extends Config( -// new WithTracerV ++ -// new WithOffchipAXINoClksSetup(3200) ++ -// new chipyard.DebugOffchip2Config -//) - -class FireSimDebugOffchip2Config extends Config( - new chipyard.config.WithUART((4000 / 100) * BigInt(115200L)) ++ - new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial - new WithDefaultFireSimBridges ++ - new WithDefaultMemModel ++ - new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking - new chipyard.DebugOffchip3Config -) - -class FireSimDebugOffchip3Config extends Config( - new WithAXIOverSerialTLCombinedBridges ++ // use combined bridge to connect to axi mem over serial - new WithDefaultFireSimBridges ++ - new WithDefaultMemModel ++ - new WithFireSimConfigTweaksWithoutClocking ++ // don't inherit firesim clocking - new chipyard.DebugOffchip3Config -) diff --git a/generators/testchipip b/generators/testchipip index b66dd655..531ffb70 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b66dd655a3605ff0b3327b133513e27b590d926e +Subproject commit 531ffb7020ef012c5d9dd8642df515d2fbadd7a8