From 9e7fcc0f4e36fa64cfad35fa6c4b81466b6bc0dd Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 30 Nov 2023 10:12:52 -0800 Subject: [PATCH 1/7] Add HasHarnessInstantiators into MultiHarnessBinder --- .../main/scala/harness/MultiHarnessBinders.scala | 16 ++++++++-------- .../src/main/scala/harness/package.scala | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index 1200208c..c4e96a3e 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -24,18 +24,18 @@ object ApplyMultiHarnessBinders { Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) { (chips(i), chips(j)) match { case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f => - f(l0.ports, l1.ports) + f(th, l0.ports, l1.ports) } } }} } } -class MultiHarnessBinder[T <: Port[_]]( +class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators]( chip0: Int, chip1: Int, chip0portFn: T => Boolean, chip1portFn: T => Boolean, - connectFn: (T, T) => Unit -)(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + connectFn: (S, T, T) => Unit +)(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => { // Override any HarnessBinders for chip0/chip1 case MultiChipParameters(`chip0`) => new Config( new HarnessBinder({case (th, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0)) @@ -45,21 +45,21 @@ class MultiHarnessBinder[T <: Port[_]]( ) // Set the multiharnessbinder key case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ { - ((chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => { + ((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => { val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p } val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p } require(chip0Port.size == 1 && chip1Port.size == 1) - connectFn(chip0Port(0), chip1Port(0)) + connectFn(th, chip0Port(0), chip1Port(0)) }) } }) -class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder[SerialTLPort]( +class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder( chip0, chip1, (p0: SerialTLPort) => p0.portId == chip0portId, (p1: SerialTLPort) => p1.portId == chip1portId, - (p0: SerialTLPort, p1: SerialTLPort) => { + (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => { (DataMirror.directionOf(p0.io.clock), DataMirror.directionOf(p1.io.clock)) match { case (Direction.Input, Direction.Output) => p0.io.clock := p1.io.clock case (Direction.Output, Direction.Input) => p1.io.clock := p0.io.clock diff --git a/generators/chipyard/src/main/scala/harness/package.scala b/generators/chipyard/src/main/scala/harness/package.scala index 258655a7..7586e8c6 100644 --- a/generators/chipyard/src/main/scala/harness/package.scala +++ b/generators/chipyard/src/main/scala/harness/package.scala @@ -7,5 +7,5 @@ package object harness { import chipyard.iobinders.Port type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit] - type MultiHarnessBinderFunction = (Seq[Port[_]], Seq[Port[_]]) => Unit + type MultiHarnessBinderFunction = (HasHarnessInstantiator, Seq[Port[_]], Seq[Port[_]]) => Unit } From 53b33d56d4ee6240b63bc94c760b17cc2e5cf5ad Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 30 Nov 2023 10:32:12 -0800 Subject: [PATCH 2/7] Update generators/chipyard/src/main/scala/harness/package.scala --- generators/chipyard/src/main/scala/harness/package.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/package.scala b/generators/chipyard/src/main/scala/harness/package.scala index 7586e8c6..d0366c55 100644 --- a/generators/chipyard/src/main/scala/harness/package.scala +++ b/generators/chipyard/src/main/scala/harness/package.scala @@ -7,5 +7,5 @@ package object harness { import chipyard.iobinders.Port type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit] - type MultiHarnessBinderFunction = (HasHarnessInstantiator, Seq[Port[_]], Seq[Port[_]]) => Unit + type MultiHarnessBinderFunction = (HasHarnessInstantiators, Seq[Port[_]], Seq[Port[_]]) => Unit } From ab1b77f3a44e74f76265021a76d3738f0dfc4583 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 30 Nov 2023 10:33:26 -0800 Subject: [PATCH 3/7] Update generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala --- .../chipyard/src/main/scala/harness/MultiHarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index c4e96a3e..f60ec418 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -38,7 +38,7 @@ class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators]( )(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => { // Override any HarnessBinders for chip0/chip1 case MultiChipParameters(`chip0`) => new Config( - new HarnessBinder({case (th, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0)) + new HarnessBinder({case (th: S, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0)) ) case MultiChipParameters(`chip1`) => new Config( new HarnessBinder({case (th, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1)) From ebf0c7452700fb4fa232dfe7e5677e95aa8b5476 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 30 Nov 2023 10:33:44 -0800 Subject: [PATCH 4/7] Update generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala --- .../chipyard/src/main/scala/harness/MultiHarnessBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala index f60ec418..d3371dfd 100644 --- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala @@ -41,7 +41,7 @@ class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators]( new HarnessBinder({case (th: S, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0)) ) case MultiChipParameters(`chip1`) => new Config( - new HarnessBinder({case (th, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1)) + new HarnessBinder({case (th: S, port: T) if chip1portFn(port) => }) ++ up(MultiChipParameters(chip1)) ) // Set the multiharnessbinder key case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ { From 10e3192404abfcde911a49021c3a86b9a9f2b98b Mon Sep 17 00:00:00 2001 From: joey0320 Date: Fri, 1 Dec 2023 15:50:14 -0800 Subject: [PATCH 5/7] fix blkdev test --- tests/blkdev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/blkdev.c b/tests/blkdev.c index 994a341b..b740617c 100644 --- a/tests/blkdev.c +++ b/tests/blkdev.c @@ -59,8 +59,8 @@ void blkdev_write(unsigned long offset, void *addr, size_t nsectors) #define TEST_NSECTORS 4 #define TEST_SIZE (TEST_NSECTORS * BLKDEV_SECTOR_SIZE / sizeof(int)) -unsigned int test_data[TEST_SIZE]; -unsigned int res_data[TEST_SIZE]; +unsigned int test_data[TEST_SIZE] __attribute__ ((aligned (64))); +unsigned int res_data[TEST_SIZE] __attribute__ ((aligned (64))); int main(void) { From e078fcba49eea6a5bfa61c3587130a07fbce1a05 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 01:54:59 -0800 Subject: [PATCH 6/7] REFACTOR: rename arty35t explicitly --- fpga/Makefile | 6 +++--- fpga/src/main/scala/arty/HarnessBinders.scala | 8 ++++---- fpga/src/main/scala/arty/TestHarness.scala | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/fpga/Makefile b/fpga/Makefile index 3d3caf1c..cfe760f4 100644 --- a/fpga/Makefile +++ b/fpga/Makefile @@ -72,11 +72,11 @@ ifeq ($(SUB_PROJECT),nexysvideo) FPGA_BRAND ?= xilinx endif -ifeq ($(SUB_PROJECT),arty) +ifeq ($(SUB_PROJECT),arty35t) # TODO: Fix with Arty SBT_PROJECT ?= fpga_platforms - MODEL ?= ArtyFPGATestHarness - VLOG_MODEL ?= ArtyFPGATestHarness + MODEL ?= Arty35THarness + VLOG_MODEL ?= Arty35THarness MODEL_PACKAGE ?= chipyard.fpga.arty CONFIG ?= TinyRocketArtyConfig CONFIG_PACKAGE ?= chipyard.fpga.arty diff --git a/fpga/src/main/scala/arty/HarnessBinders.scala b/fpga/src/main/scala/arty/HarnessBinders.scala index 5cef5f80..d2ce5489 100644 --- a/fpga/src/main/scala/arty/HarnessBinders.scala +++ b/fpga/src/main/scala/arty/HarnessBinders.scala @@ -15,19 +15,19 @@ import chipyard.harness.{HarnessBinder} import chipyard.iobinders._ class WithArtyDebugResetHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: DebugResetPort) => { + case (th: Arty35THarness, port: DebugResetPort) => { th.dut_ndreset := port.io // Debug module reset } }) class WithArtyJTAGResetHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: JTAGResetPort) => { + case (th: Arty35THarness, port: JTAGResetPort) => { port.io := PowerOnResetFPGAOnly(th.clock_32MHz) // JTAG module reset } }) class WithArtyJTAGHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: JTAGPort) => { + case (th: Arty35THarness, port: JTAGPort) => { val jtag_wire = Wire(new JTAGIO) jtag_wire.TDO.data := port.io.TDO jtag_wire.TDO.driven := true.B @@ -62,7 +62,7 @@ class WithArtyJTAGHarnessBinder extends HarnessBinder({ }) class WithArtyUARTHarnessBinder extends HarnessBinder({ - case (th: ArtyFPGATestHarness, port: UARTPort) => { + case (th: Arty35THarness, port: UARTPort) => { withClockAndReset(th.clock_32MHz, th.ck_rst) { IOBUF(th.uart_rxd_out, port.io.txd) port.io.rxd := IOBUF(th.uart_txd_in) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index 0a81740a..cdb1d4e4 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -10,7 +10,7 @@ import sifive.fpgashells.shell.xilinx.artyshell.{ArtyShell} import chipyard.harness.{HasHarnessInstantiators} -class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators { +class Arty35THarness(override implicit val p: Parameters) extends ArtyShell with HasHarnessInstantiators { // Convert harness resets from Bool to Reset type. val hReset = Wire(Reset()) hReset := ~ck_rst From 00c4992842e35e77bc327d152025298a4d24c6a3 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 4 Dec 2023 02:43:49 -0800 Subject: [PATCH 7/7] FIX: update github CI --- .github/scripts/defaults.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh index 5d98ad2b..d4eb7b56 100755 --- a/.github/scripts/defaults.sh +++ b/.github/scripts/defaults.sh @@ -34,7 +34,7 @@ grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipya grouping["group-constellation"]="chipyard-constellation" grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar" -grouping["group-fpga"]="arty arty100t nexysvideo vc707 vcu118" +grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118" # key value store to get the build strings declare -A mapping @@ -79,7 +79,7 @@ mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestCo mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig" mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig" -mapping["arty"]="SUB_PROJECT=arty verilog" +mapping["arty35t"]="SUB_PROJECT=arty35t verilog" mapping["arty100t"]="SUB_PROJECT=arty100t verilog" mapping["nexysvideo"]="SUB_PROJECT=nexysvideo verilog" mapping["vc707"]="SUB_PROJECT=vc707 verilog"