diff --git a/.circleci/config.yml b/.circleci/config.yml index ff691e41..4d849e77 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -341,6 +341,7 @@ jobs: - run: name: Run midasexamples tests command: .circleci/run-midasexamples-tests.sh + no_output_timeout: 20m chipyard-ariane-run-tests: executor: main-env steps: diff --git a/common.mk b/common.mk index b5a5bb07..ddb2a355 100644 --- a/common.mk +++ b/common.mk @@ -16,8 +16,9 @@ include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk ######################################################################################### -# variables to get all *.scala files +# Prerequisite lists ######################################################################################### +# Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) @@ -36,7 +37,7 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) +$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala mkdir -p $(@D) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ @@ -45,7 +46,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" ######################################################################################### diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index fd1a6880..c640e31c 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -56,7 +56,6 @@ Then you could use this new config fragment like the following. class SixCoreConfig extends Config( new WithTSI ++ - new WithNoGPIO ++ new WithBootROM ++ new WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/ariane b/generators/ariane index f4ba64a6..66cbcd01 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit f4ba64a624091600e9d7d40c293b8d5c17f47c56 +Subproject commit 66cbcd0115f8f4e2abb38684532ec945622adcae diff --git a/generators/boom b/generators/boom index 90911dde..d0077cff 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 90911dde1b8730f10c958d172f26f72d718be5ae +Subproject commit d0077cff74140153e314f05f631c5e07b0d694ea diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index e1a047dc..2db12ff7 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -52,14 +52,6 @@ class WithUART extends Config((site, here, up) => { UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) -class WithNoGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Nil -}) - -class WithNoUART extends Config((site, here, up) => { - case PeripheryUARTKey => Nil -}) - class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nL2TLBEntries = entries) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 281c5917..ea0f610b 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -256,8 +256,9 @@ class WithTiedOffDebug extends OverrideIOBinder({ Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ debugPortOpt.foreach { d => - d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.clock }) d.dmactiveAck := DontCare + d.clock := th.clock } Nil } diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 6d99ca6a..222ff77c 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -22,7 +22,6 @@ import freechips.rocketchip.util.{DontTouch} * Base top with periphery devices and ports, and a BOOM + Rocket subsystem */ class System(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology with HasAsyncExtInterrupts with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index e0cb771e..6fb2ef00 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -15,7 +15,6 @@ class ArianeConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) @@ -23,6 +22,7 @@ class ArianeConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new ariane.WithNArianeCores(1) ++ // single Ariane core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class dmiArianeConfig extends Config( @@ -31,7 +31,6 @@ class dmiArianeConfig extends Config( new chipyard.iobinders.WithSimAXIMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -39,4 +38,5 @@ class dmiArianeConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new ariane.WithNArianeCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 35934eab..48a9126e 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -13,7 +13,6 @@ class SmallBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -23,6 +22,7 @@ class SmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new boom.common.WithSmallBooms ++ // small boom config new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class MediumBoomConfig extends Config( @@ -32,7 +32,6 @@ class MediumBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -42,6 +41,7 @@ class MediumBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( @@ -51,7 +51,6 @@ class LargeBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -61,6 +60,7 @@ class LargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( @@ -70,7 +70,6 @@ class MegaBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -80,6 +79,7 @@ class MegaBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class DualSmallBoomConfig extends Config( @@ -89,7 +89,6 @@ class DualSmallBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -99,6 +98,7 @@ class DualSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithSmallBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class SmallRV32BoomConfig extends Config( @@ -108,7 +108,6 @@ class SmallRV32BoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -120,6 +119,7 @@ class SmallRV32BoomConfig extends Config( new boom.common.WithBoomRV32 ++ // rv32 (32bit) new boom.common.WithSmallBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class HwachaLargeBoomConfig extends Config( @@ -129,7 +129,6 @@ class HwachaLargeBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -140,6 +139,7 @@ class HwachaLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class LoopbackNICLargeBoomConfig extends Config( @@ -151,7 +151,6 @@ class LoopbackNICLargeBoomConfig extends Config( new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback new testchipip.WithTSI ++ new icenet.WithIceNIC ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -161,5 +160,6 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index af2145e7..4388ca2b 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -13,7 +13,6 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -25,6 +24,7 @@ class LargeBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: BoomAndRocketWithHwacha @@ -35,7 +35,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -48,6 +47,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha @@ -58,7 +58,6 @@ class DualLargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -70,6 +69,7 @@ class DualLargeBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: DualBoomAndRocketOneHwacha @@ -81,7 +81,6 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc @@ -95,6 +94,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocketOneHwacha @@ -107,7 +107,6 @@ class LargeBoomAndRV32RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -120,6 +119,7 @@ class LargeBoomAndRV32RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -131,7 +131,6 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -143,6 +142,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocket @@ -153,7 +153,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithControlCore ++ // add small control core to last hartid @@ -166,5 +165,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e25680ca..ac29c662 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -13,7 +13,6 @@ class RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -22,6 +21,7 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class HwachaRocketConfig extends Config( @@ -31,7 +31,6 @@ class HwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -41,6 +40,7 @@ class HwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GemminiRocketConfig @@ -51,7 +51,6 @@ class GemminiRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -61,6 +60,7 @@ class GemminiRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GemminiRocketConfig @@ -71,7 +71,6 @@ class RoccRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -81,6 +80,7 @@ class RoccRocketConfig extends Config( new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: JtagRocket @@ -91,7 +91,6 @@ class jtagRocketConfig extends Config( new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -101,6 +100,7 @@ class jtagRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: JtagRocket @@ -111,7 +111,6 @@ class dmiRocketConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -120,6 +119,7 @@ class dmiRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DmiRocket @@ -131,7 +131,6 @@ class GCDTLRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithUART ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -141,6 +140,7 @@ class GCDTLRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDTLRocketConfig @@ -153,7 +153,6 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new chipyard.config.WithUART ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink @@ -162,6 +161,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig @@ -174,7 +174,6 @@ class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -183,6 +182,7 @@ class SimBlockDeviceRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( @@ -194,7 +194,6 @@ class BlockDeviceModelRocketConfig extends Config( new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -203,6 +202,7 @@ class BlockDeviceModelRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GPIORocketConfig @@ -223,6 +223,7 @@ class GPIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig @@ -235,13 +236,13 @@ class QuadRocketConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( @@ -251,7 +252,6 @@ class RV32RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -260,6 +260,7 @@ class RV32RocketConfig extends Config( new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class GB1MemoryRocketConfig extends Config( @@ -269,7 +270,6 @@ class GB1MemoryRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -279,6 +279,7 @@ class GB1MemoryRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: Sha3Rocket @@ -289,7 +290,6 @@ class Sha3RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -299,6 +299,7 @@ class Sha3RocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: Sha3Rocket @@ -310,7 +311,6 @@ class InitZeroRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -320,6 +320,7 @@ class InitZeroRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: InitZeroRocketConfig @@ -332,7 +333,6 @@ class LoopbackNICRocketConfig extends Config( new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback new testchipip.WithTSI ++ new icenet.WithIceNIC ++ // add an IceNIC - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -341,6 +341,7 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: scratchpadrocket @@ -351,7 +352,6 @@ class ScratchpadRocketConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new testchipip.WithBackingScratchpad ++ // add backing scratchpad - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -361,6 +361,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket @@ -372,7 +373,6 @@ class RingSystemBusRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -382,5 +382,6 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index fefa271d..2a31293f 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -8,6 +8,7 @@ class TraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( @@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( @@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( @@ -31,6 +34,7 @@ class NonBlockingTraceGenL2Config extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( @@ -40,4 +44,5 @@ class NonBlockingTraceGenL2RingConfig extends Config( new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 0c74b581..c11d103d 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -29,7 +29,6 @@ class TutorialStarterConfig extends Config( // Config fragments below this line affect hardware generation // of the Top new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core - new chipyard.config.WithNoGPIO ++ // Disable GPIOs. new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op new chipyard.config.WithUART ++ // Add a UART @@ -51,6 +50,7 @@ class TutorialStarterConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 // BaseConfig configures "bare" rocketchip system new freechips.rocketchip.system.BaseConfig ) @@ -65,7 +65,6 @@ class TutorialMMIOConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -81,6 +80,7 @@ class TutorialMMIOConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) @@ -93,7 +93,6 @@ class TutorialSha3Config extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -107,6 +106,7 @@ class TutorialSha3Config extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) @@ -119,7 +119,6 @@ class TutorialSha3BlackBoxConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -134,5 +133,6 @@ class TutorialSha3BlackBoxConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index a24afd43..4e429618 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -10,27 +10,27 @@ import firrtl.stage.FirrtlCli import freechips.rocketchip.stage.RocketChipCli import freechips.rocketchip.system.RocketChipStage -import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper class ChipyardStage extends ChiselStage with PreservesAll[Phase] { override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( - classOf[freechips.rocketchip.stage.phases.Checks], - classOf[freechips.rocketchip.stage.phases.TransformAnnotations], - classOf[freechips.rocketchip.stage.phases.PreElaboration], - classOf[chisel3.stage.phases.Checks], - classOf[chisel3.stage.phases.Elaborate], - classOf[freechips.rocketchip.stage.phases.GenerateROMs], - classOf[chisel3.stage.phases.AddImplicitOutputFile], - classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile], - classOf[chisel3.stage.phases.MaybeAspectPhase], - classOf[chisel3.stage.phases.Emitter], - classOf[chisel3.stage.phases.Convert], - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags], - classOf[freechips.rocketchip.stage.phases.GenerateArtefacts], + Dependency[freechips.rocketchip.stage.phases.Checks], + Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], + Dependency[freechips.rocketchip.stage.phases.PreElaboration], + Dependency[chisel3.stage.phases.Checks], + Dependency[chisel3.stage.phases.Elaborate], + Dependency[freechips.rocketchip.stage.phases.GenerateROMs], + Dependency[chisel3.stage.phases.AddImplicitOutputFile], + Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + Dependency[chisel3.stage.phases.MaybeAspectPhase], + Dependency[chisel3.stage.phases.Emitter], + Dependency[chisel3.stage.phases.Convert], + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], + Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], ) } diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 277d04b5..fce5d432 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -10,7 +10,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll} +import firrtl.options.{Phase, PreservesAll, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -23,9 +23,9 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests]) - override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) + override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index 76f99ab7..0ed5ec11 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -7,7 +7,7 @@ import scala.collection.mutable import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable} +import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -24,8 +24,8 @@ case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotat class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Our annotations tend not to be serializable, but are not marked as such. - override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[chipyard.stage.phases.AddDefaultTests]) + override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[chipyard.stage.phases.AddDefaultTests]) override def transform(annotations: AnnotationSeq): AnnotationSeq = { val targetDir = view[StageOptions](annotations).targetDir diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index c5af5cda..cf2358d9 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -141,9 +141,9 @@ class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimL class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { - runSuite("verilator")(NICLoopbackTests) -} +//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { +// runSuite("verilator")(NICLoopbackTests) +//} // Disabled until RAM optimizations re-enabled in multiclock //class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") //class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") diff --git a/generators/rocket-chip b/generators/rocket-chip index 9b1907ea..1872f5d5 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 9b1907eacbeb268d47e204e3de1818823d605ba4 +Subproject commit 1872f5d501221f13950aa2293939634a1e0d1735 diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 3e35a94d..c1dee823 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 3e35a94d46d88506d5b14b2c34f05b8651844452 +Subproject commit c1dee8234c23c8fc454108e59ecba20987f95cde diff --git a/generators/sifive-cache b/generators/sifive-cache index d3d95ece..4ebefa3e 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d3d95ece5a570b423892bede4fed6cb0030c7701 +Subproject commit 4ebefa3e30ec44bd2f4ff82747025fb7b362b954 diff --git a/generators/testchipip b/generators/testchipip index cec2c0b6..5b3f2c96 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cec2c0b6d66c3df05d08462167bb8a58c0912d06 +Subproject commit 5b3f2c9654d4cb06a64e8ac5df864c706a07bda8 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index cb5d0af8..1653ba79 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -41,7 +41,6 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp { class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem with HasTraceGenTiles - with HasHierarchicalBusTopology with CanHaveMasterAXI4MemPort { override lazy val module = new TraceGenSystemModuleImp(this) } diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 0e86b836..acec6005 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -283,7 +283,7 @@ done_processing: bool dump; // reset for several cycles to handle pipelined reset - for (int i = 0; i < 10; i++) { + for (int i = 0; i < 100; i++) { tile->reset = 1; tile->clock = 0; tile->eval(); diff --git a/sims/firesim b/sims/firesim index d5d4f4d6..6482be6d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit d5d4f4d6f8cf5a499fee5365eec9eec794bbd08c +Subproject commit 6482be6d2e435392815f5e24631b5644787e3467 diff --git a/tools/barstools b/tools/barstools index e230e8cf..c4e5f66c 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e230e8cf3f7c0bc3c958cab22c5d90d195ca6b01 +Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 diff --git a/tools/chisel3 b/tools/chisel3 index 7a343dce..21ea734d 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit 7a343dce95a370f6cb7b9cf80e0694ac82dc94f8 +Subproject commit 21ea734d809395962a8d3195a76377f6e44308f3 diff --git a/tools/firrtl b/tools/firrtl index eb637777..7c6f58d9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit eb637777e3c4d77435cfd13358c521ed1b766ba8 +Subproject commit 7c6f58d986e67b3d0662a4cd6654a68f9cc52cf9 diff --git a/tools/treadle b/tools/treadle index a03b969a..1c67bc84 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit a03b969af104770a7662ecdbac80cebf622e674b +Subproject commit 1c67bc846aafc3bdd707f76ead8cefd5f93e0376