From e3b30dbd83f5b3497c2b0aeb20e75d80b91a0a38 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 1 Nov 2019 17:17:57 -0700 Subject: [PATCH 001/139] [FireChip] Use clock in BridgeBinders --- generators/firechip/src/main/scala/BridgeBinders.scala | 10 +++++----- generators/firechip/src/main/scala/TargetMixins.scala | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 95133561..a1410212 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -32,19 +32,19 @@ class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryD }) class WithSerialBridge extends RegisterBridgeBinder({ - case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) + case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.clock, target.serial)(target.p)) }) class WithNICBridge extends RegisterBridgeBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.clock, target.net)(target.p)) }) class WithUARTBridge extends RegisterBridgeBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(target.clock, u)(target.p)) }) class WithBlockDeviceBridge extends RegisterBridgeBinder({ - case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.clock ,target.bdev, target.reset.toBool)(target.p)) }) class WithFASEDBridge extends RegisterBridgeBinder({ @@ -55,7 +55,7 @@ class WithFASEDBridge extends RegisterBridgeBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDBridge(axi4Bundle, t.reset.toBool, + FASEDBridge(t.clock, axi4Bundle, t.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index c3982d95..b96a6606 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -41,6 +41,7 @@ trait HasTraceIOImp extends LazyModuleImp { (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => port := DeclockedTracedInstruction.fromVec(tileTrace) }) + traceIO.clock := clock // Enabled to test TracerV trace capture if (p(PrintTracePort)) { From 12485b8e5cabe8c564bf7f005bd94efc1ee1a4d3 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 20 Nov 2019 13:31:11 -0800 Subject: [PATCH 002/139] [firesim] Update TraceGen BridgeBinder --- generators/firechip/src/main/scala/BridgeBinders.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index a1410212..a6e6791a 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -67,7 +67,7 @@ class WithTracerVBridge extends RegisterBridgeBinder({ class WithTraceGenBridge extends RegisterBridgeBinder({ case target: HasTraceGenTilesModuleImp => - Seq(GroundTestBridge(target.success)(target.p)) + Seq(GroundTestBridge(target.clock, target.success)(target.p)) }) // Shorthand to register all of the provided bridges above From bcddd6e0f66c26f0fed18bb7f80b89384c5bca1f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 22 Nov 2019 16:29:55 -0800 Subject: [PATCH 003/139] [Firechip] Add support for Tile <-> Uncore rational division --- .../example/src/main/scala/ConfigMixins.scala | 1 + .../src/main/scala/TargetConfigs.scala | 18 ++++++++++++++++-- .../firechip/src/main/scala/TargetMixins.scala | 13 +++++++++++++ .../firechip/src/main/scala/Targets.scala | 2 ++ .../src/test/scala/ScalaTestSuite.scala | 3 +++ 5 files changed, 35 insertions(+), 2 deletions(-) diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/example/src/main/scala/ConfigMixins.scala index 7d7e74af..dc9eed36 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/example/src/main/scala/ConfigMixins.scala @@ -182,3 +182,4 @@ class WithInitZeroTop extends Config((site, here, up) => { Module(LazyModule(new TopWithInitZero()(p)).module) }) // DOC include end: WithInitZero + diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 37df3799..f7b70322 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -11,7 +11,8 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.DebugModuleParams -import boom.common.BoomTilesKey +import freechips.rocketchip.diplomacy.{RationalCrossing} +import boom.common.{BoomCrossingKey, BoomTilesKey} import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} @@ -19,7 +20,7 @@ import tracegen.TraceGenKey import icenet._ import firesim.bridges._ -import firesim.util.{WithNumNodes} +import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters} import firesim.configs._ class WithBootROM extends Config((site, here, up) => { @@ -320,3 +321,16 @@ class FireSimTraceGenL2Config extends Config( outerLatencyCycles = 50) ++ new WithTraceGenBridge ++ new FireSimRocketChipConfig) + + +class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(multiplier -> divisor)) + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } + case BoomCrossingKey => up(BoomCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } +}) + +class HalfRateUncore extends WithRationalTiles(2,1) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index b96a6606..6320038a 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.tile.RocketTile import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation @@ -73,3 +74,15 @@ trait CanHaveMultiCycleRegfileImp { } } +trait HasFireSimClockingImp extends HasAdditionalClocks { + val outer: HasTiles + val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { + case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case None => (clocks(0), reset) + } + + outer.tiles.foreach({ case tile => + tile.module.clock := tileClock + tile.module.reset := tileReset + }) +} diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 4c790195..3a73b0d9 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -60,6 +60,7 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l) with HasPeripheryIceNICModuleImpValidOnly with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with HasFireSimClockingImp with CanHaveMultiCycleRegfileImp class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) @@ -84,6 +85,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with HasFireSimClockingImp with CanHaveMultiCycleRegfileImp class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index f4f55cd9..74af7fcb 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -139,6 +139,9 @@ class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_Fir class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams") +// Multiclock tests +class RocketMulticlockF1Tests extends FireSimTestSuite("FireSimNoNIC", "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") + abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs From 38834a99e143f2281df0f52a677b28b167be293a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 9 Jan 2020 16:51:27 -0800 Subject: [PATCH 004/139] [firesim] Update the multiclock test --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 74af7fcb..a2f39523 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -140,7 +140,10 @@ class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRoc class RamModelBoomF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams") // Multiclock tests -class RocketMulticlockF1Tests extends FireSimTestSuite("FireSimNoNIC", "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") +class RocketMulticlockF1Tests extends FireSimTestSuite( + "FireSimNoNIC", + "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", + "WithSynthAsserts_BaseF1Config") abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { From 524299bd39e1ecedccb62abdfbfc9ed41f15b1d4 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 9 Jan 2020 16:52:02 -0800 Subject: [PATCH 005/139] [firechip] Commit some Eagle X-related mock configs --- .../firechip/src/main/scala/TargetConfigs.scala | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index f7b70322..d8350626 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -334,3 +334,16 @@ class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, her }) class HalfRateUncore extends WithRationalTiles(2,1) + +// Eagle X Mock Configs +class EagleMockConfig(numCores: Int) extends Config( + new WithBootROM ++ + new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks = 16, capacityKB = 8192) ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new WithNBigCores(numCores) ++ + new FireSimRocketChipConfig) + +class EX20C extends EagleMockConfig(20) +class EX16C extends EagleMockConfig(16) +class EX12C extends EagleMockConfig(12) +class EX8C extends EagleMockConfig(8) From 3fbc074b0191382c900becb7a66c76c9d7524b4f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 17 Jan 2020 17:56:37 -0800 Subject: [PATCH 006/139] [firechip] Instantiate multiple TracerV bridges --- .../src/main/scala/BridgeBinders.scala | 4 +-- .../src/main/scala/TargetMixins.scala | 35 +++++++++---------- .../src/test/scala/ScalaTestSuite.scala | 15 ++++---- 3 files changed, 27 insertions(+), 27 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index a6e6791a..6406d6c6 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -61,9 +61,7 @@ class WithFASEDBridge extends RegisterBridgeBinder({ }).toSeq }) -class WithTracerVBridge extends RegisterBridgeBinder({ - case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) -}) +class WithTracerVBridge extends Config((_,_,_) => { case InstantiateTracerVBridges => true }) class WithTraceGenBridge extends RegisterBridgeBinder({ case target: HasTraceGenTilesModuleImp => diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 6320038a..50d51269 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile.RocketTile import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction -import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.bridges.{TracerVBridge} import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation @@ -22,34 +22,33 @@ import boom.common.BoomTile /* Wires out tile trace ports to the top; and wraps them in a Bundle that the * TracerV bridge can match on. */ -object PrintTracePort extends Field[Boolean](false) +case object PrintTracePort extends Field[Boolean](false) +case object InstantiateTracerVBridges extends Field[Boolean](false) trait HasTraceIO { this: HasTiles => val module: HasTraceIOImp // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp - val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]] - val tileTraceNodes = tiles.map(tile => tile.traceNode) - tileTraceNodes foreach { traceNexus := _ } + val tileTraceNodes = tiles.map({ tile => + val node = BundleBridgeSink[Vec[TracedInstruction]] + node := tile.traceNode + node + }) } trait HasTraceIOImp extends LazyModuleImp { val outer: HasTraceIO - - val traceIO = IO(Output(new TraceOutputTop( - DeclockedTracedInstruction.fromNode(outer.traceNexus.in)))) - (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => - port := DeclockedTracedInstruction.fromVec(tileTrace) + outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) => + if (p(InstantiateTracerVBridges)) { + val b = TracerVBridge(node.bundle) + if (p(PrintTracePort)) { + val traceprint = WireDefault(0.U(512.W)) + traceprint := b.io.traces.asUInt + printf(s"TRACEPORT ${idx}: %x\n", traceprint) + } + } }) - traceIO.clock := clock - - // Enabled to test TracerV trace capture - if (p(PrintTracePort)) { - val traceprint = Wire(UInt(512.W)) - traceprint := Cat(traceIO.traces.map(_.asUInt)) - printf("TRACEPORT: %x\n", traceprint) - } } trait CanHaveMultiCycleRegfileImp { diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index a2f39523..7f505ab1 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -106,14 +106,17 @@ abstract class FireSimTestSuite( def diffTracelog(verilatedLog: String) { behavior of "captured instruction trace" it should s"match the chisel printf in ${verilatedLog}" in { - def getLines(file: File, dropLines: Int = 0): Seq[String] = { + def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = { val lines = Source.fromFile(file).getLines.toList - lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) + lines.filter(_.startsWith(prefixFilter)) + .drop(dropLines) + .map(_.stripPrefix(prefixFilter)) } val resetLength = 51 - val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) - assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length") + val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ") + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength) + assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, + s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { assert(vPrint == sPrint) @@ -125,7 +128,7 @@ abstract class FireSimTestSuite( mkdirs elaborate generateTestSuiteMakefrags - runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0""")) + runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) runSuite("verilator")(FastBlockdevTests) From 924f4403850df60edc533d83140225e161c248bf Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 20 Jan 2020 12:00:23 -0800 Subject: [PATCH 007/139] [Firechip] Include reset in tracerv tokens --- .../src/main/scala/TargetMixins.scala | 9 ++++++--- .../src/test/scala/ScalaTestSuite.scala | 19 ++++++++++--------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 50d51269..d7714527 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -42,10 +42,13 @@ trait HasTraceIOImp extends LazyModuleImp { outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) => if (p(InstantiateTracerVBridges)) { val b = TracerVBridge(node.bundle) + // Used for verifying the TracerV bridge if (p(PrintTracePort)) { - val traceprint = WireDefault(0.U(512.W)) - traceprint := b.io.traces.asUInt - printf(s"TRACEPORT ${idx}: %x\n", traceprint) + withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) { + val traceprint = WireDefault(0.U(512.W)) + traceprint := b.io.traces.asUInt + printf(s"TRACEPORT ${idx}: %x\n", traceprint) + } } } }) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 7f505ab1..9a8da363 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -106,15 +106,16 @@ abstract class FireSimTestSuite( def diffTracelog(verilatedLog: String) { behavior of "captured instruction trace" it should s"match the chisel printf in ${verilatedLog}" in { - def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = { - val lines = Source.fromFile(file).getLines.toList - lines.filter(_.startsWith(prefixFilter)) - .drop(dropLines) - .map(_.stripPrefix(prefixFilter)) - } - val resetLength = 51 - val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ") - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength) + def getLines(file: File): Seq[String] = Source.fromFile(file).getLines.toList + + val printfPrefix = "TRACEPORT 0: " + val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")).collect({ + case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) }) + + // Last bit indicates the core was under reset; reject those tokens + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).filter(line => + (line.last.toInt & 1) == 0) + assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}") assert(verilatedOutput.nonEmpty) From b47e692b4b06905494368c509495921ab416e191 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 20 Jan 2020 12:55:47 -0800 Subject: [PATCH 008/139] [TracerV] Drop the first token in comparison tests --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 9a8da363..14146ba5 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -113,7 +113,8 @@ abstract class FireSimTestSuite( case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) }) // Last bit indicates the core was under reset; reject those tokens - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).filter(line => + // Tail to drop the first token which is initialized in the channel + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).tail.filter(line => (line.last.toInt & 1) == 0) assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, From e45c83f810105e8596cc93cd19adef51cfa25e2d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 21 Jan 2020 13:35:29 -0800 Subject: [PATCH 009/139] [Firechip] Make reverse instruction order in trace printf --- generators/firechip/src/main/scala/TargetConfigs.scala | 5 +++++ generators/firechip/src/main/scala/TargetMixins.scala | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d8350626..a3f637d0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -76,6 +76,10 @@ class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { )) }) +class WithBoomEnableTrace extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) +}) + // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleParams => up(DebugModuleParams, site).copy(clockGate = false) @@ -170,6 +174,7 @@ class FireSimBoomConfig extends Config( new WithUARTKey ++ new WithNICKey ++ new WithBlockDevice ++ + new WithBoomEnableTrace ++ new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index d7714527..55761233 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -46,7 +46,8 @@ trait HasTraceIOImp extends LazyModuleImp { if (p(PrintTracePort)) { withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) { val traceprint = WireDefault(0.U(512.W)) - traceprint := b.io.traces.asUInt + // The reverse is here to match the behavior the Cat used in the bridge + traceprint := b.io.traces.reverse.asUInt printf(s"TRACEPORT ${idx}: %x\n", traceprint) } } From 43008adc8e08f596a6a568f6ab601bef35f4e8eb Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 21 Jan 2020 14:28:54 -0800 Subject: [PATCH 010/139] WARNING: Point at a fork of boom @ davidbiancolin --- .gitmodules | 2 +- generators/boom | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 282dc731..0240e78c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -18,7 +18,7 @@ url = https://github.com/ucb-bar/riscv-torture.git [submodule "generators/boom"] path = generators/boom - url = https://github.com/riscv-boom/riscv-boom.git + url = https://github.com/davidbiancolin/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks url = https://github.com/sifive/sifive-blocks.git diff --git a/generators/boom b/generators/boom index 2a0ea2e7..84c81dcc 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2a0ea2e7acfd4605eed513e15062848e4e5be309 +Subproject commit 84c81dcc54e87598c6635f08787ad7f133fdd45e From 271211f9b9faaa8c8585d1411e8ea6223bc81738 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 30 Jan 2020 21:49:34 -0800 Subject: [PATCH 011/139] Fix capitalization in docs (#419) --- docs/Customization/RoCC-Accelerators.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Customization/RoCC-Accelerators.rst b/docs/Customization/RoCC-Accelerators.rst index 7a3f4447..2d420177 100644 --- a/docs/Customization/RoCC-Accelerators.rst +++ b/docs/Customization/RoCC-Accelerators.rst @@ -45,7 +45,7 @@ The other interfaces available to the accelerator are ``mem``, which provides ac the ``busy`` signal, which indicates when the accelerator is still handling an instruction; and the ``interrupt`` signal, which can be used to interrupt the CPU. -Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRocc.scala`` for detailed information on the different IOs. +Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala`` for detailed information on the different IOs. Adding RoCC accelerator to Config ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ From 49dbe8daba0c051b8e5dc82ed8758289bff116bb Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 22 Jan 2020 12:38:38 -0800 Subject: [PATCH 012/139] Rename top-level example package to chipyard * FireChip now directly uses the Chipyard Top --- .circleci/config.yml | 105 +++++++----------- .circleci/defaults.sh | 12 +- .circleci/do-rtl-build.sh | 2 +- .circleci/run-tests.sh | 19 ++-- build.sbt | 7 +- .../src/main/resources/vsrc/GCDMMIOBlackBox.v | 0 .../src/main/scala/BoomConfigs.scala | 2 +- .../src/main/scala/ConfigMixins.scala | 2 +- .../src/main/scala/GCD.scala | 2 +- .../src/main/scala/Generator.scala | 4 +- .../src/main/scala/HeteroConfigs.scala | 2 +- .../src/main/scala/InitZero.scala | 2 +- .../src/main/scala/NodeTypes.scala | 2 +- .../src/main/scala/RegisterNodeExample.scala | 0 .../src/main/scala/RocketConfigs.scala | 2 +- .../src/main/scala/Subsystem.scala | 2 +- .../src/main/scala/System.scala | 2 +- .../src/main/scala/TestHarness.scala | 2 +- .../src/main/scala/TestSuites.scala | 2 +- .../src/main/scala/Top.scala | 4 +- .../src/main/scala/TopCakes.scala | 2 +- .../firechip/src/main/scala/Generator.scala | 2 +- .../src/main/scala/TargetConfigs.scala | 2 + .../src/main/scala/TargetMixins.scala | 2 +- .../firechip/src/main/scala/Targets.scala | 44 +------- variables.mk | 6 +- 26 files changed, 82 insertions(+), 151 deletions(-) rename generators/{example => chipyard}/src/main/resources/vsrc/GCDMMIOBlackBox.v (100%) rename generators/{example => chipyard}/src/main/scala/BoomConfigs.scala (99%) rename generators/{example => chipyard}/src/main/scala/ConfigMixins.scala (99%) rename generators/{example => chipyard}/src/main/scala/GCD.scala (99%) rename generators/{example => chipyard}/src/main/scala/Generator.scala (95%) rename generators/{example => chipyard}/src/main/scala/HeteroConfigs.scala (99%) rename generators/{example => chipyard}/src/main/scala/InitZero.scala (99%) rename generators/{example => chipyard}/src/main/scala/NodeTypes.scala (99%) rename generators/{example => chipyard}/src/main/scala/RegisterNodeExample.scala (100%) rename generators/{example => chipyard}/src/main/scala/RocketConfigs.scala (99%) rename generators/{utilities => chipyard}/src/main/scala/Subsystem.scala (99%) rename generators/{utilities => chipyard}/src/main/scala/System.scala (98%) rename generators/{example => chipyard}/src/main/scala/TestHarness.scala (98%) rename generators/{utilities => chipyard}/src/main/scala/TestSuites.scala (99%) rename generators/{example => chipyard}/src/main/scala/Top.scala (96%) rename generators/{example => chipyard}/src/main/scala/TopCakes.scala (97%) diff --git a/.circleci/config.yml b/.circleci/config.yml index 8a1fdb48..ad5671b1 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -188,105 +188,76 @@ jobs: key: extra-tests-{{ .Branch }}-{{ .Revision }} paths: - "/home/riscvuser/project/tests" - prepare-example: + prepare-chipyard-rocket: executor: main-env steps: - prepare-rtl: - project-key: "example" - prepare-boomrocketexample: + project-key: "chipyard-rocket" + prepare-chipyard-hetero: executor: main-env steps: - prepare-rtl: - project-key: "boomrocketexample" + project-key: "chipyard-hetero" timeout: "240m" - prepare-boom: + prepare-chipyard-boom: executor: main-env steps: - prepare-rtl: - project-key: "boom" + project-key: "chipyard-boom" prepare-rocketchip: executor: main-env steps: - prepare-rtl: project-key: "rocketchip" - prepare-blockdevrocketchip: + prepare-chipyard-blkdev: executor: main-env steps: - prepare-rtl: - project-key: "blockdevrocketchip" - prepare-hwacha: + project-key: "chipyard-blkdev" + prepare-chipyard-hwacha: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "hwacha" - prepare-gemmini: + project-key: "chipyard-hwacha" + prepare-chipyard-gemmini: executor: main-env steps: - prepare-rtl: tools-version: "esp-tools" - project-key: "gemmini" - prepare-tracegen: - executor: main-env - steps: - - prepare-rtl: - project-key: "tracegen" - prepare-tracegen-boom: - executor: main-env - steps: - - prepare-rtl: - project-key: "tracegen-boom" - prepare-firesim: - executor: main-env - steps: - - prepare-rtl: - project-key: "firesim" - build-script: "do-firesim-build.sh" - prepare-fireboom: - executor: main-env - steps: - - prepare-rtl: - project-key: "fireboom" - build-script: "do-firesim-build.sh" - midasexamples-run-tests: - executor: main-env - steps: - - setup-tools-verilator - - run: - name: Run midasexamples tests - command: .circleci/run-midasexamples-tests.sh - example-run-tests: + project-key: "chipyard-gemmini" + chipyard-rocket-run-tests: executor: main-env steps: - run-tests: - project-key: "example" - boomrocketexample-run-tests: + project-key: "chipyard-rocket" + chipyard-hetero-run-tests: executor: main-env steps: - run-tests: - project-key: "boomrocketexample" - boom-run-tests: + project-key: "chipyard-hetero" + chipyard-boom-run-tests: executor: main-env steps: - run-tests: - project-key: "boom" + project-key: "chipyard-boom" rocketchip-run-tests: executor: main-env steps: - run-tests: project-key: "rocketchip" - hwacha-run-tests: + chipyard-hwacha-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" - project-key: "hwacha" - gemmini-run-tests: + project-key: "chipyard-hwacha" + chipyard-gemmini-run-tests: executor: main-env steps: - run-tests: tools-version: "esp-tools" - project-key: "gemmini" + project-key: "chipyard-gemmini" tracegen-run-tests: executor: main-env steps: @@ -346,17 +317,17 @@ workflows: - install-riscv-toolchain # Prepare the verilator builds - - prepare-example: + - prepare-chipyard-rocket: requires: - install-riscv-toolchain - install-verilator - - prepare-boomrocketexample: + - prepare-chipyard-hetero: requires: - install-riscv-toolchain - install-verilator - - prepare-boom: + - prepare-chipyard-boom: requires: - install-riscv-toolchain - install-verilator @@ -366,17 +337,17 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-blockdevrocketchip: + - prepare-chipyard-blkdev: requires: - install-riscv-toolchain - install-verilator - - prepare-hwacha: + - prepare-chipyard-hwacha: requires: - install-esp-toolchain - install-verilator - - prepare-gemmini: + - prepare-chipyard-gemmini: requires: - install-esp-toolchain - install-verilator @@ -410,29 +381,29 @@ workflows: - install-verilator # Run the example tests - - example-run-tests: + - chipyard-rocket-run-tests: requires: - - prepare-example + - prepare-chipyard-rocket - - boomrocketexample-run-tests: + - chipyard-hetero-run-tests: requires: - - prepare-boomrocketexample + - prepare-chipyard-hetero - - boom-run-tests: + - chipyard-boom-run-tests: requires: - - prepare-boom + - prepare-chipyard-boom - rocketchip-run-tests: requires: - prepare-rocketchip - - hwacha-run-tests: + - chipyard-hwacha-run-tests: requires: - - prepare-hwacha + - prepare-chipyard-hwacha - - gemmini-run-tests: + - chipyard-gemmini-run-tests: requires: - - prepare-gemmini + - prepare-chipyard-gemmini - tracegen-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 08c4222c..64ed3138 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -41,13 +41,13 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping -mapping["example"]="SUB_PROJECT=example" -mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=LargeBoomAndRocketConfig" -mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" +mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" +mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" +mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" -mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig" -mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig" -mapping["gemmini"]="SUB_PROJECT=example CONFIG=GemminiRocketConfig" +mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" +mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" +mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]="SUB_PROJECT=tracegen CONFIG=BoomTraceGenConfig" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index dd667dfb..2e6384a2 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -32,7 +32,7 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then +if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib run "mkdir -p $REMOTE_ESP_DIR" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 6d01d182..cc747756 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -29,28 +29,25 @@ run_tracegen () { } case $1 in - example) + chipyard-rocket) run_bmark ${mapping[$1]} ;; - boomexample) + chipyard-boom) run_bmark ${mapping[$1]} ;; - boomrocketexample) - run_bmark ${mapping[$1]} - ;; - boom) + chipyard-hetero) run_bmark ${mapping[$1]} ;; rocketchip) run_bmark ${mapping[$1]} ;; - hwacha) + chipyard-hwacha) export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} ;; - gemmini) + chipyard-gemmini) export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH @@ -58,9 +55,9 @@ case $1 in cd $GEMMINI_SOFTWARE_DIR ./build.sh cd $LOCAL_SIM_DIR - $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - $LOCAL_SIM_DIR/simulator-example-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; tracegen) run_tracegen ${mapping[$1]} diff --git a/build.sbt b/build.sbt index 2fd83c55..539f9307 100644 --- a/build.sbt +++ b/build.sbt @@ -122,7 +122,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) -lazy val example = conditionalDependsOn(project in file("generators/example")) +lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet) .settings(commonSettings) @@ -131,7 +131,6 @@ lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) .settings(commonSettings) lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) - .dependsOn(rocketchip, boom) .settings(commonSettings) lazy val icenet = (project in file("generators/icenet")) @@ -155,7 +154,7 @@ lazy val gemmini = (project in file("generators/gemmini")) .settings(commonSettings) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) - .dependsOn(chisel_testers, example) + .dependsOn(chisel_testers, chipyard) .settings(commonSettings) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) @@ -196,7 +195,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, example, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/example/src/main/resources/vsrc/GCDMMIOBlackBox.v b/generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v similarity index 100% rename from generators/example/src/main/resources/vsrc/GCDMMIOBlackBox.v rename to generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v diff --git a/generators/example/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala similarity index 99% rename from generators/example/src/main/scala/BoomConfigs.scala rename to generators/chipyard/src/main/scala/BoomConfigs.scala index a6a0adb4..9eae1ea0 100644 --- a/generators/example/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/example/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigMixins.scala similarity index 99% rename from generators/example/src/main/scala/ConfigMixins.scala rename to generators/chipyard/src/main/scala/ConfigMixins.scala index acd1001e..f2dfcf2b 100644 --- a/generators/example/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigMixins.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.util.{log2Up} diff --git a/generators/example/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala similarity index 99% rename from generators/example/src/main/scala/GCD.scala rename to generators/chipyard/src/main/scala/GCD.scala index f41e78db..1b66b76c 100644 --- a/generators/example/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.util._ diff --git a/generators/example/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala similarity index 95% rename from generators/example/src/main/scala/Generator.scala rename to generators/chipyard/src/main/scala/Generator.scala index 9beb094c..32619f29 100644 --- a/generators/example/src/main/scala/Generator.scala +++ b/generators/chipyard/src/main/scala/Generator.scala @@ -1,4 +1,4 @@ -package example +package chipyard import scala.util.Try @@ -8,8 +8,6 @@ import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.system.{TestGeneration} -import utilities.{TestSuiteHelper} - object Generator extends GeneratorApp { // add unique test suites override def addTestSuites { diff --git a/generators/example/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala similarity index 99% rename from generators/example/src/main/scala/HeteroConfigs.scala rename to generators/chipyard/src/main/scala/HeteroConfigs.scala index ff3bf338..4bfea32c 100644 --- a/generators/example/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/example/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/InitZero.scala similarity index 99% rename from generators/example/src/main/scala/InitZero.scala rename to generators/chipyard/src/main/scala/InitZero.scala index 4c7f3bbb..2861e0bb 100644 --- a/generators/example/src/main/scala/InitZero.scala +++ b/generators/chipyard/src/main/scala/InitZero.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.util._ diff --git a/generators/example/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/NodeTypes.scala similarity index 99% rename from generators/example/src/main/scala/NodeTypes.scala rename to generators/chipyard/src/main/scala/NodeTypes.scala index 577b9baf..ca55b2ac 100644 --- a/generators/example/src/main/scala/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/NodeTypes.scala @@ -1,4 +1,4 @@ -package example +package chipyard import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ diff --git a/generators/example/src/main/scala/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/RegisterNodeExample.scala similarity index 100% rename from generators/example/src/main/scala/RegisterNodeExample.scala rename to generators/chipyard/src/main/scala/RegisterNodeExample.scala diff --git a/generators/example/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala similarity index 99% rename from generators/example/src/main/scala/RocketConfigs.scala rename to generators/chipyard/src/main/scala/RocketConfigs.scala index 7cc43a4d..dfdadf03 100644 --- a/generators/example/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/utilities/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala similarity index 99% rename from generators/utilities/src/main/scala/Subsystem.scala rename to generators/chipyard/src/main/scala/Subsystem.scala index d5354946..d8635cd5 100644 --- a/generators/utilities/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -3,7 +3,7 @@ // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ -package utilities +package chipyard import chisel3._ import chisel3.internal.sourceinfo.{SourceInfo} diff --git a/generators/utilities/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala similarity index 98% rename from generators/utilities/src/main/scala/System.scala rename to generators/chipyard/src/main/scala/System.scala index 0eed6660..f18a2068 100644 --- a/generators/utilities/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -3,7 +3,7 @@ // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ -package utilities +package chipyard import chisel3._ diff --git a/generators/example/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala similarity index 98% rename from generators/example/src/main/scala/TestHarness.scala rename to generators/chipyard/src/main/scala/TestHarness.scala index 50c872f2..6c01753f 100644 --- a/generators/example/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ import chisel3.experimental._ diff --git a/generators/utilities/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala similarity index 99% rename from generators/utilities/src/main/scala/TestSuites.scala rename to generators/chipyard/src/main/scala/TestSuites.scala index 725e1e69..05c4bf6e 100644 --- a/generators/utilities/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -1,4 +1,4 @@ -package utilities +package chipyard import scala.collection.mutable.{LinkedHashSet} diff --git a/generators/example/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala similarity index 96% rename from generators/example/src/main/scala/Top.scala rename to generators/chipyard/src/main/scala/Top.scala index 47ab1c28..d4382d86 100644 --- a/generators/example/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ @@ -10,8 +10,6 @@ import freechips.rocketchip.util.DontTouch import testchipip._ -import utilities.{System, SystemModule} - import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ diff --git a/generators/example/src/main/scala/TopCakes.scala b/generators/chipyard/src/main/scala/TopCakes.scala similarity index 97% rename from generators/example/src/main/scala/TopCakes.scala rename to generators/chipyard/src/main/scala/TopCakes.scala index 30f13e48..cd52ed55 100644 --- a/generators/example/src/main/scala/TopCakes.scala +++ b/generators/chipyard/src/main/scala/TopCakes.scala @@ -1,4 +1,4 @@ -package example +package chipyard import chisel3._ diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index dd5b432d..11598719 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -20,7 +20,7 @@ import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGenerat import scala.util.Try -import utilities.TestSuiteHelper +import chipyard.TestSuiteHelper trait HasTestSuites { def addTestSuites(targetName: String, params: Parameters) { diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index ed2a86c5..b57fc305 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -114,6 +114,7 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * determine which driver to build. *******************************************************************************/ class FireSimRocketChipConfig extends Config( + new chipyard.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB @@ -172,6 +173,7 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config( new FireSimRocketChipConfig) class FireSimBoomConfig extends Config( + new chipyard.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index be93bb7a..126dee1f 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -51,7 +51,7 @@ trait HasTraceIOImp extends LazyModuleImp { } trait CanHaveMultiCycleRegfileImp { - val outer: utilities.HasBoomAndRocketTiles + val outer: chipyard.HasBoomAndRocketTiles outer.tiles.map { case r: RocketTile => { diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index b608e67b..ecb6665c 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -12,7 +12,6 @@ import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.amba.axi4.AXI4Bundle import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.LazyModule -import utilities.{Subsystem, SubsystemModuleImp} import icenet._ import firesim.util.DefaultFireSimHarness import testchipip._ @@ -38,53 +37,20 @@ import FireSimValName._ * determine which driver to build. *******************************************************************************/ -class FireSimDUT(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with CanHavePeripherySerial - with HasPeripheryUART - with CanHavePeripheryIceNIC - with CanHavePeripheryBlockDevice +class FireSimDUT(implicit p: Parameters) extends chipyard.Top with HasTraceIO { override lazy val module = new FireSimModuleImp(this) } -class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with CanHavePeripherySerialModuleImp - with HasPeripheryUARTModuleImp - with HasPeripheryIceNICModuleImpValidOnly - with CanHavePeripheryBlockDeviceModuleImp +class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) with HasTraceIOImp with CanHaveMultiCycleRegfileImp class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) -class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with CanHavePeripherySerial - with HasPeripheryUART - with CanHavePeripheryBlockDevice - with HasTraceIO -{ - override lazy val module = new FireSimNoNICModuleImp(this) -} - -class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l) - with HasRTCModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with CanHavePeripherySerialModuleImp - with HasPeripheryUARTModuleImp - with CanHavePeripheryBlockDeviceModuleImp - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp +// Kept for legacy-reasons, this is equivalent to FireSimDUT +class FireSimNoNICDUT(implicit p: Parameters) extends FireSimDUT class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) @@ -107,7 +73,7 @@ class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() // Verilog blackbox integration demo class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT - with example.CanHavePeripheryGCD + with chipyard.CanHavePeripheryGCD { override lazy val module = new FireSimVerilogGCDModuleImp(this) } diff --git a/variables.mk b/variables.mk index a303eafe..1ddada7b 100644 --- a/variables.mk +++ b/variables.mk @@ -25,10 +25,10 @@ # - make it so that you only change 1 param to change most or all of them! # - mainly intended for quick developer setup for common flags ######################################################################################### -SUB_PROJECT ?= example +SUB_PROJECT ?= chipyard -ifeq ($(SUB_PROJECT),example) - SBT_PROJECT ?= example +ifeq ($(SUB_PROJECT),chipyard) + SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= $(SBT_PROJECT) From ebfa545344fcfea8bf17f598575b7a581c04d333 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 6 Feb 2020 20:15:09 -0800 Subject: [PATCH 013/139] Generator unification --- .circleci/config.yml | 32 ++ .circleci/defaults.sh | 4 +- .circleci/do-rtl-build.sh | 12 + .circleci/run-tests.sh | 9 +- build.sbt | 4 +- .../chipyard/src/main/scala/BoomConfigs.scala | 162 +++++++--- .../src/main/scala/ConfigMixins.scala | 128 +------- generators/chipyard/src/main/scala/GCD.scala | 11 +- .../src/main/scala/HeteroConfigs.scala | 214 ++++++------ .../chipyard/src/main/scala/IOBinders.scala | 131 ++++++++ .../chipyard/src/main/scala/InitZero.scala | 11 +- .../chipyard/src/main/scala/NodeTypes.scala | 2 +- .../src/main/scala/RocketConfigs.scala | 304 ++++++++++++------ .../chipyard/src/main/scala/TestHarness.scala | 39 +-- generators/chipyard/src/main/scala/Top.scala | 40 +-- .../chipyard/src/main/scala/TopCakes.scala | 27 -- .../src/main/scala/TracegenConfigs.scala | 35 ++ .../src/main/scala/BridgeBinders.scala | 83 +++-- .../src/main/scala/TargetConfigs.scala | 147 ++------- ...{TargetMixins.scala => TargetTraits.scala} | 0 .../firechip/src/main/scala/Targets.scala | 45 +-- generators/icenet | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/Configs.scala | 17 - .../tracegen/src/main/scala/TestHarness.scala | 27 -- sims/firesim | 2 +- variables.mk | 11 - 27 files changed, 815 insertions(+), 686 deletions(-) create mode 100644 generators/chipyard/src/main/scala/IOBinders.scala delete mode 100644 generators/chipyard/src/main/scala/TopCakes.scala create mode 100644 generators/chipyard/src/main/scala/TracegenConfigs.scala rename generators/firechip/src/main/scala/{TargetMixins.scala => TargetTraits.scala} (100%) delete mode 100644 generators/tracegen/src/main/scala/TestHarness.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index ad5671b1..8758064e 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -226,6 +226,31 @@ jobs: - prepare-rtl: tools-version: "esp-tools" project-key: "chipyard-gemmini" + prepare-tracegen: + executor: main-env + steps: + - prepare-rtl: + project-key: "tracegen" + prepare-tracegen-boom: + executor: main-env + steps: + - prepare-rtl: + project-key: "tracegen-boom" + prepare-firesim: + executor: main-env + steps: + - prepare-rtl: + project-key: "firesim" + build-script: "do-firesim-build.sh" + prepare-fireboom: + executor: main-env + steps: + - prepare-rtl: + project-key: "fireboom" + build-script: "do-firesim-build.sh" + + + chipyard-rocket-run-tests: executor: main-env steps: @@ -284,6 +309,13 @@ jobs: run-script: "run-firesim-tests.sh" timeout: "20m" + midasexamples-run-tests: + executor: main-env + steps: + - setup-tools-verilator + - run: + name: Run midasexamples tests + command: .circleci/run-midasexamples-tests.sh # Order and dependencies of jobs to run workflows: version: 2 diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 64ed3138..6c2fdd16 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -48,7 +48,7 @@ mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" -mapping["tracegen"]="SUB_PROJECT=tracegen CONFIG=NonBlockingTraceGenL2Config" -mapping["tracegen-boom"]="SUB_PROJECT=tracegen CONFIG=BoomTraceGenConfig" +mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" +mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 2e6384a2..5276080f 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -32,6 +32,18 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib + +if [ $1 = "chipyard-gemmini" ]; then + export RISCV=$LOCAL_ESP_DIR + export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib + export PATH=$RISCV/bin:$PATH + GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests + cd $LOCAL_SIM_DIR/../../generators/gemmini/software + git submodule update --init --recursive gemmini-rocc-tests + cd gemmini-rocc-tests + ./build.sh +fi + if [ $1 = "chipyard-hwacha" ] || [ $1 = "chipyard-gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR LD_LIB_DIR=$REMOTE_ESP_DIR/lib diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index cc747756..100418aa 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -52,12 +52,11 @@ case $1 in export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests - cd $GEMMINI_SOFTWARE_DIR - ./build.sh + rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests cd $LOCAL_SIM_DIR - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal - make run-binary ${mapping[$1]} BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal + $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; tracegen) run_tracegen ${mapping[$1]} diff --git a/build.sbt b/build.sbt index 539f9307..678fffb5 100644 --- a/build.sbt +++ b/build.sbt @@ -123,7 +123,7 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet, tracegen) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -195,7 +195,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala index 9eae1ea0..cd1e691b 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -8,74 +8,118 @@ import freechips.rocketchip.config.{Config} // BOOM Configs // --------------------- + class SmallBoomConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // use testchipip bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level mmio master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level mmio slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache - new boom.common.WithSmallBooms ++ // 1-wide BOOM - new boom.common.WithNBoomCores(1) ++ // single-core - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new boom.common.WithSmallBooms ++ // small boom config + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + class MediumBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithMediumBooms ++ // 2-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithLargeBooms ++ // 3-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithMegaBooms ++ // 4-wide BOOM + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) class DualSmallBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithSmallBooms ++ - new boom.common.WithNBoomCores(2) ++ // dual-core + new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.system.BaseConfig) class SmallRV32BoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithoutBoomFPU ++ // no fp new boom.common.WithBoomRV32 ++ // rv32 (32bit) new boom.common.WithSmallBooms ++ @@ -83,28 +127,42 @@ class SmallRV32BoomConfig extends Config( new freechips.rocketchip.system.BaseConfig) class HwachaLargeBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator - new boom.common.WithLargeBooms ++ // 3-wide BOOM - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - -class LoopbackNICBoomConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithLoopbackNIC ++ // loopback the NIC - new WithIceNIC ++ // add IceNIC - new WithBootROM ++ - new WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.system.BaseConfig) + +class LoopbackNICLargeBoomConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new testchipip.WithTSI ++ + new icenet.WithIceNIC ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigMixins.scala index f2dfcf2b..8234f0e3 100644 --- a/generators/chipyard/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigMixins.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.config import chisel3._ import chisel3.util.{log2Up} @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import icenet.{NICKey, NICConfig} +import chipyard.{BuildTop} /** * TODO: Why do we need this? @@ -35,117 +35,40 @@ import ConfigValName._ // Common Parameter Mixins // ----------------------- -/** - * Mixin to add the Chipyard bootrom - */ class WithBootROM extends Config((site, here, up) => { case BootROMParams => BootROMParams( contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") }) // DOC include start: gpio mixin -/** - * Mixin to add GPIOs and tie them off outside the DUT - */ class WithGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq( GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - // TODO: Currently FIRRTL will error if the GPIO input - // pins are unconnected, so tie them to 0. - // In future IO cell blackboxes will replace this with - // more correct functionality - for (gpio <- top.gpio) { - for (pin <- gpio.pins) { - pin.i.ival := false.B - } - } - top - } }) // DOC include end: gpio mixin -/** - * Mixin to add in UART - */ class WithUART extends Config((site, here, up) => { case PeripheryUARTKey => Seq( UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) -/** - * Mixin to remove any GPIOs - */ class WithNoGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq() }) -// DOC include start: tsi mixin -/** - * Mixin to add an offchip TSI link (used for backing memory) - */ -class WithTSI extends Config((site, here, up) => { - case SerialKey => true - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - success := top.connectSimSerial() - top - } -}) -// DOC include end: tsi mixin - -/** - * Mixin to add an DTM (used for dmi or jtag bringup) - */ -class WithDTM extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.reset := reset.asBool | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) - Debug.connectDebug(top.debug, top.psd, clock, reset.asBool, success)(p) - top - } +class WithL2TLBs(entries: Int) extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( + core = tile.core.copy(nL2TLBEntries = entries) + )) }) -// DOC include start: GCD mixin -/** - * Mixin to add a GCD peripheral - */ -class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { - case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) -}) -// DOC include end: GCD mixin - -/** - * Mixin to add a RTL block device model - */ -class WithBlockDeviceModel extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectBlockDeviceModel() - top - } +class WithTracegenTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) }) -/** - * Mixin to add a simulated block device model - */ -class WithSimBlockDevice extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectSimBlockDevice(clock, reset) - top - } -}) - -// DOC include start: WithInitZero -/** - * Mixin to add a peripheral that clears memory - */ -class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { - case InitZeroKey => Some(InitZeroConfig(base, size)) -}) -// DOC include end: WithInitZero // ------------------ // Multi-RoCC Support @@ -215,32 +138,3 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) - -/** - * Mixin to add an IceNIC - */ -class WithIceNIC(inBufFlits: Int = 1800, usePauser: Boolean = false) - extends Config((site, here, up) => { - case NICKey => Some(NICConfig( - inBufFlits = inBufFlits, - usePauser = usePauser, - checksumOffload = true)) -}) - -/** - * Mixin to loopback the IceNIC - */ -class WithLoopbackNIC extends Config((site, here, up) => { - case BuildTop => (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = up(BuildTop, site)(clock, reset, p, success) - top.connectNicLoopback() - top - } -}) - -/** - * Mixin to add a backing scratchpad (default size 4MB) - */ -class WithBackingScratchpad(base: BigInt = 0x80000000L, mask: BigInt = ((4 << 20) - 1)) extends Config((site, here, up) => { - case BackingScratchpadKey => Some(BackingScratchpadParams(base, mask)) -}) diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala index 1b66b76c..802520f0 100644 --- a/generators/chipyard/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -1,11 +1,11 @@ -package chipyard +package chipyard.example import chisel3._ import chisel3.util._ import chisel3.experimental.{IntParam, BaseModule} import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.regmapper.{HasRegMap, RegField} import freechips.rocketchip.tilelink._ @@ -198,3 +198,10 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { } // DOC include end: GCD imp trait + + +// DOC include start: GCD mixin +class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { + case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) +}) +// DOC include end: GCD mixin diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala index 4bfea32c..b5cc6b8c 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -9,140 +9,164 @@ import freechips.rocketchip.config.{Config} // --------------------- class LargeBoomAndRocketConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // default bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2 - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new boom.common.WithRenumberHarts ++ // avoid hartid overlap - new boom.common.WithLargeBooms ++ // 3-wide boom - new boom.common.WithNBoomCores(1) ++ // single-core boom - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single-core rocket - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system - -class SmallBoomAndRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithSmallBooms ++ // 1-wide boom - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new boom.common.WithRenumberHarts ++ // avoid hartid overlap + new boom.common.WithLargeBooms ++ // 3-wide boom + new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: BoomAndRocketWithHwacha class HwachaLargeBoomAndHwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha -class RoccLargeBoomAndRoccRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithRoccExample ++ // add example rocc accelerator to all harts - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - class DualLargeBoomAndRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new boom.common.WithRenumberHarts ++ + new boom.common.WithLargeBooms ++ + new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new boom.common.WithRenumberHarts ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2-boom cores + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: DualBoomAndRocketOneHwacha -class DualLargeBoomAndHwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithMultiRoCC ++ // support heterogeneous rocc - new WithMultiRoCCHwacha(2) ++ // override: put hwacha on hart-2 (rocket) - new hwacha.DefaultHwachaConfig ++ // setup hwacha on all harts + +class LargeBoomAndHwachaRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc + new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocketOneHwacha + + class LargeBoomAndRV32RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ - new freechips.rocketchip.subsystem.WithRV32 ++ // use 32-bit rocket + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + // DOC include start: DualBoomAndRocket class DualLargeBoomAndDualRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 boom cores - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocket -class MultiCoreWithControlCoreConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithControlCore ++ // add small control core (last hartid) +class LargeBoomAndRocketWithControlCoreConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithControlCore ++ // add small control core to last hartid + new chipyard.config.WithL2TLBs(1024) ++ new boom.common.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(2) ++ // 2 normal boom cores - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 normal rocket cores + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) + diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala new file mode 100644 index 00000000..969230b7 --- /dev/null +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -0,0 +1,131 @@ +package chipyard.iobinders + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug._ +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system._ +import freechips.rocketchip.util._ + +import sifive.blocks.devices.gpio._ +import sifive.blocks.devices.uart._ + +import testchipip._ +import icenet._ +import tracegen.{HasTraceGenTilesModuleImp} + +import scala.reflect.{ClassTag, classTag} + +case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) + +class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + t match { + case top: T => fn(clock, reset, success, top) + case _ => Nil + } + }) + ) +}) + +class WithGPIOTiedOff extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil +}) + +class WithSimBlockDevice extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil +}) + +class WithBlockDeviceModel extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil +}) + +class WithLoopbackNIC extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil +}) + +class WithUARTAdapter extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryUARTModuleImp) => { + val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate + top.uart.zipWithIndex.foreach{ case (dut_io, i) => + val uart_sim = Module(new UARTAdapter(i, defaultBaudRate)(top.p)) + uart_sim.io.uart.txd := dut_io.txd + dut_io.rxd := uart_sim.io.uart.rxd + } + Nil + } +}) + +class WithSimAXIMem extends RegisterIOBinder({ + (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil +}) + +class WithSimAXIMMIO extends RegisterIOBinder({ + (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil +}) + +class WithDontTouchPorts extends RegisterIOBinder({ + (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil +}) + +class WithTieOffInterrupts extends RegisterIOBinder({ + (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil +}) + +class WithTieOffL2FBusAXI extends RegisterIOBinder({ + (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { + top.l2_frontend_bus_axi4.foreach(axi => { + axi.tieoff() + experimental.DataMirror.directionOf(axi.ar.ready) match { + case ActualDirection.Input => + axi.r.bits := DontCare + axi.b.bits := DontCare + case ActualDirection.Output => + axi.aw.bits := DontCare + axi.ar.bits := DontCare + axi.w.bits := DontCare + } + }) + Nil + } +}) + +class WithTiedOffDebug extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(top.debug, top.psd) + // tieoffDebug doesn't actually tie everything off :/ + top.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } +}) + +class WithSimSerial extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripherySerialModuleImp) => { + val ser_success = top.connectSimSerial() + when (ser_success) { s := true.B } + Nil + } +}) + +class WithTiedOffSerial extends RegisterIOBinder({ + (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil +}) + + +class WithSimDTM extends RegisterIOBinder({ + (c, r, s, top: HasPeripheryDebugModuleImp) => { + val dtm_success = Wire(Bool()) + top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) + Debug.connectDebug(top.debug, top.psd, c, r, dtm_success)(top.p) + when (dtm_success) { s := true.B } + Nil + } +}) + + +class WithTraceGenSuccessBinder extends RegisterIOBinder({ + (c, r, s, top: HasTraceGenTilesModuleImp) => s := top.success; Nil +}) diff --git a/generators/chipyard/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/InitZero.scala index 2861e0bb..c351a4dd 100644 --- a/generators/chipyard/src/main/scala/InitZero.scala +++ b/generators/chipyard/src/main/scala/InitZero.scala @@ -1,9 +1,9 @@ -package chipyard +package chipyard.example import chisel3._ import chisel3.util._ import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes} -import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange} import testchipip.TLHelper @@ -65,3 +65,10 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem => fbus.fromPort(Some("init-zero"))() := initZero.node } } + + +// DOC include start: WithInitZero +class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => { + case InitZeroKey => Some(InitZeroConfig(base, size)) +}) +// DOC include end: WithInitZero diff --git a/generators/chipyard/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/NodeTypes.scala index ca55b2ac..0e2b6565 100644 --- a/generators/chipyard/src/main/scala/NodeTypes.scala +++ b/generators/chipyard/src/main/scala/NodeTypes.scala @@ -1,4 +1,4 @@ -package chipyard +package chipyard.example import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index dfdadf03..4acf7943 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -9,233 +9,357 @@ import freechips.rocketchip.config.{Config} // -------------- class RocketConfig extends Config( - new WithTSI ++ // use testchipip serial offchip link - new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) - new WithBootROM ++ // use default bootrom - new WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class HwachaRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GemminiRocketConfig class GemminiRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new gemmini.DefaultGemminiConfig ++ // use Gemmini systolic array GEMM accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GemminiRocketConfig class RoccRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: JtagRocket class jtagRocketConfig extends Config( - new WithDTM ++ // use top with dtm - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithJtagDTM ++ // enable communicating with the DTM using jtag + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithSimDTM ++ // add SimJtag and SimSerial, use both to drive sim + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ // sets DTM communication interface to JTAG new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: JtagRocket // DOC include start: DmiRocket class dmiRocketConfig extends Config( - new WithDTM ++ // use top with dtm - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffSerial ++ + new chipyard.iobinders.WithSimDTM ++ // add SimDTM and use it to drive simulation + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DmiRocket // DOC include start: GCDTLRocketConfig class GCDTLRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithUART ++ - new WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink - new WithBootROM ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithGCD(useAXI4=false, useBlackBox=false) ++ // Use GCD Chisel, connect Tilelink new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDTLRocketConfig // DOC include start: GCDAXI4BlackBoxRocketConfig class GCDAXI4BlackBoxRocketConfig extends Config( - new WithTSI ++ - new WithUART ++ - new WithNoGPIO ++ - new WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink - new WithBootROM ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig class SimBlockDeviceRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new WithSimBlockDevice ++ // use top with block-device IOs and connect to simblockdevice - new WithBootROM ++ - new WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel + new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new WithBlockDeviceModel ++ // use top with block-device IOs and connect to a blockdevicemodel - new WithBootROM ++ - new WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GPIORocketConfig class GPIORocketConfig extends Config( - new WithTSI ++ - new WithGPIO ++ // add GPIOs to the peripherybus - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top + new testchipip.WithTSI ++ + new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig class DualCoreRocketConfig extends Config( - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ - new WithNoGPIO ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles) new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class GB1MemoryRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 1GB simulated external memory + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: Sha3Rocket class Sha3RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: Sha3Rocket // DOC include start: InitZeroRocketConfig class InitZeroRocketConfig extends Config( - new WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero - new WithNoGPIO ++ - new WithTSI ++ - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new chipyard.example.WithInitZero(0x88000000L, 0x1000L) ++ // add InitZero new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: InitZeroRocketConfig class LoopbackNICRocketConfig extends Config( - new WithTSI ++ - new WithIceNIC ++ // add an IceNIC - new WithNoGPIO ++ - new WithLoopbackNIC ++ // loopback the IceNIC - new WithBootROM ++ - new WithUART ++ + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback + new testchipip.WithTSI ++ + new icenet.WithIceNIC ++ // add an IceNIC + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) class ScratchpadRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new WithBackingScratchpad ++ // add backing scratchpad + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new testchipip.WithBackingScratchpad ++ // add backing scratchpad + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 6c01753f..ca861288 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -10,48 +10,21 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.util.GeneratorApp import freechips.rocketchip.devices.debug.{Debug} -/** - * TODO: Why do we need this? - */ -import ConfigValName._ +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders} // ------------------------------- // BOOM and/or Rocket Test Harness // ------------------------------- -case object BuildTop extends Field[(Clock, Bool, Parameters, Bool) => TopModule[Top]]( - (clock: Clock, reset: Bool, p: Parameters, success: Bool) => { - val top = Module(LazyModule(new Top()(p)).suggestName("top").module) - top.debug.map { debug => debug := DontCare } - top - } -) +case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module)) -/** - * Test harness using TSI to bringup the system - */ class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val success = Output(Bool()) }) - val dut = p(BuildTop)(clock, reset.toBool, p, io.success) - dut.connectSimUARTs() - dut.connectSimAXIMem() - dut.connectSimAXIMMIO() - dut.dontTouchPorts() - dut.tieOffInterrupts() - dut.l2_frontend_bus_axi4.foreach(axi => { - axi.tieoff() - experimental.DataMirror.directionOf(axi.ar.ready) match { - case core.ActualDirection.Input => - axi.r.bits := DontCare - axi.b.bits := DontCare - case core.ActualDirection.Output => - axi.aw.bits := DontCare - axi.ar.bits := DontCare - axi.w.bits := DontCare - } - }) - + val dut = p(BuildTop)(p) + io.success := false.B + p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut)) } diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala index d4382d86..b95794e5 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -6,14 +6,6 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.util.DontTouch - -import testchipip._ - -import sifive.blocks.devices.gpio._ -import sifive.blocks.devices.uart._ - -import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp} // ------------------------------------ // BOOM and/or Rocket Top Level Systems @@ -21,26 +13,24 @@ import icenet.{CanHavePeripheryIceNIC, CanHavePeripheryIceNICModuleImp} // DOC include start: Top class Top(implicit p: Parameters) extends System - with CanHavePeripheryUARTAdapter // Enables optionally adding the UART print adapter - with HasPeripheryUART // Enables optionally adding the sifive UART - with HasPeripheryGPIO // Enables optionally adding the sifive GPIOs - with CanHavePeripheryBlockDevice // Enables optionally adding the block device - with CanHavePeripheryInitZero // Enables optionally adding the initzero example widget - with CanHavePeripheryGCD // Enables optionally adding the GCD example widget - with CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port - with CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim - with CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad + with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device + with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port + with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART + with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim + with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget + with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget { override lazy val module = new TopModule(this) } class TopModule[+L <: Top](l: L) extends SystemModule(l) - with HasPeripheryGPIOModuleImp - with HasPeripheryUARTModuleImp - with CanHavePeripheryBlockDeviceModuleImp - with CanHavePeripheryGCDModuleImp - with CanHavePeripherySerialModuleImp - with CanHavePeripheryIceNICModuleImp - with CanHavePeripheryUARTAdapterModuleImp - with DontTouch + with testchipip.CanHavePeripheryBlockDeviceModuleImp + with testchipip.CanHavePeripherySerialModuleImp + with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with icenet.CanHavePeripheryIceNICModuleImp + with chipyard.example.CanHavePeripheryGCDModuleImp + with freechips.rocketchip.util.DontTouch // DOC include end: Top diff --git a/generators/chipyard/src/main/scala/TopCakes.scala b/generators/chipyard/src/main/scala/TopCakes.scala deleted file mode 100644 index cd52ed55..00000000 --- a/generators/chipyard/src/main/scala/TopCakes.scala +++ /dev/null @@ -1,27 +0,0 @@ -package chipyard - -import chisel3._ - -import freechips.rocketchip.subsystem.BaseSubsystem -import freechips.rocketchip.config.{Field} -import freechips.rocketchip.diplomacy.{LazyModule, AddressSet} -import freechips.rocketchip.tilelink.{TLRAM} - -case class BackingScratchpadParams( - base: BigInt, - mask: BigInt) - -case object BackingScratchpadKey extends Field[Option[BackingScratchpadParams]](None) - -/** - * Trait to add a scratchpad on the mbus - */ -trait CanHaveBackingScratchpad { this: BaseSubsystem => - private val portName = "Backing-Scratchpad" - - val spadOpt = p(BackingScratchpadKey).map { param => - val spad = LazyModule(new TLRAM(address=AddressSet(param.base, param.mask), beatBytes=mbus.beatBytes)) - mbus.toVariableWidthSlave(Some(portName)) { spad.node } - spad - } -} diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala new file mode 100644 index 00000000..0e3457f0 --- /dev/null +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -0,0 +1,35 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} +import freechips.rocketchip.rocket.{DCacheParams} + +class TraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class BoomTraceGenConfig extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenL2Config extends Config( + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index f0c9c664..2e4fbd24 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -3,52 +3,48 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.annotate -import freechips.rocketchip.config.{Field, Config} +import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} -import icenet.HasPeripheryIceNICModuleImpValidOnly +import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} +import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey -import firesim.util.RegisterBridgeBinder import tracegen.HasTraceGenTilesModuleImp -class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp => - target.debug.foreach(_.clockeddmi.foreach({ cdmi => - cdmi.dmi.req.valid := false.B - cdmi.dmi.req.bits := DontCare - cdmi.dmi.resp.ready := false.B - cdmi.dmiClock := false.B.asClock - cdmi.dmiReset := false.B - })) - Seq() +import boom.common.{BoomTile} + +import chipyard.iobinders.{IOBinders, RegisterIOBinder} +import chipyard.HasBoomAndRocketTilesModuleImp + +class WithSerialBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq }) -class WithSerialBridge extends RegisterBridgeBinder({ - case target: CanHavePeripherySerialModuleImp => Seq(SerialBridge(target.serial.get)(target.p)) +class WithNICBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq }) -class WithNICBridge extends RegisterBridgeBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) +class WithUARTBridge extends RegisterIOBinder({ + (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq }) -class WithUARTBridge extends RegisterBridgeBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) +class WithBlockDeviceBridge extends RegisterIOBinder({ + (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq }) -class WithBlockDeviceBridge extends RegisterBridgeBinder({ - case target: CanHavePeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev.get, target.reset.toBool)(target.p)) -}) - -class WithFASEDBridge extends RegisterBridgeBinder({ - case t: CanHaveMasterAXI4MemPortModuleImp => +class WithFASEDBridge extends RegisterIOBinder({ + (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => @@ -59,24 +55,51 @@ class WithFASEDBridge extends RegisterBridgeBinder({ CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq + } }) -class WithTracerVBridge extends RegisterBridgeBinder({ - case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) +class WithTracerVBridge extends RegisterIOBinder({ + (c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p)) }) -class WithTraceGenBridge extends RegisterBridgeBinder({ - case target: HasTraceGenTilesModuleImp => - Seq(GroundTestBridge(target.success)(target.p)) +class WithTraceGenBridge extends RegisterIOBinder({ + (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) +class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ + (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { + target.outer.tiles.map { + case r: RocketTile => { + annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) + r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + } + case b: BoomTile => { + val core = b.module.core + core.iregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { + case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) + case _ => Nil + } + } + } + Nil + } +}) + + + // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new WithTiedOffDebug ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithTieOffInterrupts ++ new WithSerialBridge ++ new WithNICBridge ++ new WithUARTBridge ++ new WithBlockDeviceBridge ++ new WithFASEDBridge ++ + new WithFireSimMultiCycleRegfile ++ new WithTracerVBridge ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index b57fc305..9ecf6f48 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -2,6 +2,7 @@ package firesim.firesim import java.io.File +import chisel3._ import chisel3.util.{log2Up} import freechips.rocketchip.config.{Parameters, Config} import freechips.rocketchip.groundtest.TraceGenParams @@ -11,6 +12,7 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} +import freechips.rocketchip.diplomacy.LazyModule import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} @@ -21,6 +23,8 @@ import icenet._ import firesim.bridges._ import firesim.util.{WithNumNodes} import firesim.configs._ +import chipyard.{BuildTop} +import chipyard.config.ConfigValName._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -40,33 +44,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) }) -class WithUARTKey extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams( - address = BigInt(0x54000000L), - nTxEntries = 256, - nRxEntries = 256)) -}) - -class WithSerial extends Config((site, here, up) => { - case SerialKey => true -}) - -class WithBlockDevice extends Config(new testchipip.WithBlockDevice) - -class WithNICKey extends Config((site, here, up) => { - case NICKey => Some(NICConfig( - inBufFlits = 8192, - ctrlQueueDepth = 64, - checksumOffload = true)) -}) - -class WithRocketL2TLBs(entries: Int) extends Config((site, here, up) => { - case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( - core = tile.core.copy( - nL2TLBEntries = entries - ) - )) -}) class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( @@ -74,11 +51,6 @@ class WithPerfCounters extends Config((site, here, up) => { )) }) -class WithBoomL2TLBs(entries: Int) extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( - core = tile.core.copy(nL2TLBEntries = entries) - )) -}) class WithBoomEnableTrace extends Config((site, here, up) => { case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) @@ -92,7 +64,11 @@ class WithoutClockGating extends Config((site, here, up) => { // Testing configurations // This enables printfs used in testing class WithScalaTestFeatures extends Config((site, here, up) => { - case PrintTracePort => true + case PrintTracePort => true +}) + +class WithFireSimTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module) }) // FASED Config Aliases. This to enable config generation via "_" concatenation @@ -114,20 +90,24 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * determine which driver to build. *******************************************************************************/ class FireSimRocketChipConfig extends Config( - new chipyard.WithNoGPIO ++ + new chipyard.config.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithSerial ++ - new WithBlockDevice ++ - new WithRocketL2TLBs(1024) ++ + new chipyard.config.WithUART ++ + new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithL2TLBs(1024) ++ new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ new WithDefaultFireSimBridges ++ + new WithFireSimTop ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -173,22 +153,26 @@ class FireSimRocketChipSha3L2PrintfConfig extends Config( new FireSimRocketChipConfig) class FireSimBoomConfig extends Config( - new chipyard.WithNoGPIO ++ + new chipyard.config.WithNoGPIO ++ new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ new WithExtMemSize(0x400000000L) ++ // 16GB new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithSerial ++ - new WithBlockDevice ++ new WithBoomEnableTrace ++ - new WithBoomL2TLBs(1024) ++ + new chipyard.config.WithUART ++ + new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new WithDefaultFireSimBridges ++ + new WithFireSimTop ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.system.BaseConfig ) @@ -215,10 +199,12 @@ class FireSimBoomQuadCoreConfig extends Config( // dual core config (rocket + small boom) class FireSimRocketBoomConfig extends Config( - new WithBoomL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) + new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) new boom.common.WithRenumberHarts ++ // fix hart numbering new boom.common.WithSmallBooms ++ // change single BOOM to small new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ new FireSimBoomConfig ) @@ -277,72 +263,3 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config( new WithNumNodes(4) ++ new WithExtMemSize(0x200000000L) ++ // 8GB new FireSimRocketChipOctaCoreConfig) - -class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val nSets = dcp.nSets - val nWays = dcp.nWays - val blockOffset = site(SystemBusKey).blockOffset - val nBeats = min(2, site(SystemBusKey).blockBeats) - val beatBytes = site(SystemBusKey).beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => log2Up(params.size) -}) - -class FireSimTraceGenConfig extends Config( - new WithTraceGen( - List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new WithTraceGenBridge ++ - new FireSimRocketChipConfig) - -class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) - extends Config((site, here, up) => { - case TraceGenKey => params.map { dcp => TraceGenParams( - dcache = Some(dcp), - wordBits = site(XLen), - addrBits = 48, - addrBag = { - val sbp = site(SystemBusKey) - val l2p = site(InclusiveCacheKey) - val nSets = max(l2p.sets, dcp.nSets) - val nWays = max(l2p.ways, dcp.nWays) - val nBanks = site(BankedL2Key).nBanks - val blockOffset = sbp.blockOffset - val nBeats = min(2, sbp.blockBeats) - val beatBytes = sbp.beatBytes - List.tabulate(2 * nWays) { i => - Seq.tabulate(nBeats) { j => - BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset)) - } - }.flatten - }, - maxRequests = nReqs, - memStart = site(ExtMem).get.master.base, - numGens = params.size) - } - case MaxHartIdBits => log2Up(params.size) -}) - -class FireSimTraceGenL2Config extends Config( - new WithL2TraceGen( - List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new WithInclusiveCache( - nBanks = 4, - capacityKB = 1024, - outerLatencyCycles = 50) ++ - new WithTraceGenBridge ++ - new FireSimRocketChipConfig) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetTraits.scala similarity index 100% rename from generators/firechip/src/main/scala/TargetMixins.scala rename to generators/firechip/src/main/scala/TargetTraits.scala diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index ecb6665c..bdbda075 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -26,6 +26,8 @@ object FireSimValName { } import FireSimValName._ + + /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -44,40 +46,23 @@ class FireSimDUT(implicit p: Parameters) extends chipyard.Top } class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp + with HasTraceIOImp + with CanHaveMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) +class FireSim(implicit p: Parameters) extends DefaultFireSimHarness -// Kept for legacy-reasons, this is equivalent to FireSimDUT -class FireSimNoNICDUT(implicit p: Parameters) extends FireSimDUT -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) - -class FireSimTraceGenDUT(implicit p: Parameters) extends BaseSubsystem - with HasHierarchicalBusTopology - with HasTraceGenTiles - with CanHaveMasterAXI4MemPort { - override lazy val module = new FireSimTraceGenModuleImp(this) -} - -class FireSimTraceGenModuleImp(outer: FireSimTraceGenDUT) extends BaseSubsystemModuleImp(outer) - with HasTraceGenTilesModuleImp - with CanHaveMasterAXI4MemPortModuleImp - -class FireSimTraceGen(implicit p: Parameters) extends DefaultFireSimHarness( - () => new FireSimTraceGenDUT) - -// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 -class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) - -// Verilog blackbox integration demo -class FireSimVerilogGCDDUT(implicit p: Parameters) extends FireSimDUT - with chipyard.CanHavePeripheryGCD +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness { - override lazy val module = new FireSimVerilogGCDModuleImp(this) + throw new Exception("FireSimNoNIC is deprecated. Please add WithNoNIC to your TARGET_CONFIG and set DESIGN=FireSim to build a NoNIC simulator") } -class FireSimVerilogGCDModuleImp[+L <: FireSimVerilogGCDDUT](l: L) extends FireSimModuleImp(l) -class FireSimVerilogGCD(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimVerilogGCDDUT) +object FireSimTypeAliases { + // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 + type FireSimSupernode = FireSim + + // Verilog blackbox integration demo + type FireSimVerilogGCD = FireSim +} +import FireSimTypeAliases._ diff --git a/generators/icenet b/generators/icenet index 49b6dfb6..4980d3a3 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 49b6dfb6341bf128e95c549e42f881ad16dd45a5 +Subproject commit 4980d3a311e487419f2e6358d678c18b7ff3ffe4 diff --git a/generators/testchipip b/generators/testchipip index c11549ba..ff1daef0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit c11549ba30483ee3c0d331fb893c45814bdb6b63 +Subproject commit ff1daef09f2f9c2fdea5e93a3b38c58a226b7b3c diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala index dd195296..c22b0e3d 100644 --- a/generators/tracegen/src/main/scala/Configs.scala +++ b/generators/tracegen/src/main/scala/Configs.scala @@ -60,19 +60,6 @@ class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1 }) - -class TraceGenConfig extends Config( - new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - -class NonBlockingTraceGenConfig extends Config( - new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - -class BoomTraceGenConfig extends Config( - new WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ - new BaseConfig) - class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config((site, here, up) => { case TraceGenKey => params.map { dcp => TraceGenParams( @@ -100,7 +87,3 @@ class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size) }) -class NonBlockingTraceGenL2Config extends Config( - new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ - new WithInclusiveCache ++ - new BaseConfig) diff --git a/generators/tracegen/src/main/scala/TestHarness.scala b/generators/tracegen/src/main/scala/TestHarness.scala deleted file mode 100644 index 5e07909f..00000000 --- a/generators/tracegen/src/main/scala/TestHarness.scala +++ /dev/null @@ -1,27 +0,0 @@ -package tracegen - -import chisel3._ -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.diplomacy.LazyModule -import freechips.rocketchip.util.GeneratorApp - -class TestHarness(implicit p: Parameters) extends Module { - val io = IO(new Bundle { - val success = Output(Bool()) - }) - - val dut = Module(LazyModule(new TraceGenSystem).module) - io.success := dut.success - dut.connectSimAXIMem() -} - -object Generator extends GeneratorApp { - // specify the name that the generator outputs files as - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - // generate files - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/sims/firesim b/sims/firesim index 52aee63b..c771d114 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52aee63bc04c3769695a41ba18319e316c2e78d5 +Subproject commit c771d1143a98dd19f1c4a842cc8a572b5e54de98 diff --git a/variables.mk b/variables.mk index 1ddada7b..d124fed6 100644 --- a/variables.mk +++ b/variables.mk @@ -38,17 +38,6 @@ ifeq ($(SUB_PROJECT),chipyard) TB ?= TestDriver TOP ?= Top endif -ifeq ($(SUB_PROJECT),tracegen) - SBT_PROJECT ?= tracegen - MODEL ?= TestHarness - VLOG_MODEL ?= $(MODEL) - MODEL_PACKAGE ?= $(SBT_PROJECT) - CONFIG ?= TraceGenConfig - CONFIG_PACKAGE ?= $(SBT_PROJECT) - GENERATOR_PACKAGE ?= $(SBT_PROJECT) - TB ?= TestDriver - TOP ?= TraceGenSystem -endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) SBT_PROJECT ?= rocketchip From 0f56c4ce44affabc237d73e2e4cc1c4966918b61 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 11 Feb 2020 17:46:21 -0800 Subject: [PATCH 014/139] Unify configs between Chipyard and FireSim --- .circleci/config.yml | 2 +- .circleci/defaults.sh | 4 +- .../src/main/scala/RocketConfigs.scala | 4 +- generators/chipyard/src/main/scala/Top.scala | 2 + .../src/main/scala/BridgeBinders.scala | 5 +- .../src/main/scala/TargetConfigs.scala | 256 ++++++------------ .../src/main/scala/TargetTraits.scala | 74 ----- .../firechip/src/main/scala/Targets.scala | 25 -- generators/testchipip | 2 +- 9 files changed, 91 insertions(+), 283 deletions(-) delete mode 100644 generators/firechip/src/main/scala/TargetTraits.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index 8758064e..e86da712 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -307,7 +307,7 @@ jobs: extra-cache-restore: "extra-tests" project-key: "fireboom" run-script: "run-firesim-tests.sh" - timeout: "20m" + timeout: "30m" midasexamples-run-tests: executor: main-env diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 6c2fdd16..4393381e 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -50,5 +50,5 @@ mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" -mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" +mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" +mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index 4acf7943..6066f86f 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -228,7 +228,7 @@ class GPIORocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig -class DualCoreRocketConfig extends Config( +class QuadRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithSimAXIMem ++ @@ -243,7 +243,7 @@ class DualCoreRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // dual-core (2 RocketTiles) + new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/Top.scala index b95794e5..d81d779a 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/Top.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.devices.tilelink._ // DOC include start: Top class Top(implicit p: Parameters) extends System + with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port @@ -26,6 +27,7 @@ class Top(implicit p: Parameters) extends System } class TopModule[+L <: Top](l: L) extends SystemModule(l) + with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 2e4fbd24..3005d095 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp -import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} +import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} @@ -59,7 +59,7 @@ class WithFASEDBridge extends RegisterIOBinder({ }) class WithTracerVBridge extends RegisterIOBinder({ - (c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p)) + (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq }) class WithTraceGenBridge extends RegisterIOBinder({ @@ -93,6 +93,7 @@ class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( + new chipyard.iobinders.WithGPIOTiedOff ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithTieOffInterrupts ++ new WithSerialBridge ++ diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9ecf6f48..11916662 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.diplomacy.LazyModule import boom.common.BoomTilesKey -import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey} +import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} import tracegen.TraceGenKey @@ -52,10 +52,6 @@ class WithPerfCounters extends Config((site, here, up) => { }) -class WithBoomEnableTrace extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) -}) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -64,20 +60,37 @@ class WithoutClockGating extends Config((site, here, up) => { // Testing configurations // This enables printfs used in testing class WithScalaTestFeatures extends Config((site, here, up) => { - case PrintTracePort => true + case TracePortKey => up(TracePortKey, site).map(_.copy(print = true)) }) -class WithFireSimTop extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module) -}) // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package class DDR3FRFCFS extends FRFCFS16GBQuadRank class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB -// L2 Config Aliases. For use with "_" concatenation -class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache +class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) + + + +// Enables tracing on all cores +class WithTraceIO extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) +}) + + +// Tweaks that are generally applied to all firesim configs +class WithFireSimConfigTweaks extends Config( + new WithBootROM ++ // needed to support FireSim-as-top + new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ // 3.2 GHz + new WithoutClockGating ++ + new WithTraceIO ++ + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // 16 GB + new testchipip.WithTSI ++ + new testchipip.WithBlockDevice ++ + new chipyard.config.WithUART +) /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being @@ -88,178 +101,69 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache * will store this name as part of the tags for the AGFI, so that later you can * reconstruct what is in a particular AGFI. These tags are also used to * determine which driver to build. -*******************************************************************************/ -class FireSimRocketChipConfig extends Config( - new chipyard.config.WithNoGPIO ++ - new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - new WithExtMemSize(0x400000000L) ++ // 16GB - new WithoutTLMonitors ++ - new chipyard.config.WithUART ++ - new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ - new testchipip.WithTSI ++ - new testchipip.WithBlockDevice ++ - new chipyard.config.WithL2TLBs(1024) ++ - new WithPerfCounters ++ - new WithoutClockGating ++ - new WithDefaultMemModel ++ + *******************************************************************************/ + +//***************************************************************** +// Rocket configs, base off chipyard's RocketConfig +//***************************************************************** +class FireSimRocketConfig extends Config( new WithDefaultFireSimBridges ++ - new WithFireSimTop ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.system.DefaultConfig) - -class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { - case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i)) -}) - -// single core config -class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig) - -// dual core config -class FireSimRocketChipDualCoreConfig extends Config( - new WithNDuplicatedRocketCores(2) ++ - new FireSimRocketChipSingleCoreConfig) - -// quad core config -class FireSimRocketChipQuadCoreConfig extends Config( - new WithNDuplicatedRocketCores(4) ++ - new FireSimRocketChipSingleCoreConfig) - -// hexa core config -class FireSimRocketChipHexaCoreConfig extends Config( - new WithNDuplicatedRocketCores(6) ++ - new FireSimRocketChipSingleCoreConfig) - -// octa core config -class FireSimRocketChipOctaCoreConfig extends Config( - new WithNDuplicatedRocketCores(8) ++ - new FireSimRocketChipSingleCoreConfig) - -// SHA-3 accelerator config -class FireSimRocketChipSha3L2Config extends Config( - new WithInclusiveCache ++ - new sha3.WithSha3Accel ++ - new WithNBigCores(1) ++ - new FireSimRocketChipConfig) - -// SHA-3 accelerator config with synth printfs enabled -class FireSimRocketChipSha3L2PrintfConfig extends Config( - new WithInclusiveCache ++ - new sha3.WithSha3Printf ++ - new sha3.WithSha3Accel ++ - new WithNBigCores(1) ++ - new FireSimRocketChipConfig) - -class FireSimBoomConfig extends Config( - new chipyard.config.WithNoGPIO ++ - new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - new WithExtMemSize(0x400000000L) ++ // 16GB - new WithoutTLMonitors ++ - new WithBoomEnableTrace ++ - new chipyard.config.WithUART ++ - new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++ - new testchipip.WithTSI ++ - new testchipip.WithBlockDevice ++ - new chipyard.config.WithL2TLBs(1024) ++ - new WithoutClockGating ++ new WithDefaultMemModel ++ - new boom.common.WithLargeBooms ++ - new boom.common.WithNBoomCores(1) ++ + new WithFireSimConfigTweaks ++ + new chipyard.RocketConfig) + +class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ - new WithFireSimTop ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.system.BaseConfig -) + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.QuadRocketConfig) -// A safer implementation than the one in BOOM in that it -// duplicates whatever BOOMTileKey.head is present N times. This prevents -// accidentally (and silently) blowing away configurations that may change the -// tile in the "up" view -class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => { - case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i)) - case MaxHartIdBits => log2Up(site(BoomTilesKey).size) -}) -class FireSimBoomDualCoreConfig extends Config( - new WithNDuplicatedBoomCores(2) ++ - new FireSimBoomConfig) +//***************************************************************** +// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig +//***************************************************************** +class FireSimSha3RocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.Sha3RocketConfig) -class FireSimBoomQuadCoreConfig extends Config( - new WithNDuplicatedBoomCores(4) ++ - new FireSimBoomConfig) +class FireSimSha3PrintfRocketConfig extends Config( + new sha3.WithSha3Printf ++ + new FireSimSha3RocketConfig) + +//***************************************************************** +// Boom config, base off chipyard's LargeBoomConfig +//***************************************************************** +class FireSimLargeBoomConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LargeBoomConfig) + + +//******************************************************************** +// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig +//******************************************************************** +class FireSimLargeBoomAndRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.LargeBoomAndRocketConfig) + +//****************************************************************** +// Gemmini NN accel config, base off chipyard's GemminiRocketConfig +//****************************************************************** +class FireSimGemminiRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.GemminiRocketConfig) //********************************************************************************** -//* Heterogeneous Configurations -//*********************************************************************************/ - -// dual core config (rocket + small boom) -class FireSimRocketBoomConfig extends Config( - new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it) - new boom.common.WithRenumberHarts ++ // fix hart numbering - new boom.common.WithSmallBooms ++ // change single BOOM to small - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new FireSimBoomConfig -) - +// Supernode Configurations, base off chipyard's RocketConfig //********************************************************************************** -//* Gemmini Configurations -//*********************************************************************************/ - -// Gemmini systolic accelerator default config -class FireSimRocketChipGemminiL2Config extends Config( - new WithInclusiveCache ++ - new gemmini.DefaultGemminiConfig ++ - new WithNBigCores(1) ++ - new FireSimRocketChipConfig) - - -//********************************************************************************** -//* Supernode Configurations -//*********************************************************************************/ - -class SupernodeFireSimRocketChipConfig extends Config( +class SupernodeFireSimRocketConfig extends Config( new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipConfig) - -class SupernodeFireSimRocketChipSingleCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipSingleCoreConfig) - -class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config( - new WithNumNodes(6) ++ - new WithExtMemSize(0x40000000L) ++ // 1GB - new FireSimRocketChipSingleCoreConfig) - -class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config( - new WithNumNodes(8) ++ - new WithExtMemSize(0x40000000L) ++ // 1GB - new FireSimRocketChipSingleCoreConfig) - -class SupernodeFireSimRocketChipDualCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipDualCoreConfig) - -class SupernodeFireSimRocketChipQuadCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipQuadCoreConfig) - -class SupernodeFireSimRocketChipHexaCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipHexaCoreConfig) - -class SupernodeFireSimRocketChipOctaCoreConfig extends Config( - new WithNumNodes(4) ++ - new WithExtMemSize(0x200000000L) ++ // 8GB - new FireSimRocketChipOctaCoreConfig) + new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB + new FireSimRocketConfig) diff --git a/generators/firechip/src/main/scala/TargetTraits.scala b/generators/firechip/src/main/scala/TargetTraits.scala deleted file mode 100644 index 126dee1f..00000000 --- a/generators/firechip/src/main/scala/TargetTraits.scala +++ /dev/null @@ -1,74 +0,0 @@ -package firesim.firesim - -import chisel3._ -import chisel3.util.Cat -import chisel3.experimental.annotate -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.amba.axi4._ -import freechips.rocketchip.util._ -import freechips.rocketchip.tile.RocketTile -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.rocket.TracedInstruction -import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} - -import midas.targetutils.MemModelAnnotation - -import boom.common.BoomTile - -/* Wires out tile trace ports to the top; and wraps them in a Bundle that the - * TracerV bridge can match on. - */ -object PrintTracePort extends Field[Boolean](false) - -trait HasTraceIO { - this: HasTiles => - val module: HasTraceIOImp - - // Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp - val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]] - val tileTraceNodes = tiles.map(tile => tile.traceNode) - tileTraceNodes foreach { traceNexus := _ } -} - -trait HasTraceIOImp extends LazyModuleImp { - val outer: HasTraceIO - - val traceIO = IO(Output(new TraceOutputTop( - DeclockedTracedInstruction.fromNode(outer.traceNexus.in)))) - (traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) => - port := DeclockedTracedInstruction.fromVec(tileTrace) - }) - - // Enabled to test TracerV trace capture - if (p(PrintTracePort)) { - val traceprint = Wire(UInt(512.W)) - traceprint := Cat(traceIO.traces.map(_.reverse.asUInt)) - printf("TRACEPORT: %x\n", traceprint) - } -} - -trait CanHaveMultiCycleRegfileImp { - val outer: chipyard.HasBoomAndRocketTiles - - outer.tiles.map { - case r: RocketTile => { - annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) - r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) - } - case b: BoomTile => { - val core = b.module.core - core.iregfile match { - case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) - case _ => Nil - } - if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { - case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile)) - case _ => Nil - } - } - } -} - diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index bdbda075..6961782a 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -39,30 +39,5 @@ import FireSimValName._ * determine which driver to build. *******************************************************************************/ -class FireSimDUT(implicit p: Parameters) extends chipyard.Top - with HasTraceIO -{ - override lazy val module = new FireSimModuleImp(this) -} - -class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l) - with HasTraceIOImp - with CanHaveMultiCycleRegfileImp class FireSim(implicit p: Parameters) extends DefaultFireSimHarness - - -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness -{ - throw new Exception("FireSimNoNIC is deprecated. Please add WithNoNIC to your TARGET_CONFIG and set DESIGN=FireSim to build a NoNIC simulator") -} - - -object FireSimTypeAliases { - // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 - type FireSimSupernode = FireSim - - // Verilog blackbox integration demo - type FireSimVerilogGCD = FireSim -} -import FireSimTypeAliases._ diff --git a/generators/testchipip b/generators/testchipip index ff1daef0..a3da53e8 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ff1daef09f2f9c2fdea5e93a3b38c58a226b7b3c +Subproject commit a3da53e87ad890be37138e27e477eb9a563fa82e From c12819eb5235281b3a0d53883038498a07ab42e3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Feb 2020 11:40:10 -0800 Subject: [PATCH 015/139] Update docs --- docs/Advanced-Concepts/Chip-Communication.rst | 9 +- docs/Advanced-Concepts/Top-Testharness.rst | 10 +- docs/Chipyard-Basics/Chipyard-Components.rst | 6 +- .../Configs-Parameters-Mixins.rst | 53 ++---- .../Chipyard-Basics/Development-Ecosystem.rst | 2 +- docs/Customization/Custom-Chisel.rst | 4 +- docs/Customization/DMA-Devices.rst | 8 +- docs/Customization/Heterogeneous-SoCs.rst | 8 +- .../Incorporating-Verilog-Blocks.rst | 12 +- docs/Customization/Keys-Traits-Configs.rst | 41 +---- docs/Customization/MMIO-Peripherals.rst | 24 +-- docs/Customization/Memory-Hierarchy.rst | 169 +++++++++--------- docs/Generators/Gemmini.rst | 4 +- docs/Generators/Rocket-Chip.rst | 7 +- docs/Generators/SHA3.rst | 2 +- docs/Generators/SiFive-Generators.rst | 6 +- docs/Generators/TestChipIP.rst | 7 +- docs/Generators/index.rst | 2 +- docs/Quick-Start.rst | 65 ------- docs/Simulation/Software-RTL-Simulation.rst | 6 +- docs/Software/FireMarshal.rst | 1 + .../NodeTypes.rst | 12 +- .../Register-Router.rst | 14 +- docs/TileLink-Diplomacy-Reference/index.rst | 2 +- docs/Tools/FIRRTL.rst | 1 - docs/Tools/index.rst | 2 +- docs/VLSI/Advanced-Usage.rst | 4 +- docs/index.rst | 67 ++++++- 28 files changed, 247 insertions(+), 301 deletions(-) delete mode 100644 docs/Quick-Start.rst diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 29979900..fe9b6f57 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -109,16 +109,13 @@ reminder, to run a software RTL simulation, run: FireSim FPGA-accelerated simulations use TSI by default as well. -If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must create a -top-level system with the DTM (``TopWithDTM``), a test-harness to connect to the DTM (``TestHarnessWithDTM``), as well as a config to use that top-level system. +If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDTM` instead of `WithTiedOffDebug ++ WithSimSerial`. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: DmiRocket :end-before: DOC include end: DmiRocket -In this example, the ``WithDTM`` mixin specifies that the top-level SoC will instantiate a DTM (that by default is setup to use DMI). -The rest of the mixins specify the rest of the system (cores, accelerators, etc). Then you can run simulations with the new DMI-enabled top-level and test-harness. .. code-block:: bash @@ -144,7 +141,7 @@ The configuration is very similar to a DMI-based configuration. The main differe is the addition of the ``WithJtagDTM`` mixin that configures the instantiated DTM to use the JTAG protocol as the bringup method. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: JtagRocket :end-before: DOC include end: JtagRocket diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 3d22e54a..43b0be51 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -27,7 +27,7 @@ We also see this class define several ``ElaborationArtefacts``, files emitted af Subsystem ^^^^^^^^^^^^^^^^^^^^^^^^^ -Looking in `generators/utilities/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` +Looking in `generators/chipyard/src/main/scala/Subsystem.scala `__, we can see how Chipyard's ``Subsystem`` extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that defines and instantiates BOOM or Rocket tiles, depending on the parameters specified. We also connect some basic IOs for each tile here, specifically the hartids and the reset vector. @@ -35,7 +35,7 @@ We also connect some basic IOs for each tile here, specifically the hartids and System ^^^^^^^^^^^^^^^^^^^^^^^^^ -``generators/utilities/src/main/scala/System.scala`` completes the definition of the ``System``. +``generators/chipyard/src/main/scala/System.scala`` completes the definition of the ``System``. - ``HasHierarchicalBusTopology`` is defined in Rocket Chip, and specifies connections between the top-level buses - ``HasAsyncExtInterrupts`` and ``HasExtInterruptsModuleImp`` adds IOs for external interrupts and wires them appropriately to tiles @@ -45,7 +45,7 @@ System Tops ^^^^^^^^^^^^^^^^^^^^^^^^^ -A SoC Top then extends the ``System`` class with any config-specific components. +A SoC Top then extends the ``System`` class with traits for custom components. In Chipyard, this includes things like adding a NIC, UART, and GPIO as well as setting up the hardware for the bringup method. Please refer to :ref:`Communicating with the DUT` for more information on these bringup methods. @@ -55,7 +55,7 @@ TestHarness The wiring between the ``TestHarness`` and the Top are performed in methods defined in mixins added to the Top. When these methods are called from the ``TestHarness``, they may instantiate modules within the scope of the harness, and then connect them to the DUT. For example, the ``connectSimAXIMem`` method defined in the -``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMem``s +``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMems`` and connect them to the correct IOs of the top. While this roundabout way of attaching to the IOs of the top may seem to be unnecessarily complex, it allows the designer to compose @@ -66,4 +66,4 @@ TestDriver The ``TestDriver`` is defined in ``generators/rocketchip/src/main/resources/vsrc/TestDriver.v``. This Verilog file executes a simulation by instantiating the ``TestHarness``, driving the clock and reset signals, and interpreting the success output. -This file is compiled with the generated Verilog for the ``TestHarness`` and the Top to produce a simulator. +This file is compiled with the generated Verilog for the ``TestHarness`` and the ``Top`` to produce a simulator. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 29828e44..cbca299f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -29,9 +29,9 @@ Accelerators Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface. See :ref:`Hwacha` for more information. -.. Fixed Function Accelerators: - ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - TBD +**Gemmini** + A matrix-multiply accelerator targeting neural-networks + **SHA3** A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the Chipyard integration flows using the RoCC interface. diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index 6b8d0aca..e72a7444 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -74,52 +74,37 @@ Cake Pattern A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). It is used in the Rocket Chip SoC library and Chipyard framework in merging multiple system components and IO interfaces into a large system component. -This example shows a Rocket Chip based SoC that merges multiple system components (BootROM, UART, etc) into a single top-level design. +This example shows the Chipyard default top that composes multiple traits together into a fully-featured SoC with many optional components. -.. _cake-example: -.. code-block:: scala - class MySoC(implicit p: Parameters) extends RocketSubsystem - with CanHaveMasterAXI4MemPort - with HasPeripheryBootROM - with HasNoDebug - with HasPeripherySerial - with HasPeripheryUART - with HasPeripheryIceNIC - { - lazy val module = new MySoCModuleImp(this) - } +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala + :language: scala + :start-after: DOC include start: Top + :end-before: DOC include end: Top - class MySoCModuleImp(outer: MySoC) extends RocketSubsystemModuleImp(outer) - with CanHaveMasterAXI4MemPortModuleImp - with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp - with HasPeripherySerialModuleImp - with HasPeripheryUARTModuleImp - with HasPeripheryIceNICModuleImp -There are two "cakes" here. One for the lazy module (ex. ``HasPeripherySerial``) and one for the lazy module -implementation (ex. ``HasPeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines +There are two "cakes" here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module +implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. -In the ``MySoC`` example class, the "outer" ``MySoC`` instantiates the "inner" -``MySoCModuleImp`` as a lazy module implementation. This delays immediate elaboration +In the ``Top`` example class, the "outer" ``Top`` instantiates the "inner" +``TopModule`` as a lazy module implementation. This delays immediate elaboration of the module until all logical connections are determined and all configuration information is exchanged. -The ``RocketSubsystem`` outer base class, as well as the -``HasPeripheryX`` outer traits contain code to perform high-level logical -connections. For example, the ``HasPeripherySerial`` outer trait contains code -to lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s +The ``Syatem`` outer base class, as well as the +``CanHavePeripheryX`` outer traits contain code to perform high-level logical +connections. For example, the ``CanHavePeripherySerial`` outer trait contains code +to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s TileLink node to the Front bus. The ``ModuleImp`` classes and traits perform elaboration of real RTL. -For example, the ``HasPeripherySerialModuleImp`` trait physically connects +For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically connects the ``SerialAdapter`` module, and instantiates queues. In the test harness, the SoC is elaborated with -``val dut = Module(LazyModule(MySoC))``. -After elaboration, the result will be a ``MySoC`` module, which contains a -``SerialAdapter`` module (among others). +``val dut = Module(LazyModule(Top))``. +After elaboration, the result will be a ``Top`` module, which contains a +``SerialAdapter`` module (among others), if the config specified for that block to be instantiated. From a high level, classes which extend ``LazyModule`` *must* reference their module implementation through ``lazy val module``, and they @@ -134,8 +119,8 @@ Mix-in --------------------------- A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convention for an additive mix-in is ``Has``. -This is shown in the ``MySoC`` class where things such as ``HasPeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. +The naming convention for an additive mix-in is ``CanHave``. +This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. Additional References --------------------------- diff --git a/docs/Chipyard-Basics/Development-Ecosystem.rst b/docs/Chipyard-Basics/Development-Ecosystem.rst index b0cb557d..087fde6e 100644 --- a/docs/Chipyard-Basics/Development-Ecosystem.rst +++ b/docs/Chipyard-Basics/Development-Ecosystem.rst @@ -16,7 +16,7 @@ Chisel is an embedded language within Scala that provides a set of libraries to FIRRTL on the other hand is a compiler for hardware which allows the user to run FIRRTL passes that can do dead code elimination, circuit analysis, connectivity checks, and much more! These two tools in combination allow quick design space exploration and development of new RTL. -Generators +RTL Generators ------------------------------------------- Within this repository, all of the Chisel RTL is written as generators. diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst index feec3141..4ffbafbf 100644 --- a/docs/Customization/Custom-Chisel.rst +++ b/docs/Customization/Custom-Chisel.rst @@ -52,8 +52,8 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file. You can then import the classes defined in the submodule in a new project if you add it as a dependency. For instance, if you want to use this code in -the ``example`` project, change the final line in build.sbt to the following. +the ``chipyard`` project, change the final line in build.sbt to the following. .. code-block:: scala - lazy val example = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) + lazy val chipyard = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject) diff --git a/docs/Customization/DMA-Devices.rst b/docs/Customization/DMA-Devices.rst index f2e95e52..ed5678c9 100644 --- a/docs/Customization/DMA-Devices.rst +++ b/docs/Customization/DMA-Devices.rst @@ -12,10 +12,10 @@ having the CPU poll data from the device, we may want to have the device write directly to the coherent memory system instead. For example, here is a device that writes zeros to the memory at a configured address. -.. literalinclude:: ../../generators/example/src/main/scala/InitZero.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/InitZero.scala :language: scala -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top @@ -26,12 +26,12 @@ For more info on creating TileLink client nodes, take a look at :ref:`Client Nod Once we've created our top-level module including the DMA widget, we can create a configuration for it as we did before. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/InitZero.scala :language: scala :start-after: DOC include start: WithInitZero :end-before: DOC include end: WithInitZero -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: InitZeroRocketConfig :end-before: DOC include end: InitZeroRocketConfig diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index e1d58c6a..8087fd35 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -13,7 +13,7 @@ When used together you can create a heterogeneous system. The following example shows a dual core BOOM with a single core Rocket. -.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala :language: scala :start-after: DOC include start: DualBoomAndRocket :end-before: DOC include end: DualBoomAndRocket @@ -72,7 +72,7 @@ Adding Hwachas Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter. An example of adding a Hwacha to all tiles in the system is below. -.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala :language: scala :start-after: DOC include start: BoomAndRocketWithHwacha :end-before: DOC include end: BoomAndRocketWithHwacha @@ -83,12 +83,12 @@ All with the same Hwacha parameters. Assigning Accelerators to Specific Tiles with MultiRoCC ------------------------------------------------------- -Located in ``generators/example/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. +Located in ``generators/chipyard/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. -.. literalinclude:: ../../generators/example/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala :language: scala :start-after: DOC include start: DualBoomAndRocketOneHwacha :end-before: DOC include end: DualBoomAndRocketOneHwacha diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst index fc1b8d7d..bca9d067 100644 --- a/docs/Customization/Incorporating-Verilog-Blocks.rst +++ b/docs/Customization/Incorporating-Verilog-Blocks.rst @@ -48,12 +48,12 @@ Verilog files into the build process, which are part of the .settings(commonSettings) For this concrete GCD example, we will be using a ``GCDMMIOBlackBox`` -Verilog module that is defined in the ``example`` project. The Scala +Verilog module that is defined in the ``chipyard`` project. The Scala and Verilog sources follow the prescribed directory layout. .. code-block:: none - generators/example/ + generators/chipyard/ build.sbt src/main/ scala/ @@ -81,14 +81,14 @@ as the bitwidth of the GCD calculation does in this example. **Verilog GCD port list and parameters** -.. literalinclude:: ../../generators/example/src/main/resources/vsrc/GCDMMIOBlackBox.v +.. literalinclude:: ../../generators/chipyard/src/main/resources/vsrc/GCDMMIOBlackBox.v :language: Verilog :start-after: DOC include start: GCD portlist :end-before: DOC include end: GCD portlist **Chisel BlackBox Definition** -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD blackbox :end-before: DOC include end: GCD blackbox @@ -103,7 +103,7 @@ peripheral-specific traits into a ``TLRegisterRouter``. The ``params`` member and ``HasRegMap`` base trait should look familiar from the previous memory-mapped GCD device example. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD instance regmap :end-before: DOC include end: GCD instance regmap @@ -115,7 +115,7 @@ Defining a Chip with a BlackBox Since we've parameterized the GCD instantiation to choose between the Chisel and the Verilog module, creating a config is easy. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDAXI4BlackBoxRocketConfig :end-before: DOC include end: GCDAXI4BlackBoxRocketConfig diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index e7705f44..bac311c5 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -16,7 +16,7 @@ Keys specify some parameter which controls some custom widget. Keys should typic Keys should be defined and documented in sub-projects, since they generally deal with some specific block, and not system-level integration. (We make an exception for the example GCD widget). -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD key :end-before: DOC include end: GCD key @@ -24,7 +24,7 @@ Keys should be defined and documented in sub-projects, since they generally deal The object within a key is typically a ``case class XXXParams``, which defines a set of parameters which some block accepts. For example, the GCD widget's ``GCDParams`` parameterizes its address, operand widths, whether the widget should be connected by Tilelink or AXI4, and whether the widget should use the blackbox-Verilog implementation, or the Chisel implementation. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD params :end-before: DOC include end: GCD params @@ -42,14 +42,14 @@ Top-level traits should be defined and documented in subprojects, alongside thei Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD imp trait These traits are added to the default ``Top`` in Chipyard. -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top @@ -57,49 +57,22 @@ These traits are added to the default ``Top`` in Chipyard. Mixins ------ -Mixins set the keys to a non-default value. Together, the collection of Mixins which define a configuration generate the values for all the keys used by the generator. +Config mixins set the keys to a non-default value. Together, the collection of Mixins which define a configuration generate the values for all the keys used by the generator. For example, the ``WithGCDMixin`` is parameterized by the type of GCD widget you want to instantiate. When this mixin is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD mixin :end-before: DOC include end: GCD mixin We can use this mixin when composing our configs. -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDTLRocketConfig :end-before: DOC include end: GCDTLRocketConfig - -BuildTop --------- - -The ``BuildTop`` key is special, because sometimes, we need to instantiate ``TestHarness`` modules to interface with a custom widget. The ``BuildTop`` key provides a function which can call some method of the Top to instantiate these ``TestHarness`` modules. Since the ``BuildTop`` key is called from the ``TestHarness``, these modules will appear in the ``TestHarness``. The config system also lets the ``BuildTop`` key look recursively into previous definitions of itself. This enables composability of the ``Top`` configurations. - -For example, conside a config that contains the mixins ``WithGPIO ++ WithTSI``. We need to instantiate the TSI serial adapter, and connect it to the ``success`` signal of our ``TestHarness``. We also need to instantiate the GPIO pins, and tie their inputs to 0 in the ``TestHarness``, since we currently cannot drive the GPIOs in simulation. - -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala - :language: scala - :start-after: DOC include start: tsi mixin - :end-before: DOC include end: tsi mixin - - -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala - :language: scala - :start-after: DOC include start: gpio mixin - :end-before: DOC include end: gpio mixin - -When ``WithGPIO ++ WithTSI`` is evaluated right to left, the call to ``up(BuildTop, site)`` in ``WithGPIO`` will reference the function defined in the ``BuildTop`` key of ``WithTSI``. Thus, at elaboration time, when the ``BuildTop`` function is called by the ``TestHarness``, first the ``BuildTop`` function in ``WithTSI`` will be evaluated. This connects the ``success`` signal of the ``TestHarness`` to the ``SerialAdapter`` enabled by ``WithTSI``. Then, the rest of the code in the ``BuildTop`` function of ``WithGPIO`` will execute, tieing off the top-level GPIO input pins. Thus the evaluation of the ``BuildTop`` functions in a completed config is "right-to-left", matching how the evaluation of the mixins at compile-time is also "right-to-left". - -.. warning:: - In some cases, the ordering and duplication of mixins which extend ``BuildTop`` will have unintended consequences. - For example, ``WithTSI ++ WithTSI`` will attempt to generate and connect two ``SimSerial`` widgets in the ``TestHarness``, - which will likely break the simulation. - In general, you should avoid attaching multiple mixins which interface to the same top-level ports. - .. note:: Readers who want more information on the configuration system may be interested in reading :ref:`cdes`. diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index 23fddca4..c1c1a424 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -3,21 +3,21 @@ MMIO Peripherals ================== -The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/example/src/main/scala/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. +The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. For this example, we will show how to connect a MMIO peripheral which computes the GCD. -The full code can be found in ``generators/example/src/main/scala/GCD.scala``. +The full code can be found in ``generators/chipyard/src/main/scala/GCD.scala``. In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDModule`` class only creates the registers and hooks them up using ``regmap``. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD chisel :end-before: DOC include end: GCD chisel -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD instance regmap :end-before: DOC include end: GCD instance regmap @@ -51,7 +51,7 @@ The second set of arguments is the IO bundle constructor, which we create by ext The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. Notice how we can create an analogous AXI4 version of our peripheral. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD router :end-before: DOC include end: GCD router @@ -69,7 +69,7 @@ In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait a The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated. For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD lazy trait @@ -82,7 +82,7 @@ Also observe how we have to place additional AXI4 buffers and converters for the For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module. -.. literalinclude:: ../../generators/example/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD imp trait :end-before: DOC include end: GCD imp trait @@ -91,9 +91,9 @@ Constructing the Top and Config ------------------------------- Now we want to mix our traits into the system as a whole. -This code is from ``generators/example/src/main/scala/Top.scala``. +This code is from ``generators/chipyard/src/main/scala/Top.scala``. -.. literalinclude:: ../../generators/example/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala :language: scala :start-after: DOC include start: Top :end-before: DOC include end: Top @@ -105,14 +105,14 @@ The ``TopModule`` class is the actual RTL that gets synthesized. -And finally, we create a configuration class in ``generators/example/src/main/scala/Configs.scala`` that uses the ``WithGCD`` mixin defined earlier. +And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` mixin defined earlier. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala :start-after: DOC include start: GCD mixin :end-before: DOC include end: GCD mixin -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDTLRocketConfig :end-before: DOC include end: GCDTLRocketConfig diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 6266e435..26bce436 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -14,25 +14,43 @@ configure 4 KiB direct-mapped caches for L1I and L1D. .. code-block:: scala - class SmallRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores - new freechips.rocketchip.system.BaseConfig) + class SmallRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores + new freechips.rocketchip.system.BaseConfig) + + class MediumRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNMediumCores(1) ++ // Medium rocket cores + new freechips.rocketchip.system.BaseConfig) + - class MediumRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNMedCores(1) ++ // medium rocket cores - new freechips.rocketchip.system.BaseConfig) If you only want to change the size or associativity, there are configuration mixins for those too. @@ -42,18 +60,11 @@ mixins for those too. import freechips.rocketchip.subsystem.{WithL1ICacheSets, WithL1DCacheSets, WithL1ICacheWays, WithL1DCacheWays} class MyL1RocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithL1ICacheSets(128) ++ // change rocket I$ - new WithL1ICacheWays(2) ++ // change rocket I$ - new WithL1DCacheSets(128) ++ // change rocket D$ - new WithL1DCacheWays(2) ++ // change rocket D$ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithL1ICacheSets(128) ++ // change rocket I$ + new freechips.rocketchip.subsystem.WithL1ICacheWays(2) ++ // change rocket I$ + new freechips.rocketchip.subsystem.WithL1DCacheSets(128) ++ // change rocket D$ + new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++ // change rocket D$ + new RocketConfig) You can also configure the L1 data cache as an data scratchpad instead. However, there are some limitations on this. If you are using a data scratchpad, @@ -62,22 +73,26 @@ Note that these configurations fully remove the L2 cache and mbus. .. code-block:: scala - class SmallRocketConfigNoL2 extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + class ScratchpadSmallRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.system.BaseConfig) - class ScratchpadRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ - new SmallRocketConfigNoL2) This configuration fully removes the L2 cache and memory bus by setting the number of channels and number of banks to 0. @@ -92,23 +107,8 @@ set-associativity. However, you can change these parameters to obtain your desired cache configuration. The main restriction is that the number of ways and the number of banks must be powers of 2. -.. code-block:: scala - - import freechips.rocketchip.subsystem.WithInclusiveCache - - class MyCacheRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithInclusiveCache( // add 1MB, 4-way, 4-bank cache - capacityKB = 1024, - nWays = 4, - nBanks = 4) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) +Refer to the ``CacheParameters`` object defined in sifive-cache for +customization options. The Broadcast Hub ----------------- @@ -120,28 +120,29 @@ To make such a configuration, you can just copy the definition of ``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the list of included mixims. -.. code-block:: scala - - class CachelessRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) - If you want to reduce the resources used even further, you can configure the Broadcast Hub to use a bufferless design. .. code-block:: scala - import freechips.rocketchip.subsystem.WithBufferlessBroadcastHub + class NoL2SmallRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithBufferlessBroadcastHub ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ + new freechips.rocketchip.system.BaseConfig) - class BufferlessRocketConfig extends Config( - new WithBufferlessBroadcastHub ++ - new CachelessRocketConfig) The Outer Memory System ----------------------- @@ -158,15 +159,9 @@ number of DRAM channels is restricted to powers of two. import freechips.rocketchip.subsystem.WithNMemoryChannels class DualChannelRocketConfig extends Config( - new WithTSI ++ - new WithNoGPIO ++ - new WithBootROM ++ - new WithUART ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new WithNMemoryChannels(2) ++ // multi-channel outer mem - new freechips.rocketchip.subsystem.WithNBigCores(1) ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ + new RocketConfig) + In VCS and Verilator simulation, the DRAM is simulated using the ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 66f8e017..fe126f02 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -9,7 +9,7 @@ To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConf The example Chipyard config includes the following example SoC configuration which includes Gemmini: -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GemminiRocketConfig :end-before: DOC include end: GemminiRocketConfig @@ -42,7 +42,7 @@ Major parameters of interest include: * DMA parameters (``dma_maxbytes``, ``dma_buswidth``, ``mem_pipeline``): Gemmini implements a DMA to move data from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory. The size of these DMA transactions is determined by the DMA parameters. These DMA parameters are tightly coupled with Rocket Chip SoC system parameters: in particular ``dma_buswidth`` is associated with the ``SystemBusKey`` ``beatBytes`` parameter, and ``dma_maxbytes`` is associated with ``cacheblockbytes`` Rocket Chip parameters. -Software +Gemmini Software ------------------ The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__. diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst index 1509b9d7..084a5634 100644 --- a/docs/Generators/Rocket-Chip.rst +++ b/docs/Generators/Rocket-Chip.rst @@ -58,8 +58,8 @@ The ``PeripheryBus`` attaches additional peripherals like the NIC and Block Devi It can also optionally expose an external AXI4 port, which can be attached to vendor-supplied AXI4 IP. -To learn more about adding MMIO peripherals, check out the :ref:`MMIO Peripheral` -section of :ref:`Adding an Accelerator/Device`. +To learn more about adding MMIO peripherals, check out the :ref:`mmio-accelerators` +section. DMA --- @@ -68,5 +68,4 @@ You can also add DMA devices that read and write directly from the memory system. These are attached to the ``FrontendBus``. The ``FrontendBus`` can also connect vendor-supplied AXI4 DMA devices through an AXI4 to TileLink converter. -To learn more about adding DMA devices, see the :ref:`Adding a DMA port` section -of :ref:`Adding an Accelerator/Device`. +To learn more about adding DMA devices, see the :ref:`dma-devices` section. diff --git a/docs/Generators/SHA3.rst b/docs/Generators/SHA3.rst index a9b87108..c8969c3a 100644 --- a/docs/Generators/SHA3.rst +++ b/docs/Generators/SHA3.rst @@ -72,7 +72,7 @@ it can be mixed into a Rocket or BOOM core by overriding the generator. An example configuration highlighting the use of this mixin is shown here: -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: Sha3Rocket :end-before: DOC include end: Sha3Rocket diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index 19360162..35b160f8 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -18,7 +18,7 @@ Peripheral Devices These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. -.. literalinclude:: ../../generators/example/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigMixins.scala :language: scala :start-after: DOC include start: gpio mixin :end-before: DOC include end: gpio mixin @@ -26,12 +26,12 @@ To integrate one of these devices in your SoC, you will need to define a custom Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC. When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. -This example instantiates a top-level module with include GPIO ports (``TopWithGPIO``), and then ties-off the GPIO port inputs to 0 (``false.B``). +This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). Finally, you add the relevant config mixin to the SoC config. For example: -.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GPIORocketConfig :end-before: DOC include end: GPIORocketConfig diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 13b516e3..0e02c077 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -22,9 +22,7 @@ The block device controller provides a generic interface for secondary storage. This device is primarily used in FireSim to interface with a block device software simulation model. The default Linux configuration in `firesim-software `_ -To add a block device to your design, add ``HasPeripheryBlockDevice`` to your -lazy module and ``HasPeripheryBlockDeviceModuleImp`` to the implementation. -Then add the ``WithBlockDevice`` config mixin to your configuration. +To add a block device to your design, add the ``WithBlockDevice`` config mixin to your configuration. TileLink SERDES @@ -71,5 +69,4 @@ during Linux boot). In addition to working with ``stdin/stdout`` of the host, it output a UART log to a particular file using ``+uartlog=`` during simulation. By default, this UART Adapter is added to all systems within Chipyard by adding the -``CanHavePeripheryUARTWithAdapter`` and ``CanHavePeripheryUARTWithAdapterImp`` traits to the ``Top`` system. -These traits add a SiFive UART to the system as well as add the UART Adapter to the TestHarness. +``WithUART`` and ``WithUARTAdapter`` configs. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 5bb5d491..90db4ae8 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -1,6 +1,6 @@ .. _generator-index: -Generators +Included RTL Generators ============================ A Generator can be thought of as a generalized RTL design, written using a mix of meta-programming and standard RTL. diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst deleted file mode 100644 index cc650bd6..00000000 --- a/docs/Quick-Start.rst +++ /dev/null @@ -1,65 +0,0 @@ -Quick Start -=============================== - -Requirements -------------------------------------------- - -Chipyard is developed and tested on Linux-based systems. - -.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. - -.. Warning:: Working under Windows is not recommended. - -Setting up the Chipyard Repo -------------------------------------------- - -Start by fetching Chipyard's sources. Run: - -.. code-block:: shell - - git clone https://github.com/ucb-bar/chipyard.git - cd chipyard - ./scripts/init-submodules-no-riscv-tools.sh - -This will initialize and checkout all of the necessary git submodules. - -Installing the RISC-V Tools -------------------------------------------- - -We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. -This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. -To build the toolchains, you should run: - -.. code-block:: shell - - ./scripts/build-toolchains.sh - -.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. - -Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: - -.. code-block:: shell - - source ./env.sh - -What's Next? -------------------------------------------- - -This depends on what you are planning to do with Chipyard. - -* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. - -* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. - -* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. - -* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. - -* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. - -* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. - -* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. - -* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 4ad0342e..9bc236ac 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -49,16 +49,16 @@ Simulating The Default Example To compile the example design, run ``make`` in the selected verilator or VCS directory. This will elaborate the ``RocketConfig`` in the example project. -An executable called ``simulator-example-RocketConfig`` will be produced. +An executable called ``simulator-chipyard-RocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. You can then use this executable to run any compatible RV64 code. For instance, to run one of the riscv-tools assembly tests. .. code-block:: shell - ./simulator-example-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple + ./simulator-chipyard-RocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple -.. Note:: In a VCS simulator, the simulator name will be ``simv-example-RocketConfig`` instead of ``simulator-example-RocketConfig``. +.. Note:: In a VCS simulator, the simulator name will be ``simv-chipyard-RocketConfig`` instead of ``simulator-chipyard-RocketConfig``. Alternatively, we can run a pre-packaged suite of RISC-V assembly or benchmark tests, by adding the make target ``run-asm-tests`` or ``run-bmark-tests``. For example: diff --git a/docs/Software/FireMarshal.rst b/docs/Software/FireMarshal.rst index dc53b77d..87dede12 100644 --- a/docs/Software/FireMarshal.rst +++ b/docs/Software/FireMarshal.rst @@ -1,4 +1,5 @@ .. _fire-marshal: + FireMarshal ================= diff --git a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst index be3fb33d..ff80f937 100644 --- a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst +++ b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst @@ -17,7 +17,7 @@ The L1 caches and DMA devices in RocketChip/Chipyard have client nodes. You can add a TileLink client node to your LazyModule using the TLHelper object from testchipip like so: -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClient :end-before: DOC include end: MyClient @@ -66,7 +66,7 @@ TileLink managers take requests from clients on the A channel and send responses back on the D channel. You can create a manager node using the TLHelper like so: -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyManager :end-before: DOC include end: MyManager @@ -146,7 +146,7 @@ to the outputs unchanged. This node is mainly used to combine multiple nodes into a single node with multiple edges. For instance, say we have two client lazy modules, each with their own client node. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClient1+MyClient2 :end-before: DOC include end: MyClient1+MyClient2 @@ -154,21 +154,21 @@ client lazy modules, each with their own client node. Now we instantiate these two clients in another lazy module and expose their nodes as a single node. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClientGroup :end-before: DOC include end: MyClientGroup We can also do the same for managers. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyManagerGroup :end-before: DOC include end: MyManagerGroup If we want to connect the client and manager groups together, we can now do this. -.. literalinclude:: ../../generators/example/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala :language: scala :start-after: DOC include start: MyClientManagerComplex :end-before: DOC include end: MyClientManagerComplex diff --git a/docs/TileLink-Diplomacy-Reference/Register-Router.rst b/docs/TileLink-Diplomacy-Reference/Register-Router.rst index cc735578..7e28196f 100644 --- a/docs/TileLink-Diplomacy-Reference/Register-Router.rst +++ b/docs/TileLink-Diplomacy-Reference/Register-Router.rst @@ -11,14 +11,14 @@ for exposing registers themselves, it's much easier to use RocketChip's ``regmap`` interface, which can generate most of the glue logic. For TileLink devices, you can use the ``regmap`` interface by extending -the ``TLRegisterRouter`` class, as shown in :ref:`Adding An Accelerator/Device`, +the ``TLRegisterRouter`` class, as shown in :ref:`mmio-accelerators`, or you can create a regular LazyModule and instantiate a ``TLRegisterNode``. This section will focus on the second method. Basic Usage ----------- -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyDeviceController :end-before: DOC include end: MyDeviceController @@ -56,7 +56,7 @@ register. The ``RegField`` interface also provides support for reading and writing ``DecoupledIO`` interfaces. For instance, you can implement a hardware FIFO like so. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyQueueRegisters :end-before: DOC include end: MyQueueRegisters @@ -71,7 +71,7 @@ You need not specify both read and write for a register. You can also create read-only or write-only registers. So for the previous example, if you wanted enqueue and dequeue to use different addresses, you could write the following. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MySeparateQueueRegisters :end-before: DOC include end: MySeparateQueueRegisters @@ -93,7 +93,7 @@ You can also create registers using functions. Say, for instance, that you want to create a counter that gets incremented on a write and decremented on a read. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyCounterRegisters :end-before: DOC include end: MyCounterRegisters @@ -107,7 +107,7 @@ You can also pass functions that decouple the read/write request and response. The request will appear as a decoupled input and the response as a decoupled output. So for instance, if we wanted to do this for the previous example. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyCounterReqRespRegisters :end-before: DOC include end: MyCounterReqRespRegisters @@ -131,7 +131,7 @@ change the protocol being used. For instance, in the first example in :ref:`Basic Usage`, you could simply change the ``TLRegisterNode`` to and ``AXI4RegisterNode``. -.. literalinclude:: ../../generators/example/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyAXI4DeviceController :end-before: DOC include end: MyAXI4DeviceController diff --git a/docs/TileLink-Diplomacy-Reference/index.rst b/docs/TileLink-Diplomacy-Reference/index.rst index 23a5a175..dfc2ec5a 100644 --- a/docs/TileLink-Diplomacy-Reference/index.rst +++ b/docs/TileLink-Diplomacy-Reference/index.rst @@ -11,7 +11,7 @@ elaboration scheme. For a detailed explanation of Diplomacy, see `the paper by Cook, Terpstra, and Lee `_. A brief overview of how to connect simple TileLink widgets can be found -in the :ref:`Adding-an-Accelerator` section. This section will provide a +in the :ref:`mmio-accelerators` section. This section will provide a detailed reference for the TileLink and Diplomacy functionality provided by RocketChip. diff --git a/docs/Tools/FIRRTL.rst b/docs/Tools/FIRRTL.rst index a434ca0e..e9e6425a 100644 --- a/docs/Tools/FIRRTL.rst +++ b/docs/Tools/FIRRTL.rst @@ -1,4 +1,3 @@ -.. _firrtl: FIRRTL ================================ diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index efe38e34..09fd0d04 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -1,4 +1,4 @@ -Tools +Development Tools ============================== The Chipyard framework relays heavily on a set of Scala-based tools. diff --git a/docs/VLSI/Advanced-Usage.rst b/docs/VLSI/Advanced-Usage.rst index 6ab44c02..b78eda54 100644 --- a/docs/VLSI/Advanced-Usage.rst +++ b/docs/VLSI/Advanced-Usage.rst @@ -49,6 +49,6 @@ Say you need to update some power straps settings in ``example.yml`` and want to make redo-par HAMMER_REDO_ARGS='-p example.yml --only_step power_straps' -Simulation ----------- +RTL and Gate-level Simulation +----------------------------- With the Synopsys plugin, RTL and gate-level simulation is supported using VCS. While this example does not implement any simulation, refer to Hammer's documentation for how to set it up for your design. diff --git a/docs/index.rst b/docs/index.rst index dd7afe52..a98c3088 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -12,8 +12,73 @@ Chipyard is a a framework for designing and evaluating full-system hardware usin It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. -.. include:: Quick-Start.rst +Quick Start +=============================== +System Requirements +------------------------------------------- + +Chipyard is developed and tested on Linux-based systems. + +.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. + +.. Warning:: Working under Windows is not recommended. + +Setting up the Chipyard Repo +------------------------------------------- + +Start by fetching Chipyard's sources. Run: + +.. code-block:: shell + + git clone https://github.com/ucb-bar/chipyard.git + cd chipyard + ./scripts/init-submodules-no-riscv-tools.sh + +This will initialize and checkout all of the necessary git submodules. + +Installing the RISC-V Tools +------------------------------------------- + +We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. +This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. +To build the toolchains, you should run: + +.. code-block:: shell + + ./scripts/build-toolchains.sh + +.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. + +Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: + +.. code-block:: shell + + source ./env.sh + +What's Next? +------------------------------------------- + +This depends on what you are planning to do with Chipyard. + +* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. + +* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. + +* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. + +* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. + +* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. + +* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. + +* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. + +* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. + + Getting Help ------------ From 701ea7c355f221146931d4c33577416cb1d3a435 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 13 Feb 2020 12:31:36 -0800 Subject: [PATCH 016/139] Add new type of IOBinder macro --- .../chipyard/src/main/scala/IOBinders.scala | 36 +++++++++++++++++++ .../src/main/scala/BridgeBinders.scala | 4 +-- 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 969230b7..327db301 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -18,8 +18,31 @@ import tracegen.{HasTraceGenTilesModuleImp} import scala.reflect.{ClassTag, classTag} +// System for instantiating binders based +// on the scala type of the Target (_not_ its IO). This avoids needing to +// duplicate harnesses (essentially test harnesses) for each target. +// +// You could just as well create a custom harness module that instantiates +// bridges explicitly, or add methods to +// your target traits that instantiate the bridge there (i.e., akin to +// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match +// on the types rather than change trait code. + + + +// A map of partial functions that match on the type the DUT (_not_ it's +// IO) to generate an appropriate bridge. You can add your own binder by adding +// a new (key, fn) pair. You should override existing pairs in this map when +// using a custom IOBinder + +// Since we also want to compose this structure like the existing config system, +// use the scala string representation of the matched trait as a key + case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) + +// This macro overrides previous matches on some Top mixin. This is useful for +// binders which modify IO, since those typically cannot be composed class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((clock: Clock, reset: Bool, success: Bool, t: Any) => { @@ -31,6 +54,19 @@ class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit ta ) }) +// This macro composes with previous matches on some Top mixin. This is useful for +// annotation-like binders, since those can typically be composed +class RegisterBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { + case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> + ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + t match { + case top: T => fn(clock, reset, success, top) ++ + up(IOBinders, site).getOrElse(tag.runtimeClass.toString, (c: Clock, r: Bool, s: Bool, t: Any) => Nil)(clock, reset, success, top) + } + }) + ) +}) + class WithGPIOTiedOff extends RegisterIOBinder({ (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil }) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 3005d095..8561d7a1 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -24,7 +24,7 @@ import tracegen.HasTraceGenTilesModuleImp import boom.common.{BoomTile} -import chipyard.iobinders.{IOBinders, RegisterIOBinder} +import chipyard.iobinders.{IOBinders, RegisterIOBinder, RegisterBinder} import chipyard.HasBoomAndRocketTilesModuleImp class WithSerialBridge extends RegisterIOBinder({ @@ -66,7 +66,7 @@ class WithTraceGenBridge extends RegisterIOBinder({ (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) -class WithFireSimMultiCycleRegfile extends RegisterIOBinder({ +class WithFireSimMultiCycleRegfile extends RegisterBinder({ (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { target.outer.tiles.map { case r: RocketTile => { From 941c217fbe2415f6a478f38e2ae854ce37d303d3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Fri, 14 Feb 2020 11:44:10 -0800 Subject: [PATCH 017/139] [ci] Use FireSim's setup script for CI --- .circleci/do-firesim-build.sh | 7 +++++++ .circleci/run-firesim-tests.sh | 9 +++++++++ 2 files changed, 16 insertions(+) diff --git a/.circleci/do-firesim-build.sh b/.circleci/do-firesim-build.sh index 8114355f..709f3d0b 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/do-firesim-build.sh @@ -15,6 +15,13 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh +cd $LOCAL_CHIPYARD_DIR/sims/firesim/sim/firesim-lib/src/main/cc/lib +git submodule update --init elfutils libdwarf +cd $LOCAL_CHIPYARD_DIR/sims/firesim +./scripts/build-libelf.sh +./scripts/build-libdwarf.sh +cd $LOCAL_CHIPYARD_DIR + # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh index 6add6790..8cdf9e81 100755 --- a/.circleci/run-firesim-tests.sh +++ b/.circleci/run-firesim-tests.sh @@ -12,10 +12,19 @@ export FIRESIM_ENV_SOURCED=1 SIMULATION_ARGS="${mapping[$1]}" +cd $LOCAL_CHIPYARD_DIR/sims/firesim +./scripts/build-libelf.sh +./scripts/build-libdwarf.sh +cd $LOCAL_CHIPYARD_DIR + + run_test_suite () { + export RISCV=$LOCAL_RISCV_DIR + export LD_LIBRARY_PATH=$LOCAL_RISCV_DIR/lib make -C $LOCAL_FIRESIM_DIR $SIMULATION_ARGS run-${1}-tests-fast } + run_test_suite bmark run_test_suite nic run_test_suite blockdev From 1f85b2316988c02b65b4188952197e5ea4fffc79 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 18:32:00 +0000 Subject: [PATCH 018/139] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 52aee63b..dbe1ff19 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 52aee63bc04c3769695a41ba18319e316c2e78d5 +Subproject commit dbe1ff19e8b51374791483104076175b1cff03f7 From cc66b9522719a735be564471ad0103bfa39b944b Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 11:40:01 -0800 Subject: [PATCH 019/139] Update Quick-Start.rst --- docs/Quick-Start.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index cc650bd6..16164fdb 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -35,7 +35,7 @@ To build the toolchains, you should run: ./scripts/build-toolchains.sh .. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``ec2fast`` flag for an expedited installation of a pre-compiled toolchain. Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: From 97847b8ef48251b1de25da11314381d8ee343d4d Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 20:09:21 +0000 Subject: [PATCH 020/139] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index dbe1ff19..2b3c64c8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit dbe1ff19e8b51374791483104076175b1cff03f7 +Subproject commit 2b3c64c8faaeb8b2d3c31cdb66204bd1743b8fd5 From aead38ab0b22d6d77571958f3edc363ff83412cd Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Thu, 20 Feb 2020 22:16:09 +0000 Subject: [PATCH 021/139] bump to firesim dev --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 2b3c64c8..0eee2174 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2b3c64c8faaeb8b2d3c31cdb66204bd1743b8fd5 +Subproject commit 0eee217487ba766721a82a442075c52a1bdc2207 From 482c5949d1e5f9939acab17f01adb506bc692f18 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 21 Feb 2020 23:16:03 -0800 Subject: [PATCH 022/139] [ci skip] Fix Typos (#444) --- docs/index.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/index.rst b/docs/index.rst index dd7afe52..02001706 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,8 +8,8 @@ Welcome to Chipyard's documentation! .. image:: ./_static/images/chipyard-logo.svg -Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. -It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. +Chipyard is a framework for designing and evaluating full-system hardware using agile teams. +It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. .. include:: Quick-Start.rst From e40a5541e98809c36b3c0fbcec6fb1a422200448 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 22 Feb 2020 15:38:43 -0800 Subject: [PATCH 023/139] Update Quick-Start.rst --- docs/Quick-Start.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index 16164fdb..b931443c 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -35,7 +35,7 @@ To build the toolchains, you should run: ./scripts/build-toolchains.sh .. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``ec2fast`` flag for an expedited installation of a pre-compiled toolchain. + If you are running on an Amazon Web Services EC2 instance (using the FPGA Developer AMI), intending to use FireSim, you can also use the ``ec2fast`` flag for an expedited installation of a pre-compiled toolchain. Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: From 708a5fb9a610c6f003d3d78f3657cd8f125f879f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 23 Feb 2020 22:53:14 -0800 Subject: [PATCH 024/139] Address generator unification PR reviews --- .gitignore | 1 + docs/Advanced-Concepts/Chip-Communication.rst | 2 +- .../Configs-Parameters-Mixins.rst | 4 +- docs/Customization/IOBinders.rst | 25 +++++ docs/Customization/Memory-Hierarchy.rst | 102 ++---------------- docs/Customization/index.rst | 1 + docs/Makefile | 2 +- .../FPGA-Accelerated-Simulation.rst | 56 +++------- .../chipyard/src/main/scala/IOBinders.scala | 80 +++++++------- .../src/main/scala/RocketConfigs.scala | 6 +- .../src/main/scala/TracegenConfigs.scala | 1 + .../src/main/scala/BridgeBinders.scala | 18 ++-- .../firechip/src/main/scala/FireSim.scala | 38 +++++++ .../src/main/scala/TargetConfigs.scala | 16 +-- .../firechip/src/main/scala/Targets.scala | 43 -------- generators/icenet | 2 +- sims/firesim | 2 +- 17 files changed, 153 insertions(+), 246 deletions(-) create mode 100644 docs/Customization/IOBinders.rst create mode 100644 generators/firechip/src/main/scala/FireSim.scala delete mode 100644 generators/firechip/src/main/scala/Targets.scala diff --git a/.gitignore b/.gitignore index e2c66082..47cb4d87 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ bootrom/* +docs/warnings.txt /Makefrag.pkgs target *.jar diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index fe9b6f57..596ccd6d 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -109,7 +109,7 @@ reminder, to run a software RTL simulation, run: FireSim FPGA-accelerated simulations use TSI by default as well. -If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDTM` instead of `WithTiedOffDebug ++ WithSimSerial`. +If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDebug` instead of `WithTiedOffDebug ++ WithSimSerial`. .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index e72a7444..f490d2a1 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -91,8 +91,8 @@ lazy module implementation performs the actual Chisel RTL elaboration. In the ``Top`` example class, the "outer" ``Top`` instantiates the "inner" ``TopModule`` as a lazy module implementation. This delays immediate elaboration of the module until all logical connections are determined and all configuration information is exchanged. -The ``Syatem`` outer base class, as well as the -``CanHavePeripheryX`` outer traits contain code to perform high-level logical +The ``System`` outer base class, as well as the +``CanHavePeriphery`` outer traits contain code to perform high-level logical connections. For example, the ``CanHavePeripherySerial`` outer trait contains code to optionally lazily instantiate the ``SerialAdapter``, and connect the ``SerialAdapter``'s TileLink node to the Front bus. diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst new file mode 100644 index 00000000..798987b1 --- /dev/null +++ b/docs/Customization/IOBinders.rst @@ -0,0 +1,25 @@ +IOBinders +========= + +In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what modules to bind to the IOs of a ``Top`` in the ``TestHarness``. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala + :language: scala + :start-after: DOC include start: IOBinders + :end-before: DOC include end: IOBinders + + +This special key solves the problem of duplicating test-harnesses for each different ``Top`` type. + +You could just as well create a custom harness module that attaches IOs explicitly. Instead, the IOBinders key provides a map from Scala traits to attachment behaviors. + +For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala + :language: scala + :start-after: DOC include start: WithSimAXIMem + :end-before: DOC include end: WithSimAXIMem + +These classes are all ``Config`` objects, which can be mixed into the configs to specify IO connection behaviors. + +There are two macros for generating these ``Configs``. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 26bce436..99cc9f77 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -9,89 +9,30 @@ The L1 Caches Each CPU tile has an L1 instruction cache and L1 data cache. The size and associativity of these caches can be configured. The default ``RocketConfig`` uses 16 KiB, 4-way set-associative instruction and data caches. However, -if you use the ``NMedCores`` or ``NSmallCores`` configurations, you can +if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can configure 4 KiB direct-mapped caches for L1I and L1D. -.. code-block:: scala - - class SmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores - new freechips.rocketchip.system.BaseConfig) - - class MediumRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNMediumCores(1) ++ // Medium rocket cores - new freechips.rocketchip.system.BaseConfig) - - - If you only want to change the size or associativity, there are configuration -mixins for those too. +mixins for those too. See :ref:`Mixins` for how to add these to a custom ``Config`` .. code-block:: scala - import freechips.rocketchip.subsystem.{WithL1ICacheSets, WithL1DCacheSets, WithL1ICacheWays, WithL1DCacheWays} - - class MyL1RocketConfig extends Config( new freechips.rocketchip.subsystem.WithL1ICacheSets(128) ++ // change rocket I$ new freechips.rocketchip.subsystem.WithL1ICacheWays(2) ++ // change rocket I$ new freechips.rocketchip.subsystem.WithL1DCacheSets(128) ++ // change rocket D$ new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++ // change rocket D$ - new RocketConfig) + You can also configure the L1 data cache as an data scratchpad instead. However, there are some limitations on this. If you are using a data scratchpad, you can only use a single core and you cannot give the design an external DRAM. Note that these configurations fully remove the L2 cache and mbus. -.. code-block:: scala - class ScratchpadSmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) +.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala + :language: scala + :start-after: DOC include start: scratchpadrocket + :end-before: DOC include end: scratchpadrocket This configuration fully removes the L2 cache and memory bus by setting the @@ -121,27 +62,8 @@ To make such a configuration, you can just copy the definition of list of included mixims. If you want to reduce the resources used even further, you can configure -the Broadcast Hub to use a bufferless design. - -.. code-block:: scala - - class NoL2SmallRocketConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new chipyard.config.WithL2TLBs(1024) ++ - new freechips.rocketchip.subsystem.WithBufferlessBroadcastHub ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ - new freechips.rocketchip.system.BaseConfig) +the Broadcast Hub to use a bufferless design. This mixin is +``freechips.rocketchip.subsystem.WithBufferlessBroadcastHub``. The Outer Memory System @@ -156,11 +78,7 @@ number of DRAM channels is restricted to powers of two. .. code-block:: scala - import freechips.rocketchip.subsystem.WithNMemoryChannels - - class DualChannelRocketConfig extends Config( - new freechips.rocketchip.subsystem.WithNMemoryChannels(2) ++ - new RocketConfig) + new freechips.rocketchip.subsystem.WithNMemoryChannels(2) In VCS and Verilator simulation, the DRAM is simulated using the diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index c5ec5778..496f4c0a 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -42,3 +42,4 @@ We recommend reading all these pages in order. Hit next to get started! Memory-Hierarchy Boot-Process Firrtl-Transforms + IOBinders diff --git a/docs/Makefile b/docs/Makefile index adea9f26..fe9f0963 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -2,7 +2,7 @@ # # You can set these variables from the command line. -SPHINXOPTS = +SPHINXOPTS = -w warnings.txt SPHINXBUILD = python -msphinx SPHINXPROJ = Chipyard SOURCEDIR = . diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 6964ee57..89c0a939 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -44,47 +44,19 @@ familiar with FireSim, please return to the `FireSim Docs `__, and proceed with the rest of the tutorial. -Current Limitations: -++++++++++++++++++++ - -FireSim integration in Chipyard is still a work in progress. Presently, you -cannot build a FireSim simulator from any generator project in Chipyard except ``firechip``, -which properly invokes MIDAS on the target RTL. - -In the interim, workaround this limitation by importing Config and Module -classes from other generator projects into FireChip. For example, assuming you Chipyard -config looks as following: - -.. code-block:: scala - - class CustomConfig extends Config( - new WithInclusiveCache ++ - new myproject.MyCustomConfig ++ - new DefaultRocketConfig - ) - -Then the equivalent FireChip config (in ``generators/firechip/src/main/scala/TargetConfigs.scala``) based on ``FireSimRocketChipConfig`` -will look as follows: - -.. code-block:: scala - - class FireSimCustomConfig extends Config( - new WithBootROM ++ - new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ - new WithExtMemSize(0x400000000L) ++ // 16GB - new WithoutTLMonitors ++ - new WithUARTKey ++ - new WithNICKey ++ - new WithBlockDevice ++ - new WithRocketL2TLBs(1024) ++ - new WithPerfCounters ++ - new WithoutClockGating ++ - new WithInclusiveCache ++ - new myproject.MyCustomConfig ++ - new freechips.rocketchip.system.DefaultConfig) +Running your Design in FireSim +------------------------------ +Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireSim is simple. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. -You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` -variables. Note that if your target machine has I/O not provided in the default -FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need -to write a custom bridge. +.. literalinclude:: ../../generators/firechip/src/main/scala/TargetConfigs.scala + :language: scala + :start-after: DOC include start: firesimconfig + :end-before: DOC include end: firesimconfig + + +Only 3 additional config-mixins are needed. + +* ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. +* ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documnetation for details. diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 327db301..22715aaf 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -16,34 +16,29 @@ import testchipip._ import icenet._ import tracegen.{HasTraceGenTilesModuleImp} -import scala.reflect.{ClassTag, classTag} +import scala.reflect.{ClassTag} // System for instantiating binders based // on the scala type of the Target (_not_ its IO). This avoids needing to // duplicate harnesses (essentially test harnesses) for each target. -// -// You could just as well create a custom harness module that instantiates -// bridges explicitly, or add methods to -// your target traits that instantiate the bridge there (i.e., akin to -// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match -// on the types rather than change trait code. +// IOBinders is map between string representations of traits to the desired +// IO connection behavior for tops matching that trait. We use strings to enable +// composition and overriding of IOBinders, much like how normal Keys in the config +// system are used/ At elaboration, the testharness traverses this set of functions, +// and functions which match the type of the Top are evaluated. +// You can add your own binder by adding a new (key, fn) pair, typically by using +// the OverrideIOBinder or ComposeIOBinder macros -// A map of partial functions that match on the type the DUT (_not_ it's -// IO) to generate an appropriate bridge. You can add your own binder by adding -// a new (key, fn) pair. You should override existing pairs in this map when -// using a custom IOBinder - -// Since we also want to compose this structure like the existing config system, -// use the scala string representation of the matched trait as a key - -case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]](Map()) - +// DOC include start: IOBinders +case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]]( + Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]().withDefaultValue((c: Clock, r: Bool, s: Bool, t: Any) => Nil) +) // This macro overrides previous matches on some Top mixin. This is useful for -// binders which modify IO, since those typically cannot be composed -class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +// binders which drive IO, since those typically cannot be composed +class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((clock: Clock, reset: Bool, success: Bool, t: Any) => { t match { @@ -56,34 +51,41 @@ class RegisterIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit ta // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class RegisterBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> ((clock: Clock, reset: Bool, success: Bool, t: Any) => { t match { - case top: T => fn(clock, reset, success, top) ++ - up(IOBinders, site).getOrElse(tag.runtimeClass.toString, (c: Clock, r: Bool, s: Bool, t: Any) => Nil)(clock, reset, success, top) + case top: T => (up(IOBinders, site)(tag.runtimeClass.toString)(clock, reset, success, top) + ++ fn(clock, reset, success, top)) + case _ => Nil } }) ) }) -class WithGPIOTiedOff extends RegisterIOBinder({ +// DOC include end: IOBinders + +class WithGPIOTiedOff extends OverrideIOBinder({ (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil }) -class WithSimBlockDevice extends RegisterIOBinder({ +class WithSimBlockDevice extends OverrideIOBinder({ (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil }) -class WithBlockDeviceModel extends RegisterIOBinder({ +class WithBlockDeviceModel extends OverrideIOBinder({ (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil }) -class WithLoopbackNIC extends RegisterIOBinder({ +class WithLoopbackNIC extends OverrideIOBinder({ (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil }) -class WithUARTAdapter extends RegisterIOBinder({ +class WithSimNIC extends OverrideIOBinder({ + (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectSimNetwork(c, r); Nil +}) + +class WithUARTAdapter extends OverrideIOBinder({ (c, r, s, top: HasPeripheryUARTModuleImp) => { val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate top.uart.zipWithIndex.foreach{ case (dut_io, i) => @@ -95,23 +97,25 @@ class WithUARTAdapter extends RegisterIOBinder({ } }) -class WithSimAXIMem extends RegisterIOBinder({ +// DOC include start: WithSimAXIMem +class WithSimAXIMem extends OverrideIOBinder({ (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil }) +// DOC include end: WithSimAXIMem -class WithSimAXIMMIO extends RegisterIOBinder({ +class WithSimAXIMMIO extends OverrideIOBinder({ (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil }) -class WithDontTouchPorts extends RegisterIOBinder({ +class WithDontTouchPorts extends OverrideIOBinder({ (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil }) -class WithTieOffInterrupts extends RegisterIOBinder({ +class WithTieOffInterrupts extends OverrideIOBinder({ (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil }) -class WithTieOffL2FBusAXI extends RegisterIOBinder({ +class WithTieOffL2FBusAXI extends OverrideIOBinder({ (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { top.l2_frontend_bus_axi4.foreach(axi => { axi.tieoff() @@ -129,7 +133,7 @@ class WithTieOffL2FBusAXI extends RegisterIOBinder({ } }) -class WithTiedOffDebug extends RegisterIOBinder({ +class WithTiedOffDebug extends OverrideIOBinder({ (c, r, s, top: HasPeripheryDebugModuleImp) => { Debug.tieoffDebug(top.debug, top.psd) // tieoffDebug doesn't actually tie everything off :/ @@ -138,7 +142,7 @@ class WithTiedOffDebug extends RegisterIOBinder({ } }) -class WithSimSerial extends RegisterIOBinder({ +class WithSimSerial extends OverrideIOBinder({ (c, r, s, top: CanHavePeripherySerialModuleImp) => { val ser_success = top.connectSimSerial() when (ser_success) { s := true.B } @@ -146,12 +150,12 @@ class WithSimSerial extends RegisterIOBinder({ } }) -class WithTiedOffSerial extends RegisterIOBinder({ +class WithTiedOffSerial extends OverrideIOBinder({ (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil }) -class WithSimDTM extends RegisterIOBinder({ +class WithSimDebug extends OverrideIOBinder({ (c, r, s, top: HasPeripheryDebugModuleImp) => { val dtm_success = Wire(Bool()) top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) @@ -162,6 +166,6 @@ class WithSimDTM extends RegisterIOBinder({ }) -class WithTraceGenSuccessBinder extends RegisterIOBinder({ - (c, r, s, top: HasTraceGenTilesModuleImp) => s := top.success; Nil +class WithTraceGenSuccessBinder extends OverrideIOBinder({ + (c, r, s, top: HasTraceGenTilesModuleImp) => when (top.success) { s := true.B }; Nil }) diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index 6066f86f..2e0f856a 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -90,7 +90,7 @@ class jtagRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithSimAXIMem ++ - new chipyard.iobinders.WithSimDTM ++ // add SimJtag and SimSerial, use both to drive sim + new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new chipyard.config.WithNoGPIO ++ @@ -112,7 +112,7 @@ class dmiRocketConfig extends Config( new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithSimAXIMem ++ new chipyard.iobinders.WithTiedOffSerial ++ - new chipyard.iobinders.WithSimDTM ++ // add SimDTM and use it to drive simulation + new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ @@ -345,6 +345,7 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include start: scratchpadrocket class ScratchpadRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ @@ -363,3 +364,4 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include end: scratchpadrocket diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala index 0e3457f0..1e9be623 100644 --- a/generators/chipyard/src/main/scala/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -24,6 +24,7 @@ class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 8561d7a1..9a19e6ef 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -24,26 +24,26 @@ import tracegen.HasTraceGenTilesModuleImp import boom.common.{BoomTile} -import chipyard.iobinders.{IOBinders, RegisterIOBinder, RegisterBinder} +import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.HasBoomAndRocketTilesModuleImp -class WithSerialBridge extends RegisterIOBinder({ +class WithSerialBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq }) -class WithNICBridge extends RegisterIOBinder({ +class WithNICBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq }) -class WithUARTBridge extends RegisterIOBinder({ +class WithUARTBridge extends OverrideIOBinder({ (c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq }) -class WithBlockDeviceBridge extends RegisterIOBinder({ +class WithBlockDeviceBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq }) -class WithFASEDBridge extends RegisterIOBinder({ +class WithFASEDBridge extends OverrideIOBinder({ (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -58,15 +58,15 @@ class WithFASEDBridge extends RegisterIOBinder({ } }) -class WithTracerVBridge extends RegisterIOBinder({ +class WithTracerVBridge extends OverrideIOBinder({ (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq }) -class WithTraceGenBridge extends RegisterIOBinder({ +class WithTraceGenBridge extends OverrideIOBinder({ (c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p)) }) -class WithFireSimMultiCycleRegfile extends RegisterBinder({ +class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { target.outer.tiles.map { case r: RocketTile => { diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala new file mode 100644 index 00000000..884dbbf3 --- /dev/null +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -0,0 +1,38 @@ +//See LICENSE for license details. + +package firesim.firesim + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule} + +import midas.widgets.{Bridge, PeekPokeBridge} + +import chipyard.{BuildTop} +import chipyard.iobinders.{IOBinders} + +// Determines the number of times to instantiate the DUT in the harness. +// Subsumes legacy supernode support +case object NumNodes extends Field[Int](1) + +class WithNumNodes(n: Int) extends Config((pname, site, here) => { + case NumNodes => n +}) + +class FireSim(implicit val p: Parameters) extends RawModule { + val clock = IO(Input(Clock())) + val reset = WireInit(false.B) + withClockAndReset(clock, reset) { + // Instantiate multiple instances of the DUT to implement supernode + val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val peekPokeBridge = PeekPokeBridge(reset) + // A Seq of partial functions that will instantiate the right bridge only + // if that Mixin trait is present in the target's class instance + // + // Apply each partial function to each DUT instance + for ((target) <- targets) { + p(IOBinders).values.map(fn => fn(false.B, target)) + } + } +} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 11916662..dcc5be90 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -21,7 +21,6 @@ import tracegen.TraceGenKey import icenet._ import firesim.bridges._ -import firesim.util.{WithNumNodes} import firesim.configs._ import chipyard.{BuildTop} import chipyard.config.ConfigValName._ @@ -106,11 +105,13 @@ class WithFireSimConfigTweaks extends Config( //***************************************************************** // Rocket configs, base off chipyard's RocketConfig //***************************************************************** +// DOC include start: firesimconfig class FireSimRocketConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ new chipyard.RocketConfig) +// DOC include end: firesimconfig class FireSimQuadRocketConfig extends Config( new WithDefaultFireSimBridges ++ @@ -119,19 +120,6 @@ class FireSimQuadRocketConfig extends Config( new chipyard.QuadRocketConfig) -//***************************************************************** -// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig -//***************************************************************** -class FireSimSha3RocketConfig extends Config( - new WithDefaultFireSimBridges ++ - new WithDefaultMemModel ++ - new WithFireSimConfigTweaks ++ - new chipyard.Sha3RocketConfig) - -class FireSimSha3PrintfRocketConfig extends Config( - new sha3.WithSha3Printf ++ - new FireSimSha3RocketConfig) - //***************************************************************** // Boom config, base off chipyard's LargeBoomConfig //***************************************************************** diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala deleted file mode 100644 index 6961782a..00000000 --- a/generators/firechip/src/main/scala/Targets.scala +++ /dev/null @@ -1,43 +0,0 @@ -package firesim.firesim - -import chisel3._ -import freechips.rocketchip._ -import freechips.rocketchip.subsystem._ -import freechips.rocketchip.diplomacy._ -import freechips.rocketchip.tilelink._ -import freechips.rocketchip.devices.tilelink._ -import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.util.{HeterogeneousBag} -import freechips.rocketchip.amba.axi4.AXI4Bundle -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.diplomacy.LazyModule -import icenet._ -import firesim.util.DefaultFireSimHarness -import testchipip._ -import testchipip.SerialAdapter.SERIAL_IF_WIDTH -import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp} -import sifive.blocks.devices.uart._ -import java.io.File - - -object FireSimValName { - implicit val valName = ValName("FireSimHarness") -} -import FireSimValName._ - - - -/******************************************************************************* -* Top level DESIGN configurations. These describe the basic instantiations of -* the designs being simulated. -* -* In general, if you're adding or removing features from any of these, you -* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager -* will store this name as part of the tags for the AGFI, so that later you can -* reconstruct what is in a particular AGFI. These tags are also used to -* determine which driver to build. -*******************************************************************************/ - - -class FireSim(implicit p: Parameters) extends DefaultFireSimHarness diff --git a/generators/icenet b/generators/icenet index 4980d3a3..e235801c 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 4980d3a311e487419f2e6358d678c18b7ff3ffe4 +Subproject commit e235801c4c7088a303dd2136e02fb9548b4ec2f8 diff --git a/sims/firesim b/sims/firesim index c771d114..59885ac8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit c771d1143a98dd19f1c4a842cc8a572b5e54de98 +Subproject commit 59885ac828e5433ae6fea7490a7c100a6ea63155 From 43086465a8c96eb0d8d35ab7d6c394b223a820f9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 24 Feb 2020 16:09:34 -0800 Subject: [PATCH 025/139] Bump FireSim for naming changes --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 89c0a939..1b7e47bb 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -59,4 +59,4 @@ Only 3 additional config-mixins are needed. * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. -* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documnetation for details. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documentation for details. diff --git a/sims/firesim b/sims/firesim index 59885ac8..70fc4325 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 59885ac828e5433ae6fea7490a7c100a6ea63155 +Subproject commit 70fc43259b8f66e42ef682c17183dff5f16228bf From e206917b56fc5f087820a55c6d9bb90a2ca4694a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 25 Feb 2020 13:23:49 -0800 Subject: [PATCH 026/139] Bump firesim --- docs/Simulation/FPGA-Accelerated-Simulation.rst | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 1b7e47bb..ea4f3297 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -59,4 +59,4 @@ Only 3 additional config-mixins are needed. * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. -* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSIm documentation for details. +* ``WithDefaultFireSimBridges`` sets the ``IOBinders`` key to use FireSim's Bridge system, which can drive target IOs with software bridge models running on the simulation host. See the FireSim documentation for details. diff --git a/sims/firesim b/sims/firesim index 70fc4325..1c7caed6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 70fc43259b8f66e42ef682c17183dff5f16228bf +Subproject commit 1c7caed637a64a231905af9aea2148be60add16b From de2170e7a67badbc134ab2eb3ef071f9b88b79b1 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 25 Feb 2020 21:27:53 -0800 Subject: [PATCH 027/139] [setup] log init submodules (#433) --- .../init-submodules-no-riscv-tools-nolog.sh | 64 +++++++++++++++++++ scripts/init-submodules-no-riscv-tools.sh | 61 +----------------- 2 files changed, 67 insertions(+), 58 deletions(-) create mode 100755 scripts/init-submodules-no-riscv-tools-nolog.sh diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh new file mode 100755 index 00000000..ed4f5b6a --- /dev/null +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -0,0 +1,64 @@ +#!/usr/bin/env bash + +# exit script if any command fails +set -e +set -o pipefail + +RDIR=$(git rev-parse --show-toplevel) + +# Ignore toolchain submodules +cd "$RDIR" +for name in toolchains/*-tools/*/ ; do + git config submodule."${name%/}".update none +done +git config submodule.toolchains/libgloss.update none +git config submodule.toolchains/qemu.update none + +# Don't automatically initialize generators with big submodules (e.g. linux source) +git config submodule.generators/sha3.update none + +# Disable updates to the FireSim submodule until explicitly requested +git config submodule.sims/firesim.update none +# Disable updates to the hammer tool plugins repos +git config submodule.vlsi/hammer-cadence-plugins.update none +git config submodule.vlsi/hammer-synopsys-plugins.update none +git config submodule.vlsi/hammer-mentor-plugins.update none +git config submodule.software/firemarshal.update none +git submodule update --init --recursive #--jobs 8 + +# Un-ignore toolchain submodules +for name in toolchains/*-tools/*/ ; do + git config --unset submodule."${name%/}".update +done +git config --unset submodule.toolchains/libgloss.update +git config --unset submodule.toolchains/qemu.update + +git config --unset submodule.vlsi/hammer-cadence-plugins.update +git config --unset submodule.vlsi/hammer-synopsys-plugins.update +git config --unset submodule.vlsi/hammer-mentor-plugins.update + +git config --unset submodule.generators/sha3.update +git config --unset submodule.software/firemarshal.update + +# Non-recursive clone to exclude riscv-linux +git submodule update --init generators/sha3 + +git config --unset submodule.sims/firesim.update +# Minimal non-recursive clone to initialize sbt dependencies +git submodule update --init sims/firesim +( + cd sims/firesim + # Initialize dependencies for MIDAS-level RTL simulation + git submodule update --init sim/midas +) +git config submodule.sims/firesim.update none + +# Only shallow clone needed for basic SW tests +git submodule update --init software/firemarshal + +# Configure firemarshal to know where our firesim installation is +if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then + echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml +fi +echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh + diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index c4716ce4..550d8846 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -1,63 +1,8 @@ #!/usr/bin/env bash -# exit script if any command fails +# wrapper to log output from init-submodules script + set -e set -o pipefail -RDIR=$(git rev-parse --show-toplevel) - -# Ignore toolchain submodules -cd "$RDIR" -for name in toolchains/*-tools/*/ ; do - git config submodule."${name%/}".update none -done -git config submodule.toolchains/libgloss.update none -git config submodule.toolchains/qemu.update none - -# Don't automatically initialize generators with big submodules (e.g. linux source) -git config submodule.generators/sha3.update none - -# Disable updates to the FireSim submodule until explicitly requested -git config submodule.sims/firesim.update none -# Disable updates to the hammer tool plugins repos -git config submodule.vlsi/hammer-cadence-plugins.update none -git config submodule.vlsi/hammer-synopsys-plugins.update none -git config submodule.vlsi/hammer-mentor-plugins.update none -git config submodule.software/firemarshal.update none -git submodule update --init --recursive #--jobs 8 - -# Un-ignore toolchain submodules -for name in toolchains/*-tools/*/ ; do - git config --unset submodule."${name%/}".update -done -git config --unset submodule.toolchains/libgloss.update -git config --unset submodule.toolchains/qemu.update - -git config --unset submodule.vlsi/hammer-cadence-plugins.update -git config --unset submodule.vlsi/hammer-synopsys-plugins.update -git config --unset submodule.vlsi/hammer-mentor-plugins.update - -git config --unset submodule.generators/sha3.update -git config --unset submodule.software/firemarshal.update - -# Non-recursive clone to exclude riscv-linux -git submodule update --init generators/sha3 - -git config --unset submodule.sims/firesim.update -# Minimal non-recursive clone to initialize sbt dependencies -git submodule update --init sims/firesim -( - cd sims/firesim - # Initialize dependencies for MIDAS-level RTL simulation - git submodule update --init sim/midas -) -git config submodule.sims/firesim.update none - -# Only shallow clone needed for basic SW tests -git submodule update --init software/firemarshal - -# Configure firemarshal to know where our firesim installation is -if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then - echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml -fi -echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh +./scripts/init-submodules-no-riscv-tools-nolog.sh "$@" 2>&1 | tee init-submodules-no-riscv-tools.log From b6faed283a55b4f2acd484bdc90a102210b56c30 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 26 Feb 2020 05:20:54 -0800 Subject: [PATCH 028/139] Bump barstools to fix #428 (#447) barstools is now compatible with chisel 3.2.x --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 5198b388..63d74bc1 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 5198b3883c8dfb744c24e7586eec5c9e80a8dd68 +Subproject commit 63d74bc177cb070126eb0e662ff0ea500722a8d7 From 01238c8b7a5945dd437bcd407534839f574bb9df Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 27 Feb 2020 09:31:08 -0800 Subject: [PATCH 029/139] Rename Config Mixins to Fragments (#451) * [docs] rename config mixins -> fragments [ci skip] * [docs] cleanup naming | link similar sections [ci skip] * [boom] bump for mixin rename [ci skip] * [docs] cleanup capitalization [ci skip] * [docs] consistent config fragment naming [ci skip] * [boom] bump boom for documentation changes [ci skip] * [docs] update source comments [ci skip] * [docs] fix last config fragment name [ci skip] Co-Authored-By: alonamid Co-authored-by: alonamid --- docs/Advanced-Concepts/CDEs.rst | 8 ++--- docs/Advanced-Concepts/Chip-Communication.rst | 4 +-- docs/Advanced-Concepts/Top-Testharness.rst | 2 +- docs/Advanced-Concepts/index.rst | 2 +- .../Configs-Parameters-Mixins.rst | 34 +++++++++---------- docs/Customization/Heterogeneous-SoCs.rst | 30 ++++++++-------- docs/Customization/IOBinders.rst | 2 +- docs/Customization/Keys-Traits-Configs.rst | 20 +++++------ docs/Customization/MMIO-Peripherals.rst | 6 ++-- docs/Customization/Memory-Hierarchy.rst | 10 +++--- docs/Customization/index.rst | 2 +- docs/Generators/Gemmini.rst | 12 +++---- docs/Generators/Hwacha.rst | 4 +-- docs/Generators/IceNet.rst | 6 ++-- docs/Generators/SHA3.rst | 4 +-- docs/Generators/SiFive-Generators.rst | 14 ++++---- docs/Generators/TestChipIP.rst | 2 +- .../FPGA-Accelerated-Simulation.rst | 2 +- docs/Simulation/Software-RTL-Simulation.rst | 2 +- generators/boom | 2 +- ...nfigMixins.scala => ConfigFragments.scala} | 12 +++---- generators/chipyard/src/main/scala/GCD.scala | 4 +-- 22 files changed, 91 insertions(+), 93 deletions(-) rename generators/chipyard/src/main/scala/{ConfigMixins.scala => ConfigFragments.scala} (92%) diff --git a/docs/Advanced-Concepts/CDEs.rst b/docs/Advanced-Concepts/CDEs.rst index b8e130e6..6904106e 100644 --- a/docs/Advanced-Concepts/CDEs.rst +++ b/docs/Advanced-Concepts/CDEs.rst @@ -28,11 +28,11 @@ Consider the following example using CDEs. } -When forming a query based on a ``Parameters`` object, like ``p(SomeKeyX)``, the configuration system traverses the "chain" of mixins until it finds a partial function which is defined at the key, and then returns that value. +When forming a query based on a ``Parameters`` object, like ``p(SomeKeyX)``, the configuration system traverses the "chain" of config fragments until it finds a partial function which is defined at the key, and then returns that value. .. code:: scala - val params = Config(new WithX(true) ++ new WithY(true)) // "chain" together mixins + val params = Config(new WithX(true) ++ new WithY(true)) // "chain" together config fragments params(SomeKeyX) // evaluates to true params(SomeKeyY) // evaluates to true params(SomeKeyZ) // evaluates to false @@ -68,7 +68,7 @@ In this example, the partial function in ``WithXEqualsYSite`` will look up the v Here ~~~~ -``here`` provides a ``View`` of the locally defined Config, which typically just contains some partial function. +``here`` provides a ``View`` of the locally defined config, which typically just contains some partial function. .. code:: scala @@ -103,7 +103,7 @@ Up params_1(SomeKeyX) // evaluates to true params_2(SomeKeyX) // evaluates to false -In this example, note how ``up(SomeKeyY, site)`` in ``WithXEqualsYUp`` will refer to *either* the the partial function defining ``SomeKeyY`` in ``WithY(true)`` *or* the default value for ``SomeKeyY`` provided in the original ``case object SomeKeyY`` definition, *depending on the order in which the mixins were used*. Since the order of mixins affects the the order of the ``View`` traversal, ``up`` provides a different ``View`` of the parameterization in ``params_1`` and ``params_2``. +In this example, note how ``up(SomeKeyY, site)`` in ``WithXEqualsYUp`` will refer to *either* the the partial function defining ``SomeKeyY`` in ``WithY(true)`` *or* the default value for ``SomeKeyY`` provided in the original ``case object SomeKeyY`` definition, *depending on the order in which the config fragments were used*. Since the order of config fragments affects the the order of the ``View`` traversal, ``up`` provides a different ``View`` of the parameterization in ``params_1`` and ``params_2``. Also note that again, ``site`` must be recursively passed through the call to ``up``. diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index 596ccd6d..eff08670 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -81,7 +81,7 @@ Similar to TSI, the DMI protocol is an implementation of HTIF. In order to communicate with the DUT with the DMI protocol, the DUT needs to contain a Debug Transfer Module (DTM). The DTM is given in the `RISC-V Debug Specification `__ and is responsible for managing communication between the DUT and whatever lives on the other side of the DMI (in this case FESVR). -This is implemented in the Rocket Chip ``Subsystem`` by having the ``HasPeripheryDebug`` and ``HasPeripheryDebugModuleImp`` mixins. +This is implemented in the Rocket Chip ``Subsystem`` by having the ``HasPeripheryDebug`` and ``HasPeripheryDebugModuleImp`` traits. During simulation, the host sends DMI commands to a simulation stub called ``SimDTM`` (C++ class) that resides in a ``SimDTM`` Verilog module (both are located in the ``generators/rocket-chip`` project). This ``SimDTM`` Verilog module then @@ -138,7 +138,7 @@ Creating a DTM+JTAG Config First, a DTM config must be created for the system that you want to create. This step is similar to the DMI simulation section within the :ref:`Starting the TSI or DMI Simulation` section. The configuration is very similar to a DMI-based configuration. The main difference -is the addition of the ``WithJtagDTM`` mixin that configures the instantiated DTM to use the JTAG protocol as the +is the addition of the ``WithJtagDTM`` config fragment that configures the instantiated DTM to use the JTAG protocol as the bringup method. .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 43b0be51..8df37769 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -52,7 +52,7 @@ Please refer to :ref:`Communicating with the DUT` for more information on these TestHarness ------------------------- -The wiring between the ``TestHarness`` and the Top are performed in methods defined in mixins added to the Top. +The wiring between the ``TestHarness`` and the Top are performed in methods defined in traits added to the Top. When these methods are called from the ``TestHarness``, they may instantiate modules within the scope of the harness, and then connect them to the DUT. For example, the ``connectSimAXIMem`` method defined in the ``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMems`` diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index af23525a..c13e569b 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -2,7 +2,7 @@ Advanced Concepts ================================ The following sections are advanced topics about how to Chipyard works, how to use Chipyard, and special features of the framework. -They expect you to know about Chisel, Parameters, Configs, etc. +They expect you to know about Chisel, Parameters, configs, etc. .. toctree:: :maxdepth: 2 diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index f490d2a1..9d7d86d0 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -1,4 +1,4 @@ -Configs, Parameters, Mix-ins, and Everything In Between +Configs, Parameters, Mixins, and Everything In Between ======================================================== A significant portion of generators in the Chipyard framework use the Rocket Chip parameter system. @@ -14,12 +14,12 @@ We are still investigating methods to facilitate parameter exploration and disco Configs --------------------- -A *Config* is a collection of multiple generator parameters being set to specific values. -Configs are additive, can override each other, and can be composed of other Configs. -The naming convention for an additive Config is ``With``, while the naming convention for a non-additive Config will be ````. +A *config* is a collection of multiple generator parameters being set to specific values. +Configs are additive, can override each other, and can be composed of other configs (sometimes referred to as config fragments). +The naming convention for an additive config or config fragment is ``With``, while the naming convention for a non-additive config will be ````. Configs can take arguments which will in-turn set parameters in the design or reference other parameters in the design (see :ref:`Parameters`). -This example shows a basic additive Config class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. +This example shows a basic config fragment class that takes in zero arguments and instead uses hardcoded values to set the RTL design parameters. In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a set of variables that the generator can use when referencing the ``MyAcceleratorKey`` in the design. .. _basic-config-example: @@ -36,7 +36,7 @@ In this example, ``MyAcceleratorConfig`` is a Scala case class that defines a se someLength = 256) }) -This next example shows a "higher-level" additive Config that uses prior parameters that were set to derive other parameters. +This next example shows a "higher-level" additive config fragment that uses prior parameters that were set to derive other parameters. .. _complex-config-example: .. code-block:: scala @@ -50,8 +50,8 @@ This next example shows a "higher-level" additive Config that uses prior paramet hartId = up(RocketTilesKey, site).length) }) -The following example shows a non-additive Config that combines the prior two additive Configs using ``++``. -The additive Configs are applied from the right to left in the list (or bottom to top in the example). +The following example shows a non-additive config that combines or "assembles" the prior two config fragments using ``++``. +The additive config fragments are applied from the right to left in the list (or bottom to top in the example). Thus, the order of the parameters being set will first start with the ``DefaultExampleConfig``, then ``WithMyAcceleratorParams``, then ``WithMyMoreComplexAcceleratorConfig``. .. _top-level-config: @@ -68,10 +68,10 @@ The ``site`` map gives you the definitions as seen from the root of the configur The ``here`` map gives the definitions as seen at the current level of the hierarchy (i.e. in ``WithMyMoreComplexAcceleratorConfig`` itself). The ``up`` map gives the definitions as seen from the next level up from the current (i.e. from ``WithMyAcceleratorParams``). -Cake Pattern +Cake Pattern / Mixin ------------------------- -A cake pattern is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). +A cake pattern or mixin is a Scala programming pattern, which enable "mixing" of multiple traits or interface definitions (sometimes referred to as dependency injection). It is used in the Rocket Chip SoC library and Chipyard framework in merging multiple system components and IO interfaces into a large system component. This example shows the Chipyard default top that composes multiple traits together into a fully-featured SoC with many optional components. @@ -83,7 +83,7 @@ This example shows the Chipyard default top that composes multiple traits togeth :end-before: DOC include end: Top -There are two "cakes" here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module +There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to implementation). The lazy module defines all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. @@ -114,15 +114,13 @@ contain the implementation for the module, and may instantiate other normal modules OR lazy modules (for nested Diplomacy graphs, for example). - -Mix-in ---------------------------- - -A mix-in is a Scala trait, which sets parameters for specific system components, as well as enabling instantiation and wiring of the relevant system components to system buses. -The naming convention for an additive mix-in is ``CanHave``. +The naming convention for an additive mixin or trait is ``CanHave``. This is shown in the ``Top`` class where things such as ``CanHavePeripherySerial`` connect a RTL component to a bus and expose signals to the top-level. Additional References --------------------------- -A brief explanation of some of these topics is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. +Another description of traits/mixins and config fragments is given in :ref:`Keys, Traits, and Configs`. +Additionally, a brief explanation of some of these topics (with slightly different naming) is given in the following video: https://www.youtube.com/watch?v=Eko86PGEoDY. + +.. Note:: Chipyard uses the name "config fragments" over "config mixins" to avoid confusion between a mixin applying to a config or to the system ``Top`` (even though both are technically Scala mixins). diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 8087fd35..6385f3b3 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -7,8 +7,8 @@ This discussion will focus on how you combine Rocket, BOOM and Hwacha in particu Creating a Rocket and BOOM System ------------------------------------------- -Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific mixins. -Both BOOM and Rocket have mixins labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_. +Instantiating an SoC with Rocket and BOOM cores is all done with the configuration system and two specific config fragments. +Both BOOM and Rocket have config fragments labelled ``WithNBoomCores(X)`` and ``WithNBigCores(X)`` that automatically create ``X`` copies of the core/tile [1]_. When used together you can create a heterogeneous system. The following example shows a dual core BOOM with a single core Rocket. @@ -18,18 +18,18 @@ The following example shows a dual core BOOM with a single core Rocket. :start-after: DOC include start: DualBoomAndRocket :end-before: DOC include end: DualBoomAndRocket -In this example, the ``WithNBoomCores`` and ``WithNBigCores`` mixins set up the default parameters for the multiple BOOM and Rocket cores, respectively. -However, for BOOM, an extra mixin called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters. -This mixin applies to all BOOM cores in the system and changes the parameters for each. +In this example, the ``WithNBoomCores`` and ``WithNBigCores`` config fragments set up the default parameters for the multiple BOOM and Rocket cores, respectively. +However, for BOOM, an extra config fragment called ``WithLargeBooms`` is added to override the default parameters with a different set of more common default parameters. +This config fragment applies to all BOOM cores in the system and changes the parameters for each. Great! Now you have a heterogeneous setup with BOOMs and Rockets. The final thing you need to make this system work is to renumber the ``hartId``'s of the cores so that each core has a unique ``hartId`` (a ``hartId`` is the hardware thread id of the core). -The ``WithRenumberHarts`` mixin solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first). -The reason this is needed is because by default the ``WithN...Cores(X)`` mixin assumes that there are only BOOM or only Rocket cores in the system. -Thus, without the ``WithRenumberHarts`` mixin, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. +The ``WithRenumberHarts`` config fragment solves this by assigning a unique ``hartId`` to all cores in the system (it can label the Rocket cores first or the BOOM cores first). +The reason this is needed is because by default the ``WithN...Cores(X)`` config fragment assumes that there are only BOOM or only Rocket cores in the system. +Thus, without the ``WithRenumberHarts`` config fragment, each set of cores is labeled starting from zero causing multiple cores to be assigned the same ``hartId``. Another alternative option to create a multi heterogeneous core system is to override the parameters yourself so you can specify the core parameters per core. -The mixin to add to your system would look something like the following. +The config fragment to add to your system would look something like the following. .. code-block:: scala @@ -50,7 +50,7 @@ The mixin to add to your system would look something like the following. } }) -Then you could use this new mixin like the following. +Then you could use this new config fragment like the following. .. code-block:: scala @@ -83,7 +83,7 @@ All with the same Hwacha parameters. Assigning Accelerators to Specific Tiles with MultiRoCC ------------------------------------------------------- -Located in ``generators/chipyard/src/main/scala/ConfigMixins.scala`` is a mixin that provides support for adding RoCC accelerators to specific tiles in your SoC. +Located in ``generators/chipyard/src/main/scala/ConfigFragments.scala`` is a config fragment that provides support for adding RoCC accelerators to specific tiles in your SoC. Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on the ``hartId`` of the tile. For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. @@ -94,13 +94,13 @@ An example is shown below with two BOOM cores, and one Rocket tile with a RoCC a :end-before: DOC include end: DualBoomAndRocketOneHwacha In this example, the ``WithRenumberHarts`` relabels the ``hartId``'s of all the BOOM/Rocket cores. -Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` mixin assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core). -Finally, the ``WithMultiRoCC`` mixin is called. -This mixin sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. +Then after that is applied to the parameters, the ``WithMultiRoCCHwacha`` config fragment assigns a Hwacha accelerator to a particular ``hartId`` (in this case, the ``hartId`` of ``2`` corresponds to the Rocket core). +Finally, the ``WithMultiRoCC`` config fragment is called. +This config fragment sets the ``BuildRoCC`` key to use the ``MultiRoCCKey`` instead of the default. This must be used after all the RoCC parameters are set because it needs to override the ``BuildRoCC`` parameter. If this is used earlier in the configuration sequence, then MultiRoCC does not work. -This mixin can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``). +This config fragment can be changed to put more accelerators on more cores by changing the arguments to cover more ``hartId``'s (i.e. ``WithMultiRoCCHwacha(0,1,3,6,...)``). .. [1] Note, in this section "core" and "tile" are used interchangeably but there is subtle distinction between a "core" and "tile" ("tile" contains a "core", L1D/I$, PTW). diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 798987b1..59924a0f 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -22,4 +22,4 @@ For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` wh These classes are all ``Config`` objects, which can be mixed into the configs to specify IO connection behaviors. -There are two macros for generating these ``Configs``. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. +There are two macros for generating these ``Config``s. ``OverrideIOBinder`` overrides any existing behaviors set for a particular IO in the ``Config`` object. This macro is frequently used because typically top-level IOs drive or are driven by only one source, so a composition of ``IOBinders`` does not make sense. The ``ComposeIOBinder`` macro provides the functionality of not overriding existing behaviors. diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index bac311c5..0dd20a65 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -3,7 +3,7 @@ Keys, Traits, and Configs ========================= -You have probably seen snippets of Chisel referencing Keys, Traits, and Configs by this point. +You have probably seen snippets of Chisel referencing keys, traits, and configs by this point. This section aims to elucidate the interactions between these Chisel/Scala components, and provide best practices for how these should be used to create a parameterized design and configure it. @@ -36,9 +36,9 @@ Traits Typically, most custom blocks will need to modify the behavior of some pre-existing block. For example, the GCD widget needs the ``Top`` module to instantiate and connect the widget via Tilelink, generate a top-level ``gcd_busy`` port, and connect that to the module as well. Traits let us do this without modifying the existing code for the ``Top``, and enables compartmentalization of code for different custom blocks. -Top-level traits specify that the ``Top`` has been parameterized to read some custom Key and optionally instantiate and connect a widget defined by that Key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the Key is unset is a no-op. +Top-level traits specify that the ``Top`` has been parameterized to read some custom key and optionally instantiate and connect a widget defined by that key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the key is unset is a no-op. -Top-level traits should be defined and documented in subprojects, alongside their corresponding Keys. The traits should then be added to the ``Top`` being used by Chipyard. +Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``Top`` being used by Chipyard. Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. @@ -54,19 +54,19 @@ These traits are added to the default ``Top`` in Chipyard. :start-after: DOC include start: Top :end-before: DOC include end: Top -Mixins ------- +Config Fragments +---------------- -Config mixins set the keys to a non-default value. Together, the collection of Mixins which define a configuration generate the values for all the keys used by the generator. +Config fragments set the keys to a non-default value. Together, the collection of config fragments which define a configuration generate the values for all the keys used by the generator. -For example, the ``WithGCDMixin`` is parameterized by the type of GCD widget you want to instantiate. When this mixin is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. +For example, the ``WithGCD`` config fragment is parameterized by the type of GCD widget you want to instantiate. When this config fragment is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. .. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala - :start-after: DOC include start: GCD mixin - :end-before: DOC include end: GCD mixin + :start-after: DOC include start: GCD config fragment + :end-before: DOC include end: GCD config fragment -We can use this mixin when composing our configs. +We can use this config fragment when composing our configs. .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index c1c1a424..4801d4d4 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -105,12 +105,12 @@ The ``TopModule`` class is the actual RTL that gets synthesized. -And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` mixin defined earlier. +And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` config fragment defined earlier. .. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala :language: scala - :start-after: DOC include start: GCD mixin - :end-before: DOC include end: GCD mixin + :start-after: DOC include start: GCD fragment + :end-before: DOC include end: GCD fragment .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 99cc9f77..436a0ea9 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -12,8 +12,8 @@ uses 16 KiB, 4-way set-associative instruction and data caches. However, if you use the ``WithNMedCores`` or ``WithNSmallCores`` configurations, you can configure 4 KiB direct-mapped caches for L1I and L1D. -If you only want to change the size or associativity, there are configuration -mixins for those too. See :ref:`Mixins` for how to add these to a custom ``Config`` +If you only want to change the size or associativity, there are config +fragments for those too. See :ref:`Config Fragments` for how to add these to a custom ``Config``. .. code-block:: scala @@ -41,7 +41,7 @@ number of channels and number of banks to 0. The SiFive L2 Cache ------------------- -The default RocketConfig provided in the Chipyard example project uses SiFive's +The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's InclusiveCache generator to produce a shared L2 cache. In the default configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way set-associativity. However, you can change these parameters to obtain your @@ -58,11 +58,11 @@ If you do not want to use the L2 cache (say, for a resource-limited embedded design), you can create a configuration without it. Instead of using the L2 cache, you will instead use RocketChip's TileLink broadcast hub. To make such a configuration, you can just copy the definition of -``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the +``RocketConfig`` but omit the ``WithInclusiveCache`` config fragment from the list of included mixims. If you want to reduce the resources used even further, you can configure -the Broadcast Hub to use a bufferless design. This mixin is +the Broadcast Hub to use a bufferless design. This config fragment is ``freechips.rocketchip.subsystem.WithBufferlessBroadcastHub``. diff --git a/docs/Customization/index.rst b/docs/Customization/index.rst index 496f4c0a..90d36fda 100644 --- a/docs/Customization/index.rst +++ b/docs/Customization/index.rst @@ -11,7 +11,7 @@ These guides will walk you through customization of your system-on-chip: - Adding custom MMIO widgets to the Chipyard memory system by Tilelink or AXI4, with custom Top-level IOs -- Standard practices for using Keys, Traits, and Configs to parameterize your design +- Standard practices for using keys, traits, and configs to parameterize your design - Customizing the memory hierarchy diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index fe126f02..80767ce0 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -3,9 +3,9 @@ Gemmini The Gemmini project is developing a systolic-array based matrix multiplication unit generator for the investigation of software/hardware implications of such integrated SoC accelerators. It is inspired by recent trends in machine learning accelerators for edge and mobile SoCs. -Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the System Bus (i.e., directly to the L2 cache). +Gemmini is implemented as a RoCC accelerator with non-standard RISC-V custom instructions. The Gemmini unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the System Bus (i.e., directly to the L2 cache). -To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config mixin to the SoC configurations. To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``, which you can view under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. +To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConfig`` config fragment to the SoC configurations. To change the configuration of the Gemmini accelerator unit, you can write a custom configuration to replace the ``DefaultGemminiConfig``, which you can view under `generators/gemmini/src/main/scala/configs.scala `__ to see the possible configuration parameters. The example Chipyard config includes the following example SoC configuration which includes Gemmini: @@ -46,12 +46,12 @@ Gemmini Software ------------------ The Gemmini non-standard ISA extension is specified in the `Gemmini repository `__. -The ISA includes configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. +The ISA includes configuration instructions, data movement instructions (from main memory to the Gemmini scratchpad, and from the Gemmini accumulators to main memory), and matrix multiplication execution instructions. Since Gemmini instructions are not exposed through the GNU binutils assembler, several C macros are provided in order to construct the instruction encodings to call these instructions. The Gemmini generator includes a C matrix multiplication library which wraps the calls to the custom Gemmini instructions. -The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. +The ``software`` directory of the generator includes the aforementioned library and macros, as well as bare-metal tests, and some FireMarshal workloads to run the tests in a Linux environment. In particular, the matrix multiplication C library can be found in the ``software/gemmini-rocc-tests/include/gemmini.h`` file. The Gemmini generator generates a C header file based on the generator parameters. This header files gets compiled together with the matrix multiplication library to tune library performance. The generated header file can be found under ``software/gemmini-rocc-tests/include/gemmini_params.h`` @@ -64,7 +64,7 @@ To build Gemmini tests: cd generators/gemmini/software/gemmini-rocc-tests/ ./build.sh - + Afterwards, the test binaries will be found in ``generators/gemmini/software/gemmini-rocc-tests/build``. Binaries whose names end in ``-baremetal`` are meant to be run in a bare-metal environment, while binaries whose names end in ``-linux`` are meant to run in a Linux environment. You can run the tests either on a cycle-accurate RTL simulator, or on a (much faster) functional ISA simulator called Spike. The Gemmini generator implements a custom non-standard version of Spike. This implementation is found within the ``esp-tools`` Spike implementation, together with the Hwacha vector accelerator non-standard ISA-extension. In order to use this version of Spike, please make sure to build the ``esp-tools`` software toolchain, as described in :ref:`build-toolchains`. @@ -80,7 +80,7 @@ Spike is built by default without a commit log. However, if you would like to ad Alternative SoC Configs -------------------------- -The Gemmini generator includes additional alternative SoC configs (configs that are not in the Chipyard example project). +The Gemmini generator includes additional alternative SoC configs (configs that are not in the Chipyard example project). If you would like to build one of these alternative SoC configurations which are defined in within the Gemmini project repository, you can run the following commands. These commands are similar to the one required when building a simulation from the example project, but they specify that the location of the configs are in the Gemmini subproject, as opposed to the Chipyard example project: .. code-block:: shell diff --git a/docs/Generators/Hwacha.rst b/docs/Generators/Hwacha.rst index ac4f4fdf..1980cddf 100644 --- a/docs/Generators/Hwacha.rst +++ b/docs/Generators/Hwacha.rst @@ -7,9 +7,9 @@ The Hwacha project includes the Hwacha microarchitecture generator, as well as t For more information on the Hwacha project, please visit the `Hwacha website `__. -To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config mixin to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). +To add the Hwacha vector unit to an SoC, you should add the ``hwacha.DefaultHwachaConfig`` config fragment to the SoC configurations. The Hwacha vector unit uses the RoCC port of a Rocket or BOOM `tile`, and by default connects to the memory system through the `System Bus` (i.e., directly to the L2 cache). To change the configuration of the Hwacha vector unit, you can write a custom configuration to replace the ``DefaultHwachaConfig``. You can view the ``DefaultHwachaConfig`` under `generators/hwacha/src/main/scala/configs.scala `__ to see the possible configuration parameters. - + Since Hwacha implements a non-standard RISC-V extension, it requires a unique software toolchain to be able to compile and assemble its vector instructions. To install the Hwacha toolchain, run the ``./scripts/build-toolchains.sh esp-tools`` command within the root Chipyard directory. This may take a while, and it will install the ``esp-tools-install`` directory within your Chipyard root directory. ``esp-tools`` is a fork of ``riscv-tools`` (formerly a collection of relevant software RISC-V tools) that was enhanced with additional non-standard vector instructions. However, due to the upstreaming of the equivalent RISC-V toolchains, ``esp-tools`` may not be up-to-date with the latest mainline version of the tools included in it. diff --git a/docs/Generators/IceNet.rst b/docs/Generators/IceNet.rst index b520eb6c..a8595038 100644 --- a/docs/Generators/IceNet.rst +++ b/docs/Generators/IceNet.rst @@ -8,7 +8,7 @@ A diagram of IceNet's microarchitecture is shown below. .. image:: ../_static/images/nic-design.png -There are four basic parts of the NIC: the :ref:`Controller`, which takes requests +There are four basic parts of the NIC: the :ref:`Controller`, which takes requests from and sends responses to the CPU; the :ref:`Send Path`, which reads data from memory and sends it out to the network; the :ref:`Receive Path`, which receives data from the network and writes it to memory; and, optionally, @@ -80,8 +80,8 @@ and ``HasPeripheryIceNICModuleImp`` to the module implementation. If you are confused about the distinction between lazy module and module implementation, refer to :ref:`Cake Pattern`. -Then add the ``WithIceNIC`` config mixin to your configuration. This will -define ``NICKey``, which IceNIC uses to determine its parameters. The mixin +Then add the ``WithIceNIC`` config fragment to your configuration. This will +define ``NICKey``, which IceNIC uses to determine its parameters. The config fragment takes two arguments. The ``inBufFlits`` argument is the number of 64-bit flits that the input packet buffer can hold and the ``usePauser`` argument determines whether or not the NIC will have a pause handler. diff --git a/docs/Generators/SHA3.rst b/docs/Generators/SHA3.rst index c8969c3a..92173995 100644 --- a/docs/Generators/SHA3.rst +++ b/docs/Generators/SHA3.rst @@ -68,9 +68,9 @@ Using a SHA3 Accelerator ------------------------ Since the SHA3 accelerator is designed as a RoCC accelerator, it can be mixed into a Rocket or BOOM core by overriding the -``BuildRoCC`` key. The configuration mixin is defined in the SHA3 +``BuildRoCC`` key. The config fragment is defined in the SHA3 generator. An example configuration highlighting the use of -this mixin is shown here: +this config fragment is shown here: .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index 35b160f8..68c239c7 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -1,13 +1,13 @@ SiFive Generators ================== -Chipyard includes several open-source generators developed and maintained by `SiFive `__. +Chipyard includes several open-source generators developed and maintained by `SiFive `__. These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``. Last-Level Cache Generator ----------------------------- -``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` mixin to your SoC configuration. +``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration. To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section. @@ -16,24 +16,24 @@ Peripheral Devices ``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more. These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well. -To integrate one of these devices in your SoC, you will need to define a custom mixin with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following mixin to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. +To integrate one of these devices in your SoC, you will need to define a custom config fragment with the approriate address for the device using the Rocket Chip parameter system. As an example, for a GPIO device you could add the following config fragment to set the GPIO address to ``0x10012000``. This address is the start address for the GPIO configuration registers. -.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigMixins.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigFragments.scala :language: scala :start-after: DOC include start: gpio mixin :end-before: DOC include end: gpio mixin -Additionally, if the device requires top-level IOs, you will need to define a mixin to change the top-level configuration of your SoC. +Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC. When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. This example instantiates a top-level module with include GPIO ports, and then ties-off the GPIO port inputs to 0 (``false.B``). -Finally, you add the relevant config mixin to the SoC config. For example: +Finally, you add the relevant config fragment to the SoC config. For example: .. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala :language: scala :start-after: DOC include start: GPIORocketConfig :end-before: DOC include end: GPIORocketConfig -Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined mixins within the Chipyard example project. You may be able to use these config mixins directly, but you should be aware of their addresses within the SoC address map. +Some of the devices in ``sifive-blocks`` (such as GPIO) may already have pre-defined config fragments within the Chipyard example project. You may be able to use these config fragments directly, but you should be aware of their addresses within the SoC address map. diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 0e02c077..f85636b1 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -22,7 +22,7 @@ The block device controller provides a generic interface for secondary storage. This device is primarily used in FireSim to interface with a block device software simulation model. The default Linux configuration in `firesim-software `_ -To add a block device to your design, add the ``WithBlockDevice`` config mixin to your configuration. +To add a block device to your design, add the ``WithBlockDevice`` config fragment to your configuration. TileLink SERDES diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index ea4f3297..82692643 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -55,7 +55,7 @@ Converting a Chipyard config (one in ``chipyard/src/main/scala`` to run in FireS :end-before: DOC include end: firesimconfig -Only 3 additional config-mixins are needed. +Only 3 additional config fragments are needed. * ``WithFireSimConfigTweaks`` modifies your design to better fit the FireSim usage model. For example, FireSim designs typically include a UART. Technically, adding this in is optional, but *strongly* recommended. * ``WithDefaultMemModel`` sets the external memory model in the FireSim simulation. See the FireSim documentation for details. diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 9bc236ac..957913e9 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -93,7 +93,7 @@ The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. No The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class. -The ``CONFIG`` is the name of the class used for the parameter Config while the ``CONFIG_PACKAGE`` is the Scala package it resides in. +The ``CONFIG`` is the name of the class used for the parameter config while the ``CONFIG_PACKAGE`` is the Scala package it resides in. The ``GENERATOR_PACKAGE`` is the Scala package that holds the Generator class that elaborates the design. diff --git a/generators/boom b/generators/boom index 779c62c5..28003f77 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 779c62c5634847b517be64c554af66829de40067 +Subproject commit 28003f7799fa9ea6cc89b56494dc77a3b427f6c9 diff --git a/generators/chipyard/src/main/scala/ConfigMixins.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala similarity index 92% rename from generators/chipyard/src/main/scala/ConfigMixins.scala rename to generators/chipyard/src/main/scala/ConfigFragments.scala index 8234f0e3..d13f468a 100644 --- a/generators/chipyard/src/main/scala/ConfigMixins.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -32,7 +32,7 @@ object ConfigValName { import ConfigValName._ // ----------------------- -// Common Parameter Mixins +// Common Config Fragments // ----------------------- class WithBootROM extends Config((site, here, up) => { @@ -40,12 +40,12 @@ class WithBootROM extends Config((site, here, up) => { contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img") }) -// DOC include start: gpio mixin +// DOC include start: gpio config fragment class WithGPIO extends Config((site, here, up) => { case PeripheryGPIOKey => Seq( GPIOParams(address = 0x10012000, width = 4, includeIOF = false)) }) -// DOC include end: gpio mixin +// DOC include end: gpio config fragment class WithUART extends Config((site, here, up) => { case PeripheryUARTKey => Seq( @@ -80,14 +80,14 @@ class WithTracegenTop extends Config((site, here, up) => { case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]]) /** - * Mixin to enable different RoCCs based on the hartId + * Config fragment to enable different RoCCs based on the hartId */ class WithMultiRoCC extends Config((site, here, up) => { case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil) }) /** - * Mixin to add Hwachas to cores based on hart + * Config fragment to add Hwachas to cores based on hart * * For ex: * Core 0, 1, 2, 3 have been defined earlier @@ -110,7 +110,7 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { /** - * Mixin to add a small Rocket core to the system as a "control" core. + * Config fragment to add a small Rocket core to the system as a "control" core. * Used as an example of a PMU core. */ class WithControlCore extends Config((site, here, up) => { diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/GCD.scala index 802520f0..049fa876 100644 --- a/generators/chipyard/src/main/scala/GCD.scala +++ b/generators/chipyard/src/main/scala/GCD.scala @@ -200,8 +200,8 @@ trait CanHavePeripheryGCDModuleImp extends LazyModuleImp { // DOC include end: GCD imp trait -// DOC include start: GCD mixin +// DOC include start: GCD config fragment class WithGCD(useAXI4: Boolean, useBlackBox: Boolean) extends Config((site, here, up) => { case GCDKey => Some(GCDParams(useAXI4 = useAXI4, useBlackBox = useBlackBox)) }) -// DOC include end: GCD mixin +// DOC include end: GCD config fragment From 24fe57d447466098cc32cbd38d8405f4e1065ece Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 11 Feb 2020 22:42:33 -0800 Subject: [PATCH 030/139] use blackboxed SimDRAM instead of SimAXIMem --- .gitmodules | 3 ++ build.sbt | 2 +- common.mk | 8 ++++- .../chipyard/src/main/scala/BoomConfigs.scala | 16 ++++----- .../src/main/scala/HeteroConfigs.scala | 14 ++++---- .../chipyard/src/main/scala/IOBinders.scala | 15 ++++++++ .../src/main/scala/RocketConfigs.scala | 34 +++++++++---------- .../src/main/scala/TracegenConfigs.scala | 8 ++--- generators/testchipip | 2 +- .../src/main/resources/csrc/emulator.cc | 11 ++++-- .../utilities/src/main/scala/Simulator.scala | 5 +++ sims/vcs/.gitignore | 1 + sims/vcs/Makefile | 6 ++-- sims/vcs/dramsim2_ini | 1 + sims/verilator/.gitignore | 1 + sims/verilator/Makefile | 8 ++--- sims/verilator/dramsim2_ini | 1 + tools/DRAMSim2 | 1 + 18 files changed, 90 insertions(+), 47 deletions(-) create mode 120000 sims/vcs/dramsim2_ini create mode 120000 sims/verilator/dramsim2_ini create mode 160000 tools/DRAMSim2 diff --git a/.gitmodules b/.gitmodules index c4a9b2b9..88096baf 100644 --- a/.gitmodules +++ b/.gitmodules @@ -113,3 +113,6 @@ [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git +[submodule "tools/DRAMSim2"] + path = tools/DRAMSim2 + url = https://github.com/firesim/DRAMSim2.git diff --git a/build.sbt b/build.sbt index 678fffb5..0a4e2167 100644 --- a/build.sbt +++ b/build.sbt @@ -127,7 +127,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) - .dependsOn(rocketchip, sifive_cache, boom) + .dependsOn(rocketchip, sifive_cache, boom, utilities) .settings(commonSettings) lazy val utilities = conditionalDependsOn(project in file("generators/utilities")) diff --git a/common.mk b/common.mk index 1fd7a193..08e872f2 100644 --- a/common.mk +++ b/common.mk @@ -129,7 +129,7 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) +dramsim +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator @@ -156,4 +156,10 @@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) tracegen: $(output_dir)/tracegen.result +dramsim_dir = $(base_dir)/tools/DRAMSim2 +dramsim_lib = $(dramsim_dir)/libdramsim.a + +$(dramsim_lib): + $(MAKE) -C $(dramsim_dir) $(notdir $@) + .PHONY: tracegen diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/BoomConfigs.scala index cd1e691b..bda5cccd 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/BoomConfigs.scala @@ -12,7 +12,7 @@ import freechips.rocketchip.config.{Config} class SmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -32,7 +32,7 @@ class SmallBoomConfig extends Config( class MediumBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -51,7 +51,7 @@ class MediumBoomConfig extends Config( class LargeBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -70,7 +70,7 @@ class LargeBoomConfig extends Config( class MegaBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -89,7 +89,7 @@ class MegaBoomConfig extends Config( class DualSmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -108,7 +108,7 @@ class DualSmallBoomConfig extends Config( class SmallRV32BoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -129,7 +129,7 @@ class SmallRV32BoomConfig extends Config( class HwachaLargeBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -149,7 +149,7 @@ class HwachaLargeBoomConfig extends Config( class LoopbackNICLargeBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/HeteroConfigs.scala index b5cc6b8c..c275433f 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/HeteroConfigs.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.config.{Config} class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -33,7 +33,7 @@ class LargeBoomAndRocketConfig extends Config( class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -56,7 +56,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( class DualLargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -79,7 +79,7 @@ class DualLargeBoomAndRocketConfig extends Config( class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -105,7 +105,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( class LargeBoomAndRV32RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -129,7 +129,7 @@ class LargeBoomAndRV32RocketConfig extends Config( class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -151,7 +151,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 22715aaf..938ecc5f 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -103,6 +103,21 @@ class WithSimAXIMem extends OverrideIOBinder({ }) // DOC include end: WithSimAXIMem +class WithBlackBoxSimMem extends OverrideIOBinder({ + (clock, reset, _, top: CanHaveMasterAXI4MemPortModuleImp) => { + (top.mem_axi4 zip top.outer.memAXI4Node).foreach { case (io, node) => + val memSize = top.p(ExtMem).get.master.size + val lineSize = top.p(CacheBlockBytes) + (io zip node.in).foreach { case (axi4, (_, edge)) => + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) + mem.io.axi <> axi4 + mem.io.clock := clock + mem.io.reset := reset + } + }; Nil + } +}) + class WithSimAXIMMIO extends OverrideIOBinder({ (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil }) diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/RocketConfigs.scala index 2e0f856a..c596dc29 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/RocketConfigs.scala @@ -11,7 +11,7 @@ import freechips.rocketchip.config.{Config} class RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -29,7 +29,7 @@ class RocketConfig extends Config( class HwachaRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -49,7 +49,7 @@ class HwachaRocketConfig extends Config( class GemminiRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -69,7 +69,7 @@ class GemminiRocketConfig extends Config( class RoccRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -89,7 +89,7 @@ class RoccRocketConfig extends Config( class jtagRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -110,7 +110,7 @@ class jtagRocketConfig extends Config( class dmiRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation new chipyard.config.WithNoGPIO ++ @@ -129,7 +129,7 @@ class dmiRocketConfig extends Config( class GCDTLRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -150,7 +150,7 @@ class GCDTLRocketConfig extends Config( class GCDAXI4BlackBoxRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -170,7 +170,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config( class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice @@ -190,7 +190,7 @@ class SimBlockDeviceRocketConfig extends Config( class BlockDeviceModelRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel @@ -211,7 +211,7 @@ class BlockDeviceModelRocketConfig extends Config( class GPIORocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithGPIOTiedOff ++ // tie off GPIO inputs into the top @@ -231,7 +231,7 @@ class GPIORocketConfig extends Config( class QuadRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -249,7 +249,7 @@ class QuadRocketConfig extends Config( class RV32RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -267,7 +267,7 @@ class RV32RocketConfig extends Config( class GB1MemoryRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -287,7 +287,7 @@ class GB1MemoryRocketConfig extends Config( class Sha3RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -308,7 +308,7 @@ class Sha3RocketConfig extends Config( class InitZeroRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ @@ -328,7 +328,7 @@ class InitZeroRocketConfig extends Config( class LoopbackNICRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/TracegenConfigs.scala index 1e9be623..fccac401 100644 --- a/generators/chipyard/src/main/scala/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/TracegenConfigs.scala @@ -6,21 +6,21 @@ import freechips.rocketchip.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} class TraceGenConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ @@ -28,7 +28,7 @@ class BoomTraceGenConfig extends Config( new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( - new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenTop ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ diff --git a/generators/testchipip b/generators/testchipip index a3da53e8..f1b41df8 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit a3da53e87ad890be37138e27e477eb9a563fa82e +Subproject commit f1b41df80d12b35f8f514c3fb72775203a7edd2d diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 1a4f4dd2..0e86b836 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -35,6 +35,7 @@ extern tsi_t* tsi; extern dtm_t* dtm; extern remote_bitbang_t * jtag; +extern int dramsim; static uint64_t trace_count = 0; bool verbose; @@ -124,6 +125,8 @@ int main(int argc, char** argv) char ** htif_argv = NULL; int verilog_plusargs_legal = 1; + dramsim = 0; + while (1) { static struct option long_options[] = { {"cycle-count", no_argument, 0, 'c' }, @@ -132,6 +135,7 @@ int main(int argc, char** argv) {"seed", required_argument, 0, 's' }, {"rbb-port", required_argument, 0, 'r' }, {"verbose", no_argument, 0, 'V' }, + {"dramsim", no_argument, 0, 'D' }, #if VM_TRACE {"vcd", required_argument, 0, 'v' }, {"dump-start", required_argument, 0, 'x' }, @@ -140,9 +144,9 @@ int main(int argc, char** argv) }; int option_index = 0; #if VM_TRACE - int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:v:Vx:D", long_options, &option_index); #else - int c = getopt_long(argc, argv, "-chm:s:r:V", long_options, &option_index); + int c = getopt_long(argc, argv, "-chm:s:r:VD", long_options, &option_index); #endif if (c == -1) break; retry: @@ -155,6 +159,7 @@ int main(int argc, char** argv) case 's': random_seed = atoi(optarg); break; case 'r': rbb_port = atoi(optarg); break; case 'V': verbose = true; break; + case 'D': dramsim = 1; break; #if VM_TRACE case 'v': { vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w"); @@ -188,6 +193,8 @@ int main(int argc, char** argv) #endif else if (arg.substr(0, 12) == "+cycle-count") c = 'c'; + else if (arg == "+dramsim") + c = 'D'; // If we don't find a legacy '+' EMULATOR argument, it still could be // a VERILOG_PLUSARG and not an error. else if (verilog_plusargs_legal) { diff --git a/generators/utilities/src/main/scala/Simulator.scala b/generators/utilities/src/main/scala/Simulator.scala index b1b2c4c4..b2982db7 100644 --- a/generators/utilities/src/main/scala/Simulator.scala +++ b/generators/utilities/src/main/scala/Simulator.scala @@ -83,6 +83,11 @@ object GenerateSimFiles extends App with HasGenerateSimConfig { } def resources(sim: Simulator): Seq[String] = Seq( "/testchipip/csrc/SimSerial.cc", + "/testchipip/csrc/SimDRAM.cc", + "/testchipip/csrc/mm.h", + "/testchipip/csrc/mm.cc", + "/testchipip/csrc/mm_dramsim2.h", + "/testchipip/csrc/mm_dramsim2.cc", "/csrc/SimDTM.cc", "/csrc/SimJTAG.cc", "/csrc/remote_bitbang.h", diff --git a/sims/vcs/.gitignore b/sims/vcs/.gitignore index a0991ff4..c3e65b20 100644 --- a/sims/vcs/.gitignore +++ b/sims/vcs/.gitignore @@ -1,3 +1,4 @@ * !.gitignore !Makefile +!dramsim2_ini diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 86c28f23..e5c6e1be 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -47,7 +47,9 @@ VCS = vcs -full64 VCS_CC_OPTS = \ -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ + -CC "-I$(dramsim_dir)" \ -CC "-std=c++11" \ + $(dramsim_lib) \ $(RISCV)/lib/libfesvr.a VCS_NONCC_OPTS = \ @@ -78,11 +80,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_common_files) +$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_common_files) +$(sim_debug) : $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG -debug_pp diff --git a/sims/vcs/dramsim2_ini b/sims/vcs/dramsim2_ini new file mode 120000 index 00000000..19d93477 --- /dev/null +++ b/sims/vcs/dramsim2_ini @@ -0,0 +1 @@ +../../generators/testchipip/src/main/resources/dramsim2_ini \ No newline at end of file diff --git a/sims/verilator/.gitignore b/sims/verilator/.gitignore index afbfb95f..136aa28f 100644 --- a/sims/verilator/.gitignore +++ b/sims/verilator/.gitignore @@ -2,3 +2,4 @@ !.gitignore !Makefile !verilator.mk +!dramsim2_ini diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index caaba672..140f54fd 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -45,8 +45,8 @@ include $(sim_dir)/verilator.mk ######################################################################################### VERILATOR := $(INSTALLED_VERILATOR) --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread +CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS +LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim VERILATOR_CC_OPTS = \ -O3 \ @@ -97,10 +97,10 @@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) ######################################################################################### # invoke make to make verilator sim rules ######################################################################################### -$(sim): $(model_mk) +$(sim): $(model_mk) $(dramsim_lib) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk -$(sim_debug): $(model_mk_debug) +$(sim_debug): $(model_mk_debug) $(dramsim_lib) $(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk ######################################################################################### diff --git a/sims/verilator/dramsim2_ini b/sims/verilator/dramsim2_ini new file mode 120000 index 00000000..19d93477 --- /dev/null +++ b/sims/verilator/dramsim2_ini @@ -0,0 +1 @@ +../../generators/testchipip/src/main/resources/dramsim2_ini \ No newline at end of file diff --git a/tools/DRAMSim2 b/tools/DRAMSim2 new file mode 160000 index 00000000..2ec7965b --- /dev/null +++ b/tools/DRAMSim2 @@ -0,0 +1 @@ +Subproject commit 2ec7965b2ee051aaff03d5db21c6709aea4dd24e From 4dd97e0b0fe8ca89008b966dc1a27b34f15c35c1 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 2 Mar 2020 21:08:30 -0800 Subject: [PATCH 031/139] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1c7caed6..23b80238 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1c7caed637a64a231905af9aea2148be60add16b +Subproject commit 23b80238aae22625b0a0ef1c173008655c8c3842 From 48a7f22c09ba0df9f92603a17232483b59f34a11 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 3 Mar 2020 09:27:51 -0800 Subject: [PATCH 032/139] move DRAMSim2 makefrag rules --- common.mk | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/common.mk b/common.mk index 08e872f2..839e7b54 100644 --- a/common.mk +++ b/common.mk @@ -156,10 +156,14 @@ $(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) tracegen: $(output_dir)/tracegen.result +.PHONY: tracegen + +####################################### +# Rules for building DRAMSim2 library # +####################################### + dramsim_dir = $(base_dir)/tools/DRAMSim2 dramsim_lib = $(dramsim_dir)/libdramsim.a $(dramsim_lib): $(MAKE) -C $(dramsim_dir) $(notdir $@) - -.PHONY: tracegen From 9f7247b927db222ef06131b027c61c7a23d1c1ef Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 5 Mar 2020 09:17:47 -0800 Subject: [PATCH 033/139] bump firesim for makefile fix --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 23b80238..2f033c21 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 23b80238aae22625b0a0ef1c173008655c8c3842 +Subproject commit 2f033c2101612097fa27cf1768a280c980125b39 From 1e26cb1f499e3e91fa0110b2b69e8f06217c80cf Mon Sep 17 00:00:00 2001 From: John Wright Date: Thu, 5 Mar 2020 13:04:54 -0800 Subject: [PATCH 034/139] Add a git version check to the init scripts and make them work outside of the repo root. (#459) * Fixes #453 - Update scripts/init-submodules-no-riscv-tools.sh to also work if you're in scripts/ - Provide a git version check to ensure the init scripts will work (>= 1.7.8) - Update the documentation to be more explicit that the init script is also for updating. * Update scripts/init-submodules-no-riscv-tools-nolog.sh Co-Authored-By: Albert Ou --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 3 +++ scripts/init-submodules-no-riscv-tools-nolog.sh | 14 +++++++++++++- scripts/init-submodules-no-riscv-tools.sh | 3 +++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 931da013..c4732e8a 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -34,6 +34,9 @@ After cloning this repo, you will need to initialize all of the submodules. cd chipyard ./scripts/init-submodules-no-riscv-tools.sh +When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. +Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. + .. _build-toolchains: Building a Toolchain diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index ed4f5b6a..888feb0e 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -4,6 +4,19 @@ set -e set -o pipefail +# Check that git version is at least 1.7.8 +MYGIT=$(git --version) +MYGIT=${MYGIT#'git version '} # Strip prefix +case ${MYGIT} in +[1-9]*) ;; +*) echo 'warning: unknown git version' ;; +esac +MINGIT="1.7.8" +if [ "$MINGIT" != "$(echo -e "$MINGIT\n$MYGIT" | sort -V | head -n1)" ]; then + echo "This script requires git version $MINGIT or greater. Exiting." + false +fi + RDIR=$(git rev-parse --show-toplevel) # Ignore toolchain submodules @@ -61,4 +74,3 @@ if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml fi echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh - diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 550d8846..d788f804 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -5,4 +5,7 @@ set -e set -o pipefail +RDIR=$(git rev-parse --show-toplevel) +cd "$RDIR" + ./scripts/init-submodules-no-riscv-tools-nolog.sh "$@" 2>&1 | tee init-submodules-no-riscv-tools.log From 854e71a205d1b16aed615f6943771fee0d71dfdc Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 5 Mar 2020 19:35:47 -0800 Subject: [PATCH 035/139] Add tutorial config and tutorial patches --- .circleci/config.yml | 31 ++++ .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 6 + build.sbt | 8 +- generators/boom | 2 +- .../src/main/scala/ConfigFragments.scala | 12 ++ .../main/scala/{ => config}/BoomConfigs.scala | 4 +- .../scala/{ => config}/HeteroConfigs.scala | 18 +-- .../scala/{ => config}/RocketConfigs.scala | 4 +- .../scala/{ => config}/TracegenConfigs.scala | 2 - .../main/scala/config/TutorialConfigs.scala | 138 ++++++++++++++++++ .../src/main/scala/{ => example}/GCD.scala | 0 .../main/scala/{ => example}/InitZero.scala | 0 .../main/scala/{ => example}/NodeTypes.scala | 0 .../{ => example}/RegisterNodeExample.scala | 0 generators/sha3 | 2 +- .../RocketConfigs.scala.patch | 13 ++ scripts/tutorial-patches/build.sbt.patch | 35 +++++ scripts/tutorial-setup.sh | 11 ++ 19 files changed, 265 insertions(+), 22 deletions(-) rename generators/chipyard/src/main/scala/{ => config}/BoomConfigs.scala (99%) rename generators/chipyard/src/main/scala/{ => config}/HeteroConfigs.scala (95%) rename generators/chipyard/src/main/scala/{ => config}/RocketConfigs.scala (99%) rename generators/chipyard/src/main/scala/{ => config}/TracegenConfigs.scala (98%) create mode 100644 generators/chipyard/src/main/scala/config/TutorialConfigs.scala rename generators/chipyard/src/main/scala/{ => example}/GCD.scala (100%) rename generators/chipyard/src/main/scala/{ => example}/InitZero.scala (100%) rename generators/chipyard/src/main/scala/{ => example}/NodeTypes.scala (100%) rename generators/chipyard/src/main/scala/{ => example}/RegisterNodeExample.scala (100%) create mode 100644 scripts/tutorial-patches/RocketConfigs.scala.patch create mode 100644 scripts/tutorial-patches/build.sbt.patch create mode 100755 scripts/tutorial-setup.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index e86da712..a1e67f18 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -143,6 +143,15 @@ jobs: name: Check commits of each submodule command: | .circleci/check-commit.sh + tutorial-setup-check: + executor: main-env + steps: + - checkout + - run: + name: Check that the tutorial-setup patches apply + command: | + scripts/tutorial-setup.sh + install-riscv-toolchain: executor: main-env steps: @@ -193,6 +202,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-rocket" + prepare-chipyard-sha3: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sha3" prepare-chipyard-hetero: executor: main-env steps: @@ -256,6 +270,11 @@ jobs: steps: - run-tests: project-key: "chipyard-rocket" + chipyard-sha3-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sha3" chipyard-hetero-run-tests: executor: main-env steps: @@ -343,6 +362,9 @@ workflows: - commit-on-master-check + # Attempt to apply the tutorial patches + - tutorial-setup-check + # Build extra tests - build-extra-tests: requires: @@ -354,6 +376,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-sha3: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-hetero: requires: - install-riscv-toolchain @@ -417,6 +444,10 @@ workflows: requires: - prepare-chipyard-rocket + - chipyard-sha3-run-tests: + requires: + - prepare-chipyard-sha3 + - chipyard-hetero-run-tests: requires: - prepare-chipyard-hetero diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 4393381e..7fa7c68c 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -42,6 +42,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build strings declare -A mapping mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" +mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 100418aa..ac63ff15 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -28,6 +28,8 @@ run_tracegen () { make tracegen -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ } +# TODO BUG: the run-binary command forces a rebuild of the simulator in CI +# instead, directly run the simulator binary case $1 in chipyard-rocket) run_bmark ${mapping[$1]} @@ -58,6 +60,10 @@ case $1 in $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal $LOCAL_SIM_DIR/simulator-chipyard-GemminiRocketConfig $GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal ;; + chipyard-sha3) + (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) + $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv + ;; tracegen) run_tracegen ${mapping[$1]} ;; diff --git a/build.sbt b/build.sbt index 0a4e2167..52fc3cb5 100644 --- a/build.sbt +++ b/build.sbt @@ -123,7 +123,9 @@ lazy val testchipip = (project in file("generators/testchipip")) .settings(commonSettings) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, gemmini, icenet, tracegen) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, + sha3, // On separate line to allow for cleaner tutorial-setup patches + gemmini, icenet, tracegen) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -195,7 +197,9 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, + sha3, // On separate line to allow for cleaner tutorial-setup patches + utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/boom b/generators/boom index 28003f77..5323559b 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 28003f7799fa9ea6cc89b56494dc77a3b427f6c9 +Subproject commit 5323559b3075d9cd86d2e87d7b00d1c16444c328 diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index d13f468a..dae6e055 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -70,6 +70,18 @@ class WithTracegenTop extends Config((site, here, up) => { }) +class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => { + case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => + r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length)) + } + case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) => + b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0)) + } + case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) +}) + + + // ------------------ // Multi-RoCC Support // ------------------ diff --git a/generators/chipyard/src/main/scala/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala similarity index 99% rename from generators/chipyard/src/main/scala/BoomConfigs.scala rename to generators/chipyard/src/main/scala/config/BoomConfigs.scala index bda5cccd..3804b97f 100644 --- a/generators/chipyard/src/main/scala/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} // --------------------- @@ -12,7 +10,7 @@ import freechips.rocketchip.config.{Config} class SmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link diff --git a/generators/chipyard/src/main/scala/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala similarity index 95% rename from generators/chipyard/src/main/scala/HeteroConfigs.scala rename to generators/chipyard/src/main/scala/config/HeteroConfigs.scala index c275433f..af2145e7 100644 --- a/generators/chipyard/src/main/scala/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} // --------------------- @@ -11,7 +9,7 @@ import freechips.rocketchip.config.{Config} class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link @@ -19,7 +17,7 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new boom.common.WithRenumberHarts ++ // avoid hartid overlap + new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap new boom.common.WithLargeBooms ++ // 3-wide boom new boom.common.WithNBoomCores(1) ++ // single-core boom new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) @@ -42,7 +40,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -64,7 +62,7 @@ class DualLargeBoomAndRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -89,7 +87,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -113,7 +111,7 @@ class LargeBoomAndRV32RocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -137,7 +135,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -160,7 +158,7 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.config.WithUART ++ new chipyard.config.WithControlCore ++ // add small control core to last hartid new chipyard.config.WithL2TLBs(1024) ++ - new boom.common.WithRenumberHarts ++ + new chipyard.config.WithRenumberHarts ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala similarity index 99% rename from generators/chipyard/src/main/scala/RocketConfigs.scala rename to generators/chipyard/src/main/scala/config/RocketConfigs.scala index c596dc29..bc1dab63 100644 --- a/generators/chipyard/src/main/scala/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} // -------------- @@ -11,7 +9,7 @@ import freechips.rocketchip.config.{Config} class RocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link diff --git a/generators/chipyard/src/main/scala/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala similarity index 98% rename from generators/chipyard/src/main/scala/TracegenConfigs.scala rename to generators/chipyard/src/main/scala/config/TracegenConfigs.scala index fccac401..b8f503c6 100644 --- a/generators/chipyard/src/main/scala/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -1,7 +1,5 @@ package chipyard -import chisel3._ - import freechips.rocketchip.config.{Config} import freechips.rocketchip.rocket.{DCacheParams} diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala new file mode 100644 index 00000000..0c74b581 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -0,0 +1,138 @@ +package chipyard + +import freechips.rocketchip.config.{Config} + +// This file is designed to accompany a live tutorial, with slides. +// For each of 4 phases, participants will customize and build a +// small demonstration config. + +// This file is designed to be used after running chipyard/scripts/tutorial-setup.sh, +// which removes the SHA3 accelerator RTL, and provides participants +// the experience of integrating external RTL. + +// This file was originally developed for the cancelled ASPLOS-2020 +// Chipyard tutorial. While the configs here work, the corresponding +// slideware has not yet been created + +// NOTE: Configs should be read bottom-up, since they are applied bottom-up + +// Tutorial Phase 1: Configure the cores, caches +class TutorialStarterConfig extends Config( + // IOBinders specify how to connect to IOs in our TestHarness + // These config fragments do not affect + new chipyard.iobinders.WithUARTAdapter ++ // Connect a SimUART adapter to display UART on stdout + new chipyard.iobinders.WithBlackBoxSimMem ++ // Connect simulated external memory + new chipyard.iobinders.WithTieOffInterrupts ++ // Do not simulate external interrupts + new chipyard.iobinders.WithTiedOffDebug ++ // Disconnect the debug module, since we use TSI for bring-up + new chipyard.iobinders.WithSimSerial ++ // Connect external SimSerial widget to drive TSI + + // Config fragments below this line affect hardware generation + // of the Top + new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core + new chipyard.config.WithNoGPIO ++ // Disable GPIOs. + new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM + new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op + new chipyard.config.WithUART ++ // Add a UART + + // CUSTOMIZE THE CORE + // Uncomment out one (or multiple) of the lines below, and choose + // how many cores you want. + // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores + // new boom.common.WithSmallBooms ++ // Specify all BOOM cores should be Small-sized (NOTE: other options are Medium/Large/Mega) + // new boom.common.WithNBoomCores(1) ++ // Specify we want some number of BOOM cores + + // CUSTOMIZE the L2 + // Uncomment this line, and specify a size if you want to have a L2 + // new freechips.rocketchip.subsystem.WithInclusiveCache(nBanks=1, nWays=4, capacityKB=128) ++ + + // For simpler designs, we want to minimize IOs on + // our Top. These config fragments remove unnecessary + // ports + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + // BaseConfig configures "bare" rocketchip system + new freechips.rocketchip.system.BaseConfig +) + + +// Tutorial Phase 2: Integrate a TileLink or AXI4 MMIO device +class TutorialMMIOConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithRenumberHarts ++ + new chipyard.config.WithUART ++ + + // Attach either a TileLink or AXI4 version of GCD + // Uncomment one of the below lines + // new chipyard.example.WithGCD(useAXI4=false) ++ // Use TileLink version + // new chipyard.example.WithGCD(useAXI4=true) ++ // Use AXI4 version + + // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.system.BaseConfig +) + +// Tutorial Phase 3: Integrate a SHA3 RoCC accelerator +class TutorialSha3Config extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithRenumberHarts ++ + new chipyard.config.WithUART ++ + + // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo + // new sha3.WithSha3Accel ++ + + // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.system.BaseConfig +) + +// Tutorial Phase 4: Integrate a Black-box verilog version of the SHA3 RoCC accelerator +class TutorialSha3BlackBoxConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithRenumberHarts ++ + new chipyard.config.WithUART ++ + + // Uncomment these lines once SHA3 is integrated + // new sha3.WithSha3BlackBox ++ // Specify we want the Black-box verilog version of Sha3 Ctrl + // new sha3.WithSha3Accel ++ + + // For this demonstration we assume the base system is a single-core Rocket, for fast elaboration + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.system.BaseConfig +) diff --git a/generators/chipyard/src/main/scala/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala similarity index 100% rename from generators/chipyard/src/main/scala/GCD.scala rename to generators/chipyard/src/main/scala/example/GCD.scala diff --git a/generators/chipyard/src/main/scala/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala similarity index 100% rename from generators/chipyard/src/main/scala/InitZero.scala rename to generators/chipyard/src/main/scala/example/InitZero.scala diff --git a/generators/chipyard/src/main/scala/NodeTypes.scala b/generators/chipyard/src/main/scala/example/NodeTypes.scala similarity index 100% rename from generators/chipyard/src/main/scala/NodeTypes.scala rename to generators/chipyard/src/main/scala/example/NodeTypes.scala diff --git a/generators/chipyard/src/main/scala/RegisterNodeExample.scala b/generators/chipyard/src/main/scala/example/RegisterNodeExample.scala similarity index 100% rename from generators/chipyard/src/main/scala/RegisterNodeExample.scala rename to generators/chipyard/src/main/scala/example/RegisterNodeExample.scala diff --git a/generators/sha3 b/generators/sha3 index 543adb4f..cec8db9d 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 543adb4ff1ac8b4f21f8d3ac5f7e865f8d109731 +Subproject commit cec8db9d6b3a602771cae63eaf6705baa3492f6a diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch new file mode 100644 index 00000000..eca5596d --- /dev/null +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -0,0 +1,13 @@ +diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala +index bc1dab6..1d84129 100644 +--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala ++++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala +@@ -293,7 +293,7 @@ class Sha3RocketConfig extends Config( + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ +- new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator ++// new sha3.WithSha3Accel ++ // add SHA3 rocc accelerator + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch new file mode 100644 index 00000000..b5eb87bf --- /dev/null +++ b/scripts/tutorial-patches/build.sbt.patch @@ -0,0 +1,35 @@ +diff --git a/build.sbt b/build.sbt +index 52fc3cb..875e3b4 100644 +--- a/build.sbt ++++ b/build.sbt +@@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) + + lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, +- sha3, // On separate line to allow for cleaner tutorial-setup patches ++// sha3, // On separate line to allow for cleaner tutorial-setup patches + gemmini, icenet, tracegen) + .settings(commonSettings) + +@@ -147,9 +147,9 @@ lazy val boom = (project in file("generators/boom")) + .dependsOn(rocketchip) + .settings(commonSettings) + +-lazy val sha3 = (project in file("generators/sha3")) +- .dependsOn(rocketchip, chisel_testers, midasTargetUtils) +- .settings(commonSettings) ++// lazy val sha3 = (project in file("generators/sha3")) ++// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(commonSettings) + + lazy val gemmini = (project in file("generators/gemmini")) + .dependsOn(rocketchip, chisel_testers, testchipip) +@@ -198,7 +198,7 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") + + lazy val firechip = (project in file("generators/firechip")) + .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, +- sha3, // On separate line to allow for cleaner tutorial-setup patches ++// sha3, // On separate line to allow for cleaner tutorial-setup patches + utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .settings( + commonSettings, diff --git a/scripts/tutorial-setup.sh b/scripts/tutorial-setup.sh new file mode 100755 index 00000000..88843f35 --- /dev/null +++ b/scripts/tutorial-setup.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e -x + +rm -rf generators/sha3 + +for p in scripts/tutorial-patches/*.patch +do + echo "Applying tutorial patch $p" + git apply $p +done From 7cf37b604e8e16383e6910d83a217e35b436bd03 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 30 Aug 2019 22:53:30 -0700 Subject: [PATCH 036/139] add ring topology system bus --- .../src/main/scala/config/RocketConfigs.scala | 19 +++++++++++++++++++ .../main/scala/config/TracegenConfigs.scala | 9 +++++++++ .../src/main/scala/TargetConfigs.scala | 10 ++++++++++ generators/testchipip | 2 +- 4 files changed, 39 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index bc1dab63..954c531b 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -363,3 +363,22 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket + +class RingSystemBusRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new testchipip.WithRingSystemBus ++ // Ring-topology system bus + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index b8f503c6..ead38869 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -32,3 +32,12 @@ class NonBlockingTraceGenL2Config extends Config( new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) + +class NonBlockingTraceGenL2RingConfig extends Config( + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTraceGenSuccessBinder ++ + new chipyard.config.WithTracegenTop ++ + new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ + new testchipip.WithRingSystemBus ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index dcc5be90..d13ba0a2 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -19,6 +19,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ +import testchipip.WithRingSystemBus import firesim.bridges._ import firesim.configs._ @@ -148,6 +149,15 @@ class FireSimGemminiRocketConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.GemminiRocketConfig) +//****************************************************************** +// Configuration with Ring topology SystemBus +//****************************************************************** +class FireSimRingSystemBusRocketConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.RingSystemBusRocketConfig) + //********************************************************************************** // Supernode Configurations, base off chipyard's RocketConfig //********************************************************************************** diff --git a/generators/testchipip b/generators/testchipip index f1b41df8..535eb6c5 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit f1b41df80d12b35f8f514c3fb72775203a7edd2d +Subproject commit 535eb6c58374b96c60e4e8217c709d60a66dab4a From d0bec3fba766bb5f3292dfc47e6aae0c183a8384 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 9 Mar 2020 18:06:41 -0700 Subject: [PATCH 037/139] Ariane Integration (#448) * [ariane/make] integrate ariane | have verilator be installed on path not in makefile * [misc] warn on verilator not found | search for v files | cleanup build.sbt + .gitignore * [firesim] bump * [ci] add midas ariane tests * [docker/ci] use new docker-image with verilator | re-elab on v changes for ariane | address comments * [ci] remove references to local verilator install * [verilator] update flags * [verilator] minimal set of flags for ariane * [ariane] bump ariane to master * [ci] revert to 4.016 verilator * [ci] install verilator to ci server | misc compile fixes * [ci/make] add longer ci timeout | update when assert is added in verilator sim * [firesim] bump for misc. updates * [make/ci] cleanup makefile and remove firesim tests of it * [docs/firesim] bump and clean docs * [firesim] bump * [ci] use remote verilator for midas tests * [misc] cleanup built.sbt more * [firesim] bump * [misc] bump build.sbt patch for tutorials * [firesim/ci] cleanup and bump firesim --- .circleci/README.md | 9 +-- .circleci/build-verilator.sh | 35 ------------ .circleci/config.yml | 56 +++++++++---------- .circleci/defaults.sh | 8 ++- .circleci/do-firesim-build.sh | 13 ++--- .circleci/do-rtl-build.sh | 12 ++-- .circleci/install-verilator.sh | 23 ++++++++ .circleci/run-firesim-tests.sh | 1 - .circleci/run-midasexamples-tests.sh | 13 ++--- .circleci/run-tests.sh | 13 +++-- .gitmodules | 3 + README.md | 5 +- build.sbt | 13 +++-- common.mk | 15 +++-- docs/Chipyard-Basics/Chipyard-Components.rst | 4 ++ docs/Generators/Ariane.rst | 14 +++++ docs/Generators/index.rst | 1 + generators/ariane | 1 + .../src/main/scala/ArianeConfigs.scala | 42 ++++++++++++++ .../chipyard/src/main/scala/Generator.scala | 1 + .../chipyard/src/main/scala/Subsystem.scala | 22 +++++--- .../chipyard/src/main/scala/TestSuites.scala | 41 ++++++++++++++ .../src/main/scala/config/BoomConfigs.scala | 2 - .../src/main/scala/BridgeBinders.scala | 6 +- .../firechip/src/main/scala/Generator.scala | 3 +- .../src/main/scala/TargetConfigs.scala | 11 ++++ scripts/centos-req.sh | 8 +++ scripts/tutorial-patches/build.sbt.patch | 21 ++----- scripts/ubuntu-req.sh | 8 +++ sims/firesim | 2 +- sims/vcs/Makefile | 20 ++++--- sims/verilator/Makefile | 44 +++++++++++---- sims/verilator/verilator.mk | 39 ------------- variables.mk | 8 +-- 34 files changed, 315 insertions(+), 202 deletions(-) delete mode 100755 .circleci/build-verilator.sh create mode 100755 .circleci/install-verilator.sh create mode 100644 docs/Generators/Ariane.rst create mode 160000 generators/ariane create mode 100644 generators/chipyard/src/main/scala/ArianeConfigs.scala delete mode 100644 sims/verilator/verilator.mk diff --git a/.circleci/README.md b/.circleci/README.md index 83fd3264..a50fc44a 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -16,9 +16,8 @@ For example: - prepare-rocketchip: requires: - install-riscv-toolchain - - install-verilator -This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` and `install-verilator` steps to run before it can run. +This specifies that the `prepare-rocketchip` job needs the `install-riscv-toolchain` steps to run before it can run. All jobs in the CI workflow are specified at the top of `config.yml` They specify a docker image to use (in this case a riscv-boom image since that is already available and works nicely) and an environment. @@ -36,7 +35,6 @@ This directory contains all the collateral for the Chipyard CI to work. The following is included: `build-toolchains.sh` # build either riscv-tools or esp-tools - `build-verilator.sh` # build verilator (remotely) `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work `do-rtl-build.sh` # use verilator to build a sim executable (remotely) `config.yml` # main circleci config script to enumerate jobs/workflows @@ -48,11 +46,10 @@ How things are setup for Chipyard The steps for CI to run are as follows. 1st, build the toolchains in parallel (note: `esp-tools` is currently not used in the run). The docker image sets up the `PATH` and `RISCV` variable so that `riscv-tools` is the default (currently the `env.sh` script that is created at tool build is unused). -2nd, install verilator using the `*.mk` to cache unique versions of verilator (mainly for if verilator is bumped). -3rd, create the simulator binary. +2nd, create the simulator binary. This requires the `riscv-tools` for `fesvr` and `verilator` to be able to build the binary. This stores all collateral for the tests (srcs, generated-srcs, sim binary, etc) to run "out of the gate" in the next job (make needs everything or else it will run again). -4th, finally run the tests that were wanted. +3rd, finally run the desired tests. Other CI Setup -------------- diff --git a/.circleci/build-verilator.sh b/.circleci/build-verilator.sh deleted file mode 100755 index a6780d1c..00000000 --- a/.circleci/build-verilator.sh +++ /dev/null @@ -1,35 +0,0 @@ -#!/bin/bash - -# build verilator - -# turn echo on and error on earliest command -set -ex - -# get shared variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -# call clean on exit -trap clean EXIT - -run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR - -if [ ! -d "$LOCAL_VERILATOR_DIR" ]; then - # set stricthostkeychecking to no (must happen before rsync) - run "echo \"Ping $SERVER\"" - - clean - - run "mkdir -p $REMOTE_CHIPYARD_DIR" - copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR - - run "make -j$NPROC -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR verilator_install" - - # copy so that circleci can cache - mkdir -p $LOCAL_CHIPYARD_DIR - mkdir -p $LOCAL_VERILATOR_DIR - copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR - copy $SERVER:$REMOTE_VERILATOR_DIR/ $LOCAL_VERILATOR_DIR - - cp -r $LOCAL_VERILATOR_DIR/install/bin/* $LOCAL_VERILATOR_DIR/install/share/verilator/bin/. -fi diff --git a/.circleci/config.yml b/.circleci/config.yml index a1e67f18..5fdc774d 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -4,9 +4,6 @@ version: 2.1 parameters: - verilator-cache-version: - type: string - default: "v3" tools-cache-version: type: string default: "v4" @@ -15,7 +12,7 @@ parameters: executors: main-env: docker: - - image: riscvboom/riscvboom-images:0.0.12 + - image: riscvboom/riscvboom-images:0.0.13 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit @@ -54,8 +51,8 @@ commands: - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e" - checkout - setup-tools-verilator: - description: "Get toolchain and verilator" + setup-tools: + description: "Get toolchain" parameters: tools-version: type: string @@ -69,9 +66,6 @@ commands: - restore_cache: keys: - << parameters.tools-version >>-installed-<< pipeline.parameters.tools-cache-version >>-{{ checksum "../<< parameters.tools-version >>.hash" }} - - restore_cache: - keys: - - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} prepare-rtl: description: "Run the prepare step of RTL" @@ -88,7 +82,7 @@ commands: type: string default: "do-rtl-build.sh" steps: - - setup-tools-verilator: + - setup-tools: tools-version: "<< parameters.tools-version >>" - run: name: Building << parameters.project-key >> subproject using Verilator @@ -117,7 +111,7 @@ commands: type: string default: "10m" steps: - - setup-tools-verilator: + - setup-tools: tools-version: "<< parameters.tools-version >>" - restore_cache: keys: @@ -166,18 +160,10 @@ jobs: executor: main-env steps: - ssh-checkout - - restore_cache: - keys: - - verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} - run: - name: Build Verilator + name: Install Verilator to remote command: | - .circleci/build-verilator.sh - no_output_timeout: 120m - - save_cache: - key: verilator-installed-<< pipeline.parameters.verilator-cache-version >>-{{ checksum "sims/verilator/verilator.mk" }} - paths: - - "/home/riscvuser/verilator" + .circleci/install-verilator.sh build-extra-tests: executor: main-env steps: @@ -262,9 +248,11 @@ jobs: - prepare-rtl: project-key: "fireboom" build-script: "do-firesim-build.sh" - - - + prepare-chipyard-ariane: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-ariane" chipyard-rocket-run-tests: executor: main-env steps: @@ -327,14 +315,19 @@ jobs: project-key: "fireboom" run-script: "run-firesim-tests.sh" timeout: "30m" - midasexamples-run-tests: executor: main-env steps: - - setup-tools-verilator + - setup-tools - run: name: Run midasexamples tests command: .circleci/run-midasexamples-tests.sh + chipyard-ariane-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-ariane" + # Order and dependencies of jobs to run workflows: version: 2 @@ -357,7 +350,6 @@ workflows: - install-esp-toolchain - # Build verilator - install-verilator - commit-on-master-check @@ -431,13 +423,17 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-ariane: + requires: + - install-riscv-toolchain + - install-verilator + # Run the respective tests # Run midasexamples test - midasexamples-run-tests: requires: - install-riscv-toolchain - - install-verilator # Run the example tests - chipyard-rocket-run-tests: @@ -486,3 +482,7 @@ workflows: requires: - prepare-fireboom - build-extra-tests + + - chipyard-ariane-run-tests: + requires: + - prepare-chipyard-ariane diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 7fa7c68c..552ac1db 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -20,22 +20,24 @@ clean () { # make parallelism NPROC=8 +# verilator version +VERILATOR_VERSION=v4.028 + # remote variables REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB REMOTE_RISCV_DIR=$REMOTE_WORK_DIR/riscv-tools-install REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard -REMOTE_VERILATOR_DIR=$REMOTE_WORK_DIR/verilator REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) LOCAL_CHECKOUT_DIR=$HOME/project LOCAL_RISCV_DIR=$HOME/riscv-tools-install LOCAL_ESP_DIR=$HOME/esp-tools-install LOCAL_CHIPYARD_DIR=$LOCAL_CHECKOUT_DIR -LOCAL_VERILATOR_DIR=$HOME/verilator LOCAL_SIM_DIR=$LOCAL_CHIPYARD_DIR/sims/verilator LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim @@ -53,3 +55,5 @@ mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" +mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" +mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config" diff --git a/.circleci/do-firesim-build.sh b/.circleci/do-firesim-build.sh index 709f3d0b..7d86c779 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/do-firesim-build.sh @@ -28,18 +28,15 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv/esp-tools, verilator, and chipyard to remote +# copy over riscv/esp-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_VERILATOR_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then TOOLS_DIR=$REMOTE_ESP_DIR @@ -54,9 +51,11 @@ fi # Build MIDAS-level verilator sim FIRESIM_VARS="${mapping[$1]}" run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$VERILATOR_BIN_DIR:\$PATH\"; export FIRESIM_ENV_SOURCED=1; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \ +run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + export FIRESIM_ENV_SOURCED=1; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator" run "rm -rf $REMOTE_CHIPYARD_DIR/project" diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index 5276080f..52c920f5 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -21,11 +21,9 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv/esp-tools, verilator, and chipyard to remote +# copy over riscv/esp-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_VERILATOR_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" run "cp -r ~/.sbt $REMOTE_WORK_DIR" @@ -56,9 +54,11 @@ fi # enter the verilator directory and build the specific config on remote server run "make -C $REMOTE_SIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \ - make -j$NPROC -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" +run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ + make -j$NPROC -C $REMOTE_SIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$1]}" run "rm -rf $REMOTE_CHIPYARD_DIR/project" # copy back the final build diff --git a/.circleci/install-verilator.sh b/.circleci/install-verilator.sh new file mode 100755 index 00000000..86d1ae04 --- /dev/null +++ b/.circleci/install-verilator.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +# move verilator to the remote server + +# turn echo on and error on earliest command +set -ex + +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +run_script $LOCAL_CHIPYARD_DIR/.circleci/clean-old-files.sh $CI_DIR + +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" + +run "git clone http://git.veripool.org/git/verilator $REMOTE_VERILATOR_DIR; \ + cd $REMOTE_VERILATOR_DIR; \ + git checkout $VERILATOR_VERSION; \ + autoconf; \ + export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR; \ + ./configure; \ + make -j$NPROC;" diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh index 8cdf9e81..d1111e60 100755 --- a/.circleci/run-firesim-tests.sh +++ b/.circleci/run-firesim-tests.sh @@ -7,7 +7,6 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh -export PATH=$LOCAL_VERILATOR_DIR/install/bin:$PATH export FIRESIM_ENV_SOURCED=1 SIMULATION_ARGS="${mapping[$1]}" diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 7d31ac11..467dc0e9 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -19,13 +19,11 @@ run "echo \"Ping $SERVER\"" clean -# copy over riscv-tools, verilator, and chipyard to remote +# copy over riscv-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" -run "mkdir -p $REMOTE_VERILATOR_DIR" run "mkdir -p $REMOTE_RISCV_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR -copy $LOCAL_VERILATOR_DIR/ $SERVER:$REMOTE_VERILATOR_DIR copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR # Copy ivy2 and sbt directories @@ -35,12 +33,13 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -VERILATOR_BIN_DIR=$REMOTE_VERILATOR_DIR/install/bin # Run midasexamples test run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" -run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ - export PATH=\"$VERILATOR_BIN_DIR:\$PATH\"; export FIRESIM_ENV_SOURCED=1; \ - export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; \ +run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export FIRESIM_ENV_SOURCED=1; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" TARGET_PROJECT=midasexamples test" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index ac63ff15..480908c9 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -9,14 +9,12 @@ set -ex SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" source $SCRIPT_DIR/defaults.sh -export VERILATOR_ROOT=$LOCAL_VERILATOR_DIR/install/share/verilator - run_bmark () { - make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ + make run-bmark-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ } run_asm () { - make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ + make run-asm-tests-fast -j$NPROC -C $LOCAL_SIM_DIR $@ } run_both () { @@ -25,7 +23,7 @@ run_both () { } run_tracegen () { - make tracegen -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR $@ + make tracegen -C $LOCAL_SIM_DIR $@ } # TODO BUG: the run-binary command forces a rebuild of the simulator in CI @@ -47,7 +45,7 @@ case $1 in export RISCV=$LOCAL_ESP_DIR export LD_LIBRARY_PATH=$LOCAL_ESP_DIR/lib export PATH=$RISCV/bin:$PATH - make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR VERILATOR_INSTALL_DIR=$LOCAL_VERILATOR_DIR ${mapping[$1]} + make run-rv64uv-p-asm-tests -j$NPROC -C $LOCAL_SIM_DIR ${mapping[$1]} ;; chipyard-gemmini) export RISCV=$LOCAL_ESP_DIR @@ -70,6 +68,9 @@ case $1 in tracegen-boom) run_tracegen ${mapping[$1]} ;; + chipyard-ariane) + make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv + ;; *) echo "No set of tests for $1. Did you spell it right?" exit 1 diff --git a/.gitmodules b/.gitmodules index 88096baf..34846d61 100644 --- a/.gitmodules +++ b/.gitmodules @@ -113,6 +113,9 @@ [submodule "software/firemarshal"] path = software/firemarshal url = https://github.com/firesim/FireMarshal.git +[submodule "generators/ariane"] + path = generators/ariane + url = https://github.com/ucb-bar/ariane-wrapper.git [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git diff --git a/README.md b/README.md index 26f32cf5..0eec2d87 100644 --- a/README.md +++ b/README.md @@ -10,14 +10,14 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. ## Resources * Chipyard Documentation: https://chipyard.readthedocs.io/ -* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf +* Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf * Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf ## Need help? @@ -63,3 +63,4 @@ These publications cover many of the internal components used in Chipyard. Howev [rocket-chip]: https://github.com/freechipsproject/rocket-chip [boom]: https://github.com/ucb-bar/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ +[ariane]: https://github.com/pulp-platform/ariane/ diff --git a/build.sbt b/build.sbt index 52fc3cb5..a633066f 100644 --- a/build.sbt +++ b/build.sbt @@ -125,7 +125,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen) + gemmini, icenet, tracegen, ariane) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -147,6 +147,10 @@ lazy val boom = (project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) +lazy val ariane = (project in file("generators/ariane")) + .dependsOn(rocketchip) + .settings(commonSettings) + lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) .settings(commonSettings) @@ -196,12 +200,9 @@ lazy val sifive_cache = (project in file("generators/sifive-cache")).settings( lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") -lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, - sha3, // On separate line to allow for cleaner tutorial-setup patches - utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") +lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) + .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) ) - diff --git a/common.mk b/common.mk index 839e7b54..bf40e602 100644 --- a/common.mk +++ b/common.mk @@ -6,10 +6,12 @@ SHELL=/bin/bash ######################################################################################### # variables to get all *.scala files ######################################################################################### -lookup_scala_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.scala" -print 2> /dev/null) +lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS=$(addprefix $(base_dir)/,generators sims/firesim/sim) -SCALA_SOURCES=$(call lookup_scala_srcs,$(SOURCE_DIRS)) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) +SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) +VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) +ARIANE_VLOG_SOURCES = $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v) ######################################################################################### # rocket and testchipip classes @@ -42,7 +44,8 @@ $(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null -generator_temp: $(SCALA_SOURCES) $(sim_files) +# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile +generator_temp: $(SCALA_SOURCES) $(ARIANE_VLOG_SOURCES) $(sim_files) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" @@ -64,7 +67,7 @@ HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNES $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp @echo "" > /dev/null -firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) +firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) # DOC include end: FirrtlCompiler @@ -89,7 +92,7 @@ harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp # remove duplicate files and headers in list of simulation file inputs ######################################################################################## $(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes) - awk '{print $1;}' $^ | sort -u | grep -v '.*\.h$$' > $@ + awk '{print $1;}' $^ | sort -u | grep -v '.*\.\(svh\|h\)$$' > $@ ######################################################################################### # helper rule to just make verilog files diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index cbca299f..d3ec9a95 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -20,6 +20,10 @@ Processor Cores An out-of-order RISC-V core. See :ref:`Berkeley Out-of-Order Machine (BOOM)` for more information. +**Ariane Core** + An in-order RISC-V core written in System Verilog. + See :ref:`Ariane Core` for more information. + Accelerators ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/Generators/Ariane.rst b/docs/Generators/Ariane.rst new file mode 100644 index 00000000..e58f9dfc --- /dev/null +++ b/docs/Generators/Ariane.rst @@ -0,0 +1,14 @@ +Ariane Core +==================================== + +`Ariane `__ is a 6-stage in-order scalar processor core, originally developed at ETH-Zurich by F. Zaruba and L. Benini. +The `Ariane core` is wrapped in an `Ariane tile` so it can be used as a component within the `Rocket Chip SoC generator`. +The core by itself exposes an AXI interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals. + +.. Warning:: Since the core uses an AXI interface to connect to memory, it is highly recommended to use the core in a single-core setup (since AXI is a non-coherent memory interface). + +While the core itself is not a generator, we expose the same parameterization that the Ariane core provides (i.e. change branch prediction parameters). + +.. Warning:: This target does not support Verilator simulation at this time. Please use VCS. + +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 90db4ae8..675318d9 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -27,4 +27,5 @@ so changes to the generators themselves will automatically be used when building TestChipIP SiFive-Generators SHA3 + Ariane diff --git a/generators/ariane b/generators/ariane new file mode 160000 index 00000000..145b5ed1 --- /dev/null +++ b/generators/ariane @@ -0,0 +1 @@ +Subproject commit 145b5ed106efd0b22c2105c20722ab303fa4039b diff --git a/generators/chipyard/src/main/scala/ArianeConfigs.scala b/generators/chipyard/src/main/scala/ArianeConfigs.scala new file mode 100644 index 00000000..e0cb771e --- /dev/null +++ b/generators/chipyard/src/main/scala/ArianeConfigs.scala @@ -0,0 +1,42 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +// --------------------- +// Ariane Configs +// --------------------- + +class ArianeConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithSimAXIMem ++ // drive the master AXI4 memory with a SimAXIMem + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new ariane.WithNArianeCores(1) ++ // single Ariane core + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + +class dmiArianeConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithSimAXIMem ++ + new chipyard.iobinders.WithTiedOffSerial ++ + new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation + new chipyard.config.WithNoGPIO ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new ariane.WithNArianeCores(1) ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala index 32619f29..4baba357 100644 --- a/generators/chipyard/src/main/scala/Generator.scala +++ b/generators/chipyard/src/main/scala/Generator.scala @@ -14,6 +14,7 @@ object Generator extends GeneratorApp { implicit val p: Parameters = params TestSuiteHelper.addRocketTestSuites TestSuiteHelper.addBoomTestSuites + TestSuiteHelper.addArianeTestSuites // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index d8635cd5..96443a9f 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -22,24 +22,26 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} +import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} - -trait HasBoomAndRocketTiles extends HasTiles +trait HasChipyardTiles extends HasTiles with CanHavePeripheryPLIC with CanHavePeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem => - val module: HasBoomAndRocketTilesModuleImp + val module: HasChipyardTilesModuleImp protected val rocketTileParams = p(RocketTilesKey) protected val boomTileParams = p(BoomTilesKey) + protected val arianeTileParams = p(ArianeTilesKey) // crossing can either be per tile or global (aka only 1 crossing specified) private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) + private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size) - val allTilesInfo = (rocketTileParams ++ boomTileParams) zip (rocketCrossings ++ boomCrossings) + val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings) // Make a tile and wire its nodes into the system, // according to the specified type of clock crossing. @@ -59,6 +61,10 @@ trait HasBoomAndRocketTiles extends HasTiles val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately } + case a: ArianeTileParams => { + val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) + (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately + } } connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) @@ -79,14 +85,14 @@ trait HasBoomAndRocketTiles extends HasTiles }.toList } -trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp +trait HasChipyardTilesModuleImp extends HasTilesModuleImp with HasPeripheryDebugModuleImp { - val outer: HasBoomAndRocketTiles + val outer: HasChipyardTiles } class Subsystem(implicit p: Parameters) extends BaseSubsystem - with HasBoomAndRocketTiles + with HasChipyardTiles { override lazy val module = new SubsystemModuleImp(this) @@ -95,7 +101,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer) with HasResetVectorWire - with HasBoomAndRocketTilesModuleImp + with HasChipyardTilesModuleImp { tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) => wire.hartid := i.U diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 05c4bf6e..7d901c62 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -9,6 +9,7 @@ import freechips.rocketchip.util.{GeneratorApp} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} import boom.common.{BoomTilesKey} +import ariane.{ArianeTilesKey} /** * A set of pre-chosen regression tests @@ -139,4 +140,44 @@ object TestSuiteHelper TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } + + /** + * Add Ariane tests (asm, bmark, regression) + */ + def addArianeTestSuites(implicit p: Parameters) = { + val xlen = p(XLen) + p(ArianeTilesKey).find(_.hartId == 0).map { tileParams => + val coreParams = tileParams.core + val vm = coreParams.useVM + val env = if (vm) List("p","v") else List("p") + coreParams.fpu foreach { case cfg => + if (xlen == 32) { + TestGeneration.addSuites(env.map(rv32uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv32ud)) + } else { + TestGeneration.addSuite(rv32udBenchmarks) + TestGeneration.addSuites(env.map(rv64uf)) + if (cfg.fLen >= 64) + TestGeneration.addSuites(env.map(rv64ud)) + } + } + if (coreParams.useAtomics) { + if (tileParams.dcache.flatMap(_.scratch).isEmpty) + TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + else + TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + } + if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + val (rvi, rvu) = + if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) + else ((if (vm) rv32i else rv32pi), rv32u) + + TestGeneration.addSuites(rvi.map(_("p"))) + TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + TestGeneration.addSuite(benchmarks) + TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + } + } + } diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 3804b97f..35934eab 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -6,7 +6,6 @@ import freechips.rocketchip.config.{Config} // BOOM Configs // --------------------- - class SmallBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts @@ -26,7 +25,6 @@ class SmallBoomConfig extends Config( new boom.common.WithNBoomCores(1) ++ // single-core boom new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system - class MediumBoomConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 9a19e6ef..cfa1a873 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -21,11 +21,12 @@ import midas.targetutils.{MemModelAnnotation} import firesim.bridges._ import firesim.configs.MemModelKey import tracegen.HasTraceGenTilesModuleImp +import ariane.ArianeTile import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} -import chipyard.HasBoomAndRocketTilesModuleImp +import chipyard.HasChipyardTilesModuleImp class WithSerialBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq @@ -67,7 +68,7 @@ class WithTraceGenBridge extends OverrideIOBinder({ }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (c, r, s, target: HasBoomAndRocketTilesModuleImp) => { + (c, r, s, target: HasChipyardTilesModuleImp) => { target.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) @@ -84,6 +85,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ case _ => Nil } } + case a: ArianeTile => Nil } Nil } diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 11598719..18aeefc8 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -26,6 +26,7 @@ trait HasTestSuites { def addTestSuites(targetName: String, params: Parameters) { TestSuiteHelper.addRocketTestSuites(params) TestSuiteHelper.addBoomTestSuites(params) + TestSuiteHelper.addArianeTestSuites(params) TestGeneration.addSuite(FastBlockdevTests) TestGeneration.addSuite(SlowBlockdevTests) if (!targetName.contains("NoNIC")) @@ -61,7 +62,7 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike { override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs lazy val generatorArgs = GeneratorArgs(args) lazy val genDir = new File(names.targetDir) - // The only reason this is not generateFirrtl; generateAnno is that we need to use a different + // The only reason this is not generateFirrtl; generateAnno is that we need to use a different // JsonProtocol to properly write out the annotations. Fix once the generated are unified elaborate generateTestSuiteMakefrags diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d13ba0a2..e07a73a6 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -19,6 +19,7 @@ import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ +import ariane.ArianeTilesKey import testchipip.WithRingSystemBus import firesim.bridges._ @@ -76,6 +77,7 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) // Enables tracing on all cores class WithTraceIO extends Config((site, here, up) => { case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) case TracePortKey => Some(TracePortParams()) }) @@ -165,3 +167,12 @@ class SupernodeFireSimRocketConfig extends Config( new WithNumNodes(4) ++ new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB new FireSimRocketConfig) + +//********************************************************************************** +//* Ariane Configurations +//*********************************************************************************/ +class FireSimArianeConfig extends Config( + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks ++ + new chipyard.ArianeConfig) diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index 8fac61af..30b9fe70 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -1,5 +1,7 @@ #!/bin/bash +set -ex + sudo yum groupinstall -y "Development tools" sudo yum install -y gmp-devel mpfr-devel libmpc-devel zlib-devel vim git java java-devel curl https://bintray.com/sbt/rpm/rpm | sudo tee /etc/yum.repos.d/bintray-sbt-rpm.repo @@ -16,3 +18,9 @@ sudo yum install -y centos-release-scl sudo yum install -y devtoolset-8-make # install DTC sudo yum install -y dtc + +# install verilator +git clone http://git.veripool.org/git/verilator +cd verilator +git checkout v4.028 +autoconf && ./configure && make -j16 && sudo make install diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index b5eb87bf..422c59c8 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,5 +1,5 @@ diff --git a/build.sbt b/build.sbt -index 52fc3cb..875e3b4 100644 +index a633066..3df8b74 100644 --- a/build.sbt +++ b/build.sbt @@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) @@ -8,28 +8,19 @@ index 52fc3cb..875e3b4 100644 .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen) + gemmini, icenet, tracegen, ariane) .settings(commonSettings) -@@ -147,9 +147,9 @@ lazy val boom = (project in file("generators/boom")) +@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val sha3 = (project in file("generators/sha3")) - .dependsOn(rocketchip, chisel_testers, midasTargetUtils) - .settings(commonSettings) -+// lazy val sha3 = (project in file("generators/sha3")) -+// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) -+// .settings(commonSettings) ++//lazy val sha3 = (project in file("generators/sha3")) ++// .dependsOn(rocketchip, chisel_testers, midasTargetUtils) ++// .settings(commonSettings) lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) -@@ -198,7 +198,7 @@ lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") - - lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, hwacha, chipyard, icenet, testchipip, sifive_blocks, sifive_cache, -- sha3, // On separate line to allow for cleaner tutorial-setup patches -+// sha3, // On separate line to allow for cleaner tutorial-setup patches - utilities, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") - .settings( - commonSettings, diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index 1858c3a4..da626052 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -1,5 +1,7 @@ #!/bin/bash +set -ex + sudo apt-get install -y build-essential bison flex sudo apt-get install -y libgmp-dev libmpfr-dev libmpc-dev zlib1g-dev vim git default-jdk default-jre # install sbt: https://www.scala-sbt.org/release/docs/Installing-sbt-on-Linux.html @@ -17,3 +19,9 @@ sudo apt-get install -y libgtk-3-dev sudo apt-get install -y python3-pip python3.6-dev rsync libguestfs-tools expat ctags # install DTC sudo apt-get install -y device-tree-compiler + +# install verilator +git clone http://git.veripool.org/git/verilator +cd verilator +git checkout v4.028 +autoconf && ./configure && make -j16 && sudo make install diff --git a/sims/firesim b/sims/firesim index 2f033c21..9f970576 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 2f033c2101612097fa27cf1768a280c980125b39 +Subproject commit 9f9705762a7e19b1e9ff77a92f7f4413ffe83265 diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e5c6e1be..e829047c 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -62,20 +62,25 @@ VCS_NONCC_OPTS = \ +v2k \ +vcs+lic+wait \ +vc+list \ - -f $(sim_common_files) \ + -error=noZMMCM \ + -assert svaext \ -sverilog \ + +libext+.v \ +incdir+$(build_dir) \ + -f $(sim_common_files) \ + $(sim_vsrcs) + +VCS_DEFINES = \ + +define+VCS \ +define+CLOCK_PERIOD=1.0 \ - $(sim_vsrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE_MEM_INIT \ +define+RANDOMIZE_REG_INIT \ +define+RANDOMIZE_GARBAGE_ASSIGN \ - +define+RANDOMIZE_INVALID_ASSIGN \ - +libext+.v + +define+RANDOMIZE_INVALID_ASSIGN -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) ######################################################################################### # vcs simulator rules @@ -84,9 +89,10 @@ $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug) : $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ - +define+DEBUG -debug_pp + +define+DEBUG \ + -debug_pp ######################################################################################### # create a vcs vpd rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 140f54fd..13e7d201 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -1,6 +1,9 @@ ######################################################################################### # verilator makefile ######################################################################################### +ifeq ($(shell which verilator),) +$(error Did not find Verilator in PATH. Make sure all requirements are installed) +endif ######################################################################################### # general path variables @@ -38,12 +41,11 @@ debug: $(sim_debug) # import other necessary rules and variables ######################################################################################### include $(base_dir)/common.mk -include $(sim_dir)/verilator.mk ######################################################################################### # verilator binary and flags ######################################################################################### -VERILATOR := $(INSTALLED_VERILATOR) --cc --exe +VERILATOR := verilator --cc --exe CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim @@ -54,17 +56,38 @@ VERILATOR_CC_OPTS = \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ -LDFLAGS "$(LDFLAGS)" +# default flags added for ariane +ARIANE_VERILATOR_FLAGS = \ + --unroll-count 256 \ + -Werror-PINMISSING \ + -Werror-IMPLICIT \ + -Wno-fatal \ + -Wno-PINCONNECTEMPTY \ + -Wno-ASSIGNDLY \ + -Wno-DECLFILENAME \ + -Wno-UNUSED \ + -Wno-UNOPTFLAT \ + -Wno-BLKANDNBLK \ + -Wno-style \ + -Wall + +# normal flags used for chipyard builds (that are incompatible with ariane) +CHIPYARD_VERILATOR_FLAGS = \ + --assert + VERILATOR_NONCC_OPTS = \ --top-module $(VLOG_MODEL) \ - +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ - +define+STOP_COND=\$$c\(\"done_reset\"\) \ - --assert \ + $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ --output-split-cfuncs 100 \ - $(sim_vsrcs) \ - -f $(sim_common_files) + -f $(sim_common_files) \ + $(sim_vsrcs) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) +VERILATOR_DEFINES = \ + +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ + +define+STOP_COND=\$$c\(\"done_reset\"\) + +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) ######################################################################################### # verilator build paths and file names @@ -81,14 +104,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### - -$(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) +$(model_mk): $(sim_vsrcs) $(sim_common_files) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR) +$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" diff --git a/sims/verilator/verilator.mk b/sims/verilator/verilator.mk deleted file mode 100644 index 12ab165d..00000000 --- a/sims/verilator/verilator.mk +++ /dev/null @@ -1,39 +0,0 @@ -######################################################################################### -# verilator installation makefrag -######################################################################################### - -######################################################################################### -# verilator version, binary, and path -######################################################################################### -VERILATOR_VERSION = 4.016 -VERILATOR_INSTALL_DIR ?= verilator_install -VERILATOR_SRCDIR = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION) -INSTALLED_VERILATOR = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator) - -######################################################################################### -# build and install our own verilator to work around versioning issues -######################################################################################### -$(INSTALLED_VERILATOR): $(VERILATOR_SRCDIR)/bin/verilator - $(MAKE) -C $(VERILATOR_SRCDIR) installbin installdata - touch $@ - -.PHONY: -verilator_install: $(INSTALLED_VERILATOR) - -$(VERILATOR_SRCDIR)/bin/verilator: $(VERILATOR_SRCDIR)/Makefile - $(MAKE) -C $(VERILATOR_SRCDIR) verilator_bin - touch $@ - -$(VERILATOR_SRCDIR)/Makefile: $(VERILATOR_SRCDIR)/configure - mkdir -p $(dir $@) - cd $(dir $@) && ./configure --prefix=$(abspath $(VERILATOR_INSTALL_DIR)/install) - -$(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz - rm -rf $(dir $@) - mkdir -p $(dir $@) - cat $^ | tar -xz --strip-components=1 -C $(dir $@) - touch $@ - -$(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz: - mkdir -p $(dir $@) - wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@ diff --git a/variables.mk b/variables.mk index d124fed6..8a1bb1df 100644 --- a/variables.mk +++ b/variables.mk @@ -114,11 +114,11 @@ HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir # files that contain lists of files needed for VCS or Verilator simulation -sim_files ?= $(build_dir)/sim_files.f -sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f -sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f +sim_files ?= $(build_dir)/sim_files.f +sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f +sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f # single file that contains all files needed for VCS or Verilator simulation (unique and without .h's) -sim_common_files ?= $(build_dir)/sim_files.common.f +sim_common_files ?= $(build_dir)/sim_files.common.f ######################################################################################### # java arguments used in sbt From 0a66a3504714417683fd5af21752ac02d8f51932 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 9 Mar 2020 21:40:38 -0700 Subject: [PATCH 038/139] [GCD] Fix GCD example (#465) --- generators/chipyard/src/main/scala/example/GCD.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala index 049fa876..475e0bdc 100644 --- a/generators/chipyard/src/main/scala/example/GCD.scala +++ b/generators/chipyard/src/main/scala/example/GCD.scala @@ -125,7 +125,7 @@ trait GCDModule extends HasRegMap { gcd.valid := impl.io.output_valid impl.io.output_ready := gcd.ready - status := Cat(impl.io.input_ready, impl.io.output_ready) + status := Cat(impl.io.input_ready, impl.io.output_valid) io.gcd_busy := impl.io.busy regmap( From f517070432ddfede9a0bc93cb241ee01b4d4cb65 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 10 Mar 2020 11:33:06 -0700 Subject: [PATCH 039/139] Move DockerImage into Chipyard + Bump BOOM (#463) * [ci] move docker image to chipyard [ci skip] * [ci] bump with new image * [boom] bump --- .circleci/config.yml | 2 +- .circleci/images/Dockerfile | 196 ++++++++++++++++++++++++++++++++++++ .circleci/images/README.md | 18 ++++ generators/boom | 2 +- 4 files changed, 216 insertions(+), 2 deletions(-) create mode 100644 .circleci/images/Dockerfile create mode 100644 .circleci/images/README.md diff --git a/.circleci/config.yml b/.circleci/config.yml index 5fdc774d..dfadcba6 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: riscvboom/riscvboom-images:0.0.13 + - image: ucbbar/chipyard-image:1.0.0 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit diff --git a/.circleci/images/Dockerfile b/.circleci/images/Dockerfile new file mode 100644 index 00000000..807c15f0 --- /dev/null +++ b/.circleci/images/Dockerfile @@ -0,0 +1,196 @@ +### Note: This DockerFile is adapted from https://github.com/CircleCI-Public/example-images/openjdk + +FROM openjdk:11.0.1-jdk-sid + +# man directory is missing in some base images +# https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=863199 +RUN apt-get update \ + && mkdir -p /usr/share/man/man1 \ + && apt-get install -y \ + bzip2 \ + ca-certificates \ + curl \ + git \ + gnupg \ + gzip \ + locales \ + mercurial \ + netcat \ + net-tools \ + openssh-client \ + parallel \ + sudo \ + tar \ + unzip \ + wget \ + xvfb \ + zip + +# Set timezone to UTC by default +RUN ln -sf /usr/share/zoneinfo/Etc/UTC /etc/localtime + +# Use unicode +RUN locale-gen C.UTF-8 || true +ENV LANG=C.UTF-8 + +# install jq +RUN JQ_URL="https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/jq-latest" \ + && curl --silent --show-error --location --fail --retry 3 --output /usr/bin/jq $JQ_URL \ + && chmod +x /usr/bin/jq \ + && jq --version + +# Install Docker + +# Docker.com returns the URL of the latest binary when you hit a directory listing +# We curl this URL and `grep` the version out. +# The output looks like this: + +#> # To install, run the following commands as root: +#> curl -fsSLO https://download.docker.com/linux/static/stable/x86_64/docker-17.05.0-ce.tgz && tar --strip-components=1 -xvzf docker-17.05.0-ce.tgz -C /usr/local/bin +#> +#> # Then start docker in daemon mode: +#> /usr/local/bin/dockerd + +RUN set -ex \ + && export DOCKER_VERSION=$(curl --silent --fail --retry 3 https://download.docker.com/linux/static/stable/x86_64/ | grep -o -e 'docker-[.0-9]*-ce\.tgz' | sort -r | head -n 1) \ + && DOCKER_URL="https://download.docker.com/linux/static/stable/x86_64/${DOCKER_VERSION}" \ + && echo Docker URL: $DOCKER_URL \ + && curl --silent --show-error --location --fail --retry 3 --output /tmp/docker.tgz "${DOCKER_URL}" \ + && ls -lha /tmp/docker.tgz \ + && tar -xz -C /tmp -f /tmp/docker.tgz \ + && mv /tmp/docker/* /usr/bin \ + && rm -rf /tmp/docker /tmp/docker.tgz \ + && which docker \ + && (docker version || true) + +# docker compose +RUN COMPOSE_URL="https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/docker-compose-latest" \ + && curl --silent --show-error --location --fail --retry 3 --output /usr/bin/docker-compose $COMPOSE_URL \ + && chmod +x /usr/bin/docker-compose \ + && docker-compose version + +# install dockerize +RUN DOCKERIZE_URL="https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/dockerize-latest.tar.gz" \ + && curl --silent --show-error --location --fail --retry 3 --output /tmp/dockerize-linux-amd64.tar.gz $DOCKERIZE_URL \ + && tar -C /usr/local/bin -xzvf /tmp/dockerize-linux-amd64.tar.gz \ + && rm -rf /tmp/dockerize-linux-amd64.tar.gz \ + && dockerize --version + +RUN groupadd --gid 3434 riscvuser \ + && useradd --uid 3434 --gid riscvuser --shell /bin/bash --create-home riscvuser \ + && echo 'riscvuser ALL=NOPASSWD: ALL' >> /etc/sudoers.d/50-riscvuser \ + && echo 'Defaults env_keep += "DEBIAN_FRONTEND"' >> /etc/sudoers.d/env_keep + +# BEGIN IMAGE CUSTOMIZATIONS + +# cacerts from OpenJDK 9-slim to workaround http://bugs.java.com/view_bug.do?bug_id=8189357 +# AND https://github.com/docker-library/openjdk/issues/145 +# +# Created by running: +# docker run --rm openjdk:9-slim cat /etc/ssl/certs/java/cacerts | # aws s3 cp - s3://circle-downloads/circleci-images/cache/linux-amd64/openjdk-9-slim-cacerts --acl public-read +RUN if java -fullversion 2>&1 | grep -q '"9.'; then curl --silent --show-error --location --fail --retry 3 --output /etc/ssl/certs/java/cacerts https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/openjdk-9-slim-cacerts; fi + +# Install Maven Version: 3.6.3 +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/apache-maven.tar.gz https://www.apache.org/dist/maven/maven-3/3.6.3/binaries/apache-maven-3.6.3-bin.tar.gz \ + && tar xf /tmp/apache-maven.tar.gz -C /opt/ \ + && rm /tmp/apache-maven.tar.gz \ + && ln -s /opt/apache-maven-* /opt/apache-maven \ + && /opt/apache-maven/bin/mvn -version + +# Install Ant Version: 1.10.5 +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/apache-ant.tar.gz https://archive.apache.org/dist/ant/binaries/apache-ant-1.10.5-bin.tar.gz \ + && tar xf /tmp/apache-ant.tar.gz -C /opt/ \ + && ln -s /opt/apache-ant-* /opt/apache-ant \ + && rm -rf /tmp/apache-ant.tar.gz \ + && /opt/apache-ant/bin/ant -version + +ENV ANT_HOME=/opt/apache-ant + +# Install Gradle Version: 5.0 +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/gradle.zip https://services.gradle.org/distributions/gradle-5.0-bin.zip \ + && unzip -d /opt /tmp/gradle.zip \ + && rm /tmp/gradle.zip \ + && ln -s /opt/gradle-* /opt/gradle \ + && /opt/gradle/bin/gradle -version + +# Install sbt from https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/sbt-latest.tgz +RUN curl --silent --show-error --location --fail --retry 3 --output /tmp/sbt.tgz https://circle-downloads.s3.amazonaws.com/circleci-images/cache/linux-amd64/sbt-latest.tgz \ + && tar -xzf /tmp/sbt.tgz -C /opt/ \ + && rm /tmp/sbt.tgz \ + && /opt/sbt/bin/sbt sbtVersion + +# Install openjfx +RUN apt-get update +RUN apt-get install -y --no-install-recommends openjfx + +# Add build-essential +RUN apt-get install -y build-essential + +# Add RISCV toolchain necessary dependencies +RUN apt-get install -y \ + autoconf \ + automake \ + autotools-dev \ + babeltrace \ + bc \ + bison \ + curl \ + device-tree-compiler \ + expat \ + flex \ + gawk \ + gperf \ + libexpat-dev \ + libgmp-dev \ + libmpc-dev \ + libmpfr-dev \ + libtool \ + libusb-1.0-0-dev \ + patchutils \ + pkg-config \ + python \ + python-pexpect \ + python3 \ + texinfo \ + zlib1g-dev \ + rsync + +# Add minimal QEMU dependencies +RUN apt-get install -y \ + libfdt-dev \ + libglib2.0-dev \ + libpixman-1-dev + +# Install verilator +RUN git clone http://git.veripool.org/git/verilator \ + && cd verilator \ + && git checkout v4.028 \ + && autoconf && ./configure && make && make install + +# Update PATH for Java tools +ENV PATH="/opt/sbt/bin:/opt/apache-maven/bin:/opt/apache-ant/bin:/opt/gradle/bin:$PATH" + +# Add HOME environment variable +ENV HOME="/home/riscvuser" + +# Update PATH for RISCV toolchain (note: hardcoded for CircleCI) +ENV RISCV="$HOME/riscv-tools-install" +ENV LD_LIBRARY_PATH="$RISCV/lib" +ENV PATH="$RISCV/bin:$PATH" + +WORKDIR $HOME +USER riscvuser + +# smoke test with path +RUN mvn -version \ + && ant -version \ + && gradle -version \ + && sbt sbtVersion \ + && verilator --version + +# remove extra folders +RUN rm -rf project/ + +# END IMAGE CUSTOMIZATIONS + +CMD ["/bin/sh"] diff --git a/.circleci/images/README.md b/.circleci/images/README.md new file mode 100644 index 00000000..a2172ba2 --- /dev/null +++ b/.circleci/images/README.md @@ -0,0 +1,18 @@ +General +------- +This DockerFile contains the necessary steps to build a Docker container that can run +projects with riscv-tools, chisel3, firrtl, and verilator. It installs the necessary +apt-get packages and sets the environment variables needed in CircleCI. + +Build and Deploy the Container +------------------------------ + + sudo docker build . # to test build before building it with a tag + sudo docker build -t :tag . # to build with tag (ex. 0.0.3) + sudo docker login # login into the account to push to + sudo docker push :tag # to push to repo with tag + +Path Names +---------- +Older docker images (when this Dockerfile was in `riscv-boom/riscv-boom`) can be found in the `riscvboom/riscvboom-images`. +Current up-to-date images are located in `ucbbar/chipyard-image` diff --git a/generators/boom b/generators/boom index 5323559b..a26504f3 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 5323559b3075d9cd86d2e87d7b00d1c16444c328 +Subproject commit a26504f34db8327a5d4d9bb3a342dddf79e02b35 From 958332e1bf1bfc2f931605f9f51a9b63df9044dc Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 12 Mar 2020 21:58:24 -0700 Subject: [PATCH 040/139] [firesim] Update ClockBridge API --- generators/firechip/src/main/scala/TargetConfigs.scala | 3 ++- generators/firechip/src/main/scala/TargetMixins.scala | 3 ++- tools/firrtl | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0d8f38dd..ffcb6811 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -22,6 +22,7 @@ import icenet._ import firesim.bridges._ import firesim.util.{WithNumNodes, FireSimClockKey, FireSimClockParameters} import firesim.configs._ +import midas.widgets.RationalClock class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -348,7 +349,7 @@ class FireSimTraceGenL2Config extends Config( class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(multiplier -> divisor)) + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) case RocketCrossingKey => up(RocketCrossingKey, site) map { r => r.copy(crossingType = RationalCrossing()) } diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 55761233..653a450f 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -16,6 +16,7 @@ import firesim.bridges.{TracerVBridge} import firesim.util.{HasAdditionalClocks, FireSimClockKey} import midas.targetutils.MemModelAnnotation +import midas.widgets.RationalClock import boom.common.BoomTile @@ -80,7 +81,7 @@ trait CanHaveMultiCycleRegfileImp { trait HasFireSimClockingImp extends HasAdditionalClocks { val outer: HasTiles val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { - case Some((numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) case None => (clocks(0), reset) } diff --git a/tools/firrtl b/tools/firrtl index f738fbe8..7eb1c7c0 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit f738fbe8667ed6b76ec00a15960b9c3a42b8654a +Subproject commit 7eb1c7c074713335f252bc8e7b48b9f3e057056c From 72dfbfabd4dc890065872042c45881db4663352d Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Thu, 12 Mar 2020 15:29:01 +0200 Subject: [PATCH 041/139] Allow user to override MAKE command used by toolchain and openocd build. On macOS, "gnumake" and "make" are both supplied by the OS, but are too old to build glibc (both are version 3.81 as of this writing). Homebrew provides the "gmake" executable, which is recent enough for glibc. However, the existing logic in "scripts/build-util.sh" will always prefer "gnumake" over "gmake". The configure logic in the riscv-glibc library allows a user to override the preference for "gnumake" by setting the MAKE environment variable. This change makes "scripts/build-openocd.sh" and "scripts/build-toolchains.sh" mimic that behavior. A user can now use "gmake" instead of "gnumake" during the toolchain build like so: MAKE=gmake ./scripts/build-toolchains.sh --- scripts/build-util.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/build-util.sh b/scripts/build-util.sh index be58a6a1..10a7cb7b 100644 --- a/scripts/build-util.sh +++ b/scripts/build-util.sh @@ -14,7 +14,8 @@ case ${ncpu} in *) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;; esac -MAKE=$(command -v gnumake || command -v gmake || command -v make) +# Allow user to override MAKE +[ -n "${MAKE}" ] || MAKE=$(command -v gnumake || command -v gmake || command -v make) readonly MAKE From d540899b48e473f490d4d5fad98993838f9e1ff8 Mon Sep 17 00:00:00 2001 From: Tynan McAuley <16469394+tymcauley@users.noreply.github.com> Date: Fri, 13 Mar 2020 23:51:09 +0200 Subject: [PATCH 042/139] Fix name of Ubuntu/Debian package "libexpat1-dev". (#466) The "libxpat1-dev" package doesn't exist on Ubuntu/Debian, and results in an error when installing Ubuntu/Debian dependencies. The desired package: https://packages.ubuntu.com/bionic/libexpat1-dev Co-authored-by: Tynan McAuley --- scripts/ubuntu-req.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index da626052..ee541e81 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -10,7 +10,7 @@ curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89 sudo apt-get update sudo apt-get install -y sbt sudo apt-get install -y texinfo gengetopt -sudo apt-get install -y libxpat1-dev libusb-dev libncurses5-dev cmake +sudo apt-get install -y libexpat1-dev libusb-dev libncurses5-dev cmake # deps for poky sudo apt-get install -y python3.6 patch diffstat texi2html texinfo subversion chrpath git wget # deps for qemu From 179dd5973433126690dcea124126800fce3bc391 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Mar 2020 18:34:36 -0700 Subject: [PATCH 043/139] bump gemmini to v0.2 (#469) * bump gemmini to v0.2 * bump gemmini * bump gemmini v0.2 --- generators/gemmini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/gemmini b/generators/gemmini index 6602434b..d6f36d37 160000 --- a/generators/gemmini +++ b/generators/gemmini @@ -1 +1 @@ -Subproject commit 6602434b34fb33d005af50cd5e7bf8534f82ebf7 +Subproject commit d6f36d37d1e10b7fd514e6680b1eaea032cee628 From d5592ca1a7829cbbe24a0db7a58844c4125abf63 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Mar 2020 18:44:47 -0700 Subject: [PATCH 044/139] bump firesim (#470) * Fix capitalization in docs (#419) * Update Quick-Start.rst * [ci skip] Fix Typos (#444) * Update Quick-Start.rst * bump firesim Co-authored-by: Sagar Karandikar --- docs/Customization/RoCC-Accelerators.rst | 2 +- docs/index.rst | 4 ++-- sims/firesim | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/Customization/RoCC-Accelerators.rst b/docs/Customization/RoCC-Accelerators.rst index 7a3f4447..2d420177 100644 --- a/docs/Customization/RoCC-Accelerators.rst +++ b/docs/Customization/RoCC-Accelerators.rst @@ -45,7 +45,7 @@ The other interfaces available to the accelerator are ``mem``, which provides ac the ``busy`` signal, which indicates when the accelerator is still handling an instruction; and the ``interrupt`` signal, which can be used to interrupt the CPU. -Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRocc.scala`` for detailed information on the different IOs. +Look at the examples in ``generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala`` for detailed information on the different IOs. Adding RoCC accelerator to Config ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/index.rst b/docs/index.rst index a98c3088..debfaf99 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -8,8 +8,8 @@ Welcome to Chipyard's documentation! .. image:: ./_static/images/chipyard-logo.svg -Chipyard is a a framework for designing and evaluating full-system hardware using agile teams. -It is composed of a collection of tools and libraries designed to provide an intergration between open-source and commercial tools for the development of systems-on-chip. +Chipyard is a framework for designing and evaluating full-system hardware using agile teams. +It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. Quick Start diff --git a/sims/firesim b/sims/firesim index 9f970576..e64e51df 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9f9705762a7e19b1e9ff77a92f7f4413ffe83265 +Subproject commit e64e51dfca00e5ad53089847a1781a73acfe8b9b From a99a1c8025c0cf5af03df9bad1ec4469878b1877 Mon Sep 17 00:00:00 2001 From: alonamid Date: Fri, 13 Mar 2020 19:14:36 -0700 Subject: [PATCH 045/139] Resolve conflict (#471) * Fix capitalization in docs (#419) * Update Quick-Start.rst * [ci skip] Fix Typos (#444) * Update Quick-Start.rst Co-authored-by: Sagar Karandikar From dc7e8f748dfc7c02825630989a1330b877db84a8 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Sat, 14 Mar 2020 11:36:53 -0700 Subject: [PATCH 046/139] Barstools and chip docs (#446) * WIP; Add some information on building a chip [skip ci] * [docs] [ci skip] re-org chip/barstools docs Also add macrocompiler flag descriptions * [docs] Add MDF description [ci-skip] * [docs] Address some of Abe and Harrison's feedback [ci skip] * [docs] Update hierarchy/transform section [ci skip] * [docs] Address all feedback except cost function [ci skip] * [docs] Describe macro compiler cost function [ci skip] Co-authored-by: John Wright --- docs/Tools/Barstools.rst | 130 ++++++++++++++++++++++++++++++++++ docs/VLSI/Building-A-Chip.rst | 52 +++++++++++++- 2 files changed, 180 insertions(+), 2 deletions(-) diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 81435130..34562227 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -3,3 +3,133 @@ Barstools Barstools is a collection of useful FIRRTL transformations and compilers to help the build process. Included in the tools are a MacroCompiler (used to map Chisel memory constructs to vendor SRAMs), FIRRTL transforms (to separate harness and top-level SoC files), and more. + +Mapping technology SRAMs (MacroCompiler) +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +If you are planning on building a real chip, it is likely that you will plan on using some amount of static random access memory, or SRAM. +SRAM macros offer superior storage density over flip-flop arrays at the cost of restricting the number of read or write transactions that can happen in a cycle. +Unlike in Verilog, these types of sequential memory elements are first-class primitives in Chisel and FIRRTL (``SeqMem`` elements). +This allows Chisel designs to contain abstract instantiations of sequential memory elements without knowing the underlying implementation or process technology. + +Modern CAD tools typically cannot synthesize SRAMs from a high-level RTL description. +This, unfortunately, requires the designer to include the SRAM instantiation in the source RTL, which removes its process portability. +In Verilog-entry designs, it is possible to create a layer of abstraction that allows a new process technology to implement a specific sequential memory block in a wrapper module. +However, this method can be fragile and laborious. + +The FIRRTL compiler contains a transformation to replace the ``SeqMem`` primitives called ``ReplSeqMem``. +This simply converts all ``SeqMem`` instances above a size threshold into external module references. +An external module reference is a FIRRTL construct that enables a design to reference a module without describing its contents, only its inputs and outputs. +A list of unique SRAM configurations is output to a ``.conf`` file by FIRRTL, which is used to map technology SRAMs. +Without this transform, FIRRTL will map all ``SeqMem`` s to flip-flop arrays with equivalent behavior, which may lead to a design that is difficult to route. + +The ``.conf`` file is consumed by a tool called MacroCompiler, which is part of the :ref:`Barstools` scala package. +MacroCompiler is also passed an ``.mdf`` file that describes the available list of technology SRAMs or the capabilities of the SRAM compiler, if one is provided by the foundry. +Typically a foundry SRAM compiler will be able to generate a set of different SRAMs collateral based on some requirements on size, aspect ratio, etc. (see :ref:`SRAM MDF Fields`). +Using a user-customizable cost function, MacroCompiler will select the SRAMs that are the best fit for each dimensionality in the ``.conf`` file. +This may include over provisioning (e.g. using a 64x1024 SRAM for a requested 60x1024, if the latter is not available) or arraying. +Arraying can be done in both width and depth, as well as to solve masking constraints. +For example, a 128x2048 array could be composed of four 64x1024 arrays, with two macros in parallel to create two 128x1024 virtual SRAMs which are combinationally muxed to add depth. +If this macro requires byte-granularity write masking, but no technology SRAMs support masking, then the tool may choose to use thirty-two 8x1024 arrays in a similar configuration. +For information on writing ``.mdf`` files, look at `MDF on github `__ and a brief description in :ref:`SRAM MDF Fields` section. + +The output of MacroCompiler is a Verilog file containing modules that wrap the technology SRAMs into the specified interface names from the ``.conf``. +If the technology supports an SRAM compiler, then MacroCompiler will also emit HammerIR that can be passed to Hammer to run the compiler itself and generate design collateral. +Documentation for SRAM compilers is forthcoming. + +MacroCompiler Options ++++++++++++++++++++++ +MacroCompiler accepts many command-line parameters which affect how it maps ``SeqMem`` s to technology specific macros. +This highest level option ``--mode`` specifies in general how MacroCompiler should map the input ``SeqMem`` s to technology macros. +The ``strict`` value forces MacroCompiler to map all memories to technology macros and error if it is unable to do so. +The ``synflops`` value forces MacroCompiler to map all memories to flip flops. +The ``compileandsynflops`` value instructs MacroCompiler to use the technology compiler to determine sizes of technology macros used but to then create mock versions of these macros with flip flops. +The ``fallbacksynflops`` value causes MacroCompiler to compile all possible memories to technology macros but when unable to do so to use flip flops to implement the remaining memories. +The final and default value, ``compileavailable``, instructs MacroCompiler to compile all memories to the technology macros and do nothing if it is unable to map them. + +Most of the rest of the options are used to control where different inputs and outputs are expected and produced. +The option ``--macro-conf`` is the file that contains the set of input ``SeqMem`` configurations to map in the ``.conf`` format described above. +The option ``--macro-mdf`` also describes the input ``SeqMem`` s but is instead in the ``.mdf`` format. +The option ``--library`` is an ``.mdf`` description of the available technology macros that can be mapped to. +This file could be a list of fixed size memories often referred to as a cache of macros, or a description of what size memories could be made available through some technology specific process (usually an SRAM compiler), or a mix of both. +The option ``--use-compiler`` instructs MacroCompiler that it is allowed to use any compilers listed in the ``--library`` specification. +If this option is not set MacroCompiler will only map to macros directly listed in the ``--library`` specification. +The ``--verilog`` option specifies where MacroCompiler will write the verilog containing the new technology mapped memories. +The ``--firrtl`` option similarly specifies where MacroCompiler will write the FIRRTL that will be used to generate this verilog. +This option is optional and no FIRRTL will be emitted if it is not specified. +The ``--hammer-ir`` option specifies where MacroCompiler will write the details of which macros need to be generated from a technology compiler. +This option is not needed if ``--use-compiler`` is not specified. +This file can then be passed to HAMMER to have it run the technology compiler producing the associated macro collateral. +The ``--cost-func`` option allows the user to specify a different cost function for the mapping task. +Because the mapping of memories is a multi-dimensional space spanning performance, power, and area, the cost function setting of MacroCompiler allows the user to tune the mapping to their preference. +The default option is a reasonable heuristic that attempts to minimize the number of technology macros instantiated per ``SeqMem`` without wasting too many memory bits. +There are two ways to add additional cost functions. +First, you can simply write another one in scala and call `registerCostMetric` which then enables you to pass its name to this command-line flag. +Second, there is a pre-defined `ExternalMetric` which will execute a program (passed in as a path) with the MDF description of the memory being compiled and the memory being proposed as a mapping. +The program should print a floating point number which is the cost for this mapping, if no number is printed MacroCompiler will assume this is an illegal mapping. +The ``--cost-param`` option allows the user to specify parameters to pass to the cost function if the cost function supports that. +The ``--force-synflops [mem]`` options allows the user to override any heuristics in MacroCompiler and force it to map the given memory to flip-flops. +Likewise, the ``--force-compile [mem]`` option allows the user to force MacroCompiler to map the given ``mem`` to a technology macro. + +SRAM MDF Fields ++++++++++++++++ + +Technology SRAM macros described in MDF can be defined at three levels of detail. +A single instance can be defined with the `SRAMMacro` format. +A group of instances that share the number and type of ports but vary in width and depth can be defined with the `SRAMGroup` format. +A set of groups of SRAMs that can be generated together from a single source like a compiler can be defined with the `SRAMCompiler` format. + +At the most concrete level the `SRAMMAcro` defines a particular instance of an SRAM. +That includes its functional attributes such as its width, depth, and number of access ports. +These ports can be read, write, or read and write ports, and the instance can have any number. +In order to correctly map to these functional ports to the physical instance each port is described in a list of sub-structures, in the parent instance's structure. +Each port is only required to have an address and data field, but can have many other optional fields. +These optional fields include a clock, write enable, read enable, chip enable, mask. +The mask field can have a different granularity than the data field, e.g. it could be a bit mask or a byte mask. +Each field must also specify its polarity, whether it is active high or active low. + +In addition to these functional descriptions of the SRAM there are also other fields that specify physical/implementation characteristics. +These include the threshold voltage, the mux factor, as well as a list of extra non-functional ports. + +The next level of detail, an `SRAMGroup` includes a range of depths and widths, as well as a set of threshold voltages. +A range has a lower bound, upper bound, and a step size. +The least concrete level, an `SRAMCompiler` is simply a set of `SRAMGroups`. + +Separating the Top module from the TestHarness module +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Unlike the FireSim and Software simulation flows, a VLSI flow needs to separate the test harness and the chip (a.k.a. DUT) into separate files. +This is necessary to facilitate post-synthesis and post-place-and-route simulation, as the module names in the RTL and gate-level verilog files would collide. +Simulations after you the design goes through a VLSI flow will use the verilog netlist generated from the flow and will need an untouched test harness to drive it. +Separating these components into separate files makes this straightforward. +Without the separation the file that included the test harness would also redefine the DUT which is often disallowed in simulation tools. +To do this, there is a FIRRTL ``App`` in :ref:`Barstools` called ``GenerateTopAndHarness``, which runs the appropriate transforms to elaborate the modules separately. +This also renames modules in the test harness so that any modules that are instantiated in both the test harness and the chip are uniquified. + +.. Note:: For VLSI projects, this ``App`` is run instead of the normal FIRRTL ``App`` to elaborate Verilog. + +Macro Description Format +~~~~~~~~~~~~~~~~~~~~~~~~ + +The SRAM technology macros and IO cells are described in a json format called Macro Description Format (MDF). +MDF is specialized for each type of macro it supports. +The specialization is defined in their respective sections. + + + +Mapping technology IO cells +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Like technology SRAMs, IO cells are almost always included in digital ASIC designs to allow pin configurability, increase the voltage level of the IO signal, and provide ESD protection. +Unlike SRAMs, there is no corresponding primitive in Chisel or FIRRTL. +However, this problem can be solved similarly to ``SeqMems`` by leveraging the strong typing available in these scala-based tools. +We are actively developing a FIRRTL transform that will automatically configure, map, and connect technology IO cells. +Stay tuned for more information! + +In the meantime, it is recommended that you instantiate the IO cells in your Chisel design. +This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recommended that inclusion of these cells be configurable using the ``rocket-chip`` parameterization system. +The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness. +When simulating chip-specific designs, it is important to include the IO cells. +The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check. +They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the top module from the test harness`) consistent after synthesis and place-and-route, +which allows the RTL simulation test harness to be reused. diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index 6f7cd4b1..b684a07b 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -1,6 +1,54 @@ .. _build-a-chip: Building A Chip -============================== +=============== + +In this section, we will discuss many of the ASIC-specific transforms and methodologies within Chipyard. +For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. + +Transforming the RTL +-------------------- + +Building a chip requires specializing the generic verilog emitted by FIRRTL to adhere to the constraints imposed by the technology used for fabrication. +This includes mapping Chisel memories to available technology macros such as SRAMs, mapping the input and output of your chip to connect to technology IO cells, see :ref:`Barstools`. +In addition to these required transformations, it may also be beneficial to transform the RTL to make it more amenable to hierarchical physical design easier. +This often includes modifying the logical hierarchy to match the physical hierarchy through grouping components together or flattening components into a single larger module. + + +Modifying the logical hierarchy +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Building a large or complex chip often requires using hierarchical design to place and route sections of the chip separately. +In addition, the design as written in Chipyard may not have a hierarchy that matches the physical hierarchy that would work best in the place and route tool. +In order to reorganize the design to have its logical hierarchy match its physical hierarchy there are several FIRRTL transformations that can be run. +These include grouping, which pull several modules into a larger one, and flattening, which dissolves a modules boundary leaving its components in its containing module. +These transformations can be applied repeatedly to different parts of the design to arrange it as the physical designer sees fit. +More details on how to use these transformations to reorganize the design hierarchy are forthcoming. + + +Creating a floorplan +-------------------- + +An ASIC floorplan is a specification that the place-and-route tools will follow when placing instances in the design. +This includes the top-level chip dimensions, placement of SRAM macros, placement of custom (analog) circuits, IO cell placement, bump or wirebond pad placement, blockages, hierarchical boundaries, and pin placement. + +Much of the design effort that goes into building a chip involves developing optimal floorplans for the instance of the design that is being manufactured. +Often this is a highly manual and iterative process which consumes much of the physical designer's time. +This cost becomes increasingly apparent as the parameterization space grows rapidly when using tools like Chisel- cycle times are hampered by the human labor +that is required to floorplan each instance of the design. +The Hammer team is actively developing methods of improving the agility of floorplanning for generator-based designs, like those that use Chisel. +The libraries we are developing will emit Hammer IR that can be passed directly to the Hammer tool without the need for human intervention. +Stay tuned for more information. + +In the meantime, see the `Hammer Documentation `__ for information on the Hammer IR floorplan API. +It is possible to write this IR directly, or to generate it using simple python scripts. +While we certainly look forward to having a more featureful toolkit, we have built many chips to date in this way. + + +Running the VLSI flow +--------------------- + +For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. +For an example of how to use the VLSI in the context of Chipyard, see :ref:`ASAP7 Tutorial`. + -.. Note:: Please refer to the other sections in VLSI for tools/flows on how to build a chip. This section will be filled in ASAP. From c798592f448fd545b5424e84cfe75d76a9c2a430 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 14 Mar 2020 12:08:08 -0700 Subject: [PATCH 047/139] Update CHANGELOG.md (#475) * Update CHANGELOG.md * [skip CI] Update CHANGELOG.md Co-Authored-By: Sagar Karandikar * Update CHANGELOG.md Co-authored-by: Sagar Karandikar --- CHANGELOG.md | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 31fb2250..22783946 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,6 +2,43 @@ This changelog follows the format defined here: https://keepachangelog.com/en/1.0.0/ +## [1.2.0] - 2020-03-14 + +A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/418 + +### Added +* Ring Topology System Bus NoC (#461) +* Integration of the Ariane core into Chipyard (#448) +* FireMarshal now generates an extra copy of linux kernel with dwarf debugging info for use in FirePerf (#427) +* Add option to use blackboxed SimDRAM instead of SimAXIMem (#449) +* Log `init-submodules` script (#433) +* Moved the Docker image used for CI into Chipyard (prev. in BOOM) (#463) + +### Changed +* Bump FireSim to 1.9.0 - Includes FirePerf TracerV Flame Graph features +* IOBinders and BuildTop unification between FireChip and Chipyard (#390) +* Bump BOOM to version 2.2.4 (#463) +* Bump Gemmini to version 0.2 (#469) +* Update to CircleCI 2.1 config. syntax and cleanup CI file (#421) +* FireMarshal moved from FireSim to Chipyard (#415) +* Rename config. mixins to config fragments (#451) + +### Fixed +* `git status` should be clean. (Although you will need to manually cleanup the libgloss and qemu directories after first setup). (#411, #414) +* Fix Hetero. BOOM + Rocket + Hwacha config (#413) +* Fix VCS stdout (#417) +* Add a git version check to the init scripts and make them work outside of the repo root (#459) +* Fix generation of env.sh for zsh (#435) +* GCD example bug (#465) + +### Deprecated + + +### Removed + + + + ## [1.1.0] - 2020-01-25 A more detailed account of everything included is included in the dev to master PR for this release: https://github.com/ucb-bar/chipyard/pull/367 From 0d902f5e92534c15d6479554062fbe36d3c2acab Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 14 Mar 2020 12:41:14 -0700 Subject: [PATCH 048/139] bump to firesim dev that will become master --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index e64e51df..5cef02ad 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e64e51dfca00e5ad53089847a1781a73acfe8b9b +Subproject commit 5cef02ad96365d6663756c143b174afad435828c From 3a5090b65cfe3d5bdd468b3fde46a5dfbe001b81 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Sat, 14 Mar 2020 19:59:33 +0000 Subject: [PATCH 049/139] bump icenet testchipip to master --- generators/icenet | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/icenet b/generators/icenet index e235801c..f2272284 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit e235801c4c7088a303dd2136e02fb9548b4ec2f8 +Subproject commit f22722847444ecfcd5369f1b33547727d051b834 diff --git a/generators/testchipip b/generators/testchipip index 535eb6c5..3a83cd0a 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 535eb6c58374b96c60e4e8217c709d60a66dab4a +Subproject commit 3a83cd0a4036bec8ea9a2bebd582539723601e73 From ece9163b023a12f834306b82cbc83255b4f710ec Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 14 Mar 2020 13:03:48 -0700 Subject: [PATCH 050/139] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 5cef02ad..3f5467ac 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 5cef02ad96365d6663756c143b174afad435828c +Subproject commit 3f5467ace1c204d45cc2cdd26773260ce09c9a8a From b63adae5d9285df79a9514e4df45e11740408449 Mon Sep 17 00:00:00 2001 From: Sagar Karandikar Date: Sat, 14 Mar 2020 13:26:47 -0700 Subject: [PATCH 051/139] update changelog (#479) --- CHANGELOG.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 22783946..f9447b0e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -32,10 +32,10 @@ A more detailed account of everything included is included in the dev to master * GCD example bug (#465) ### Deprecated - +* N/A ### Removed - +* N/A From a3e12b96b0278c4bf6317f1f125849854126f392 Mon Sep 17 00:00:00 2001 From: Alon Amid Date: Sun, 15 Mar 2020 01:04:51 +0000 Subject: [PATCH 052/139] [skip ci] bump firesim 1.9.0 --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3f5467ac..ce0d05a1 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3f5467ace1c204d45cc2cdd26773260ce09c9a8a +Subproject commit ce0d05a10a47e58e17e1b081115429dc6328768d From ffb9c81ce246c051a880dd986e4254747acbb4cb Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 16 Mar 2020 12:06:59 -0700 Subject: [PATCH 053/139] fix literalincludes and other path references in documentation --- docs/Advanced-Concepts/Chip-Communication.rst | 4 ++-- docs/Customization/DMA-Devices.rst | 6 ++--- docs/Customization/Heterogeneous-SoCs.rst | 6 ++--- .../Incorporating-Verilog-Blocks.rst | 9 +++---- docs/Customization/Keys-Traits-Configs.rst | 10 ++++---- docs/Customization/MMIO-Peripherals.rst | 24 +++++++++---------- docs/Customization/Memory-Hierarchy.rst | 2 +- docs/Generators/Gemmini.rst | 2 +- docs/Generators/SHA3.rst | 2 +- docs/Generators/SiFive-Generators.rst | 6 ++--- .../NodeTypes.rst | 12 +++++----- .../Register-Router.rst | 12 +++++----- 12 files changed, 48 insertions(+), 47 deletions(-) diff --git a/docs/Advanced-Concepts/Chip-Communication.rst b/docs/Advanced-Concepts/Chip-Communication.rst index eff08670..e36805ec 100644 --- a/docs/Advanced-Concepts/Chip-Communication.rst +++ b/docs/Advanced-Concepts/Chip-Communication.rst @@ -111,7 +111,7 @@ FireSim FPGA-accelerated simulations use TSI by default as well. If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must tie-off the TSI interface, and instantiate the `SimDTM`. Note that we use `WithTiedOffSerial ++ WithSimDebug` instead of `WithTiedOffDebug ++ WithSimSerial`. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: DmiRocket :end-before: DOC include end: DmiRocket @@ -141,7 +141,7 @@ The configuration is very similar to a DMI-based configuration. The main differe is the addition of the ``WithJtagDTM`` config fragment that configures the instantiated DTM to use the JTAG protocol as the bringup method. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: JtagRocket :end-before: DOC include end: JtagRocket diff --git a/docs/Customization/DMA-Devices.rst b/docs/Customization/DMA-Devices.rst index ed5678c9..554ff2d4 100644 --- a/docs/Customization/DMA-Devices.rst +++ b/docs/Customization/DMA-Devices.rst @@ -12,7 +12,7 @@ having the CPU poll data from the device, we may want to have the device write directly to the coherent memory system instead. For example, here is a device that writes zeros to the memory at a configured address. -.. literalinclude:: ../../generators/chipyard/src/main/scala/InitZero.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala :language: scala .. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala @@ -26,12 +26,12 @@ For more info on creating TileLink client nodes, take a look at :ref:`Client Nod Once we've created our top-level module including the DMA widget, we can create a configuration for it as we did before. -.. literalinclude:: ../../generators/chipyard/src/main/scala/InitZero.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala :language: scala :start-after: DOC include start: WithInitZero :end-before: DOC include end: WithInitZero -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: InitZeroRocketConfig :end-before: DOC include end: InitZeroRocketConfig diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 6385f3b3..765a1afe 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -13,7 +13,7 @@ When used together you can create a heterogeneous system. The following example shows a dual core BOOM with a single core Rocket. -.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala :language: scala :start-after: DOC include start: DualBoomAndRocket :end-before: DOC include end: DualBoomAndRocket @@ -72,7 +72,7 @@ Adding Hwachas Adding a Hwacha accelerator is as easy as adding the ``DefaultHwachaConfig`` so that it can setup the Hwacha parameters and add itself to the ``BuildRoCC`` parameter. An example of adding a Hwacha to all tiles in the system is below. -.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala :language: scala :start-after: DOC include start: BoomAndRocketWithHwacha :end-before: DOC include end: BoomAndRocketWithHwacha @@ -88,7 +88,7 @@ Named ``MultiRoCCKey``, this key allows you to attach RoCC accelerators based on For example, using this allows you to create a 8 tile system with a RoCC accelerator on only a subset of the tiles. An example is shown below with two BOOM cores, and one Rocket tile with a RoCC accelerator (Hwacha) attached. -.. literalinclude:: ../../generators/chipyard/src/main/scala/HeteroConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/HeteroConfigs.scala :language: scala :start-after: DOC include start: DualBoomAndRocketOneHwacha :end-before: DOC include end: DualBoomAndRocketOneHwacha diff --git a/docs/Customization/Incorporating-Verilog-Blocks.rst b/docs/Customization/Incorporating-Verilog-Blocks.rst index bca9d067..57a0bab1 100644 --- a/docs/Customization/Incorporating-Verilog-Blocks.rst +++ b/docs/Customization/Incorporating-Verilog-Blocks.rst @@ -57,7 +57,8 @@ and Verilog sources follow the prescribed directory layout. build.sbt src/main/ scala/ - GCD.scala + example/ + GCD.scala resources/ vsrc/ GCDMMIOBlackBox.v @@ -88,7 +89,7 @@ as the bitwidth of the GCD calculation does in this example. **Chisel BlackBox Definition** -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD blackbox :end-before: DOC include end: GCD blackbox @@ -103,7 +104,7 @@ peripheral-specific traits into a ``TLRegisterRouter``. The ``params`` member and ``HasRegMap`` base trait should look familiar from the previous memory-mapped GCD device example. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD instance regmap :end-before: DOC include end: GCD instance regmap @@ -115,7 +116,7 @@ Defining a Chip with a BlackBox Since we've parameterized the GCD instantiation to choose between the Chisel and the Verilog module, creating a config is easy. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDAXI4BlackBoxRocketConfig :end-before: DOC include end: GCDAXI4BlackBoxRocketConfig diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index 0dd20a65..ffa303b7 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -16,7 +16,7 @@ Keys specify some parameter which controls some custom widget. Keys should typic Keys should be defined and documented in sub-projects, since they generally deal with some specific block, and not system-level integration. (We make an exception for the example GCD widget). -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD key :end-before: DOC include end: GCD key @@ -24,7 +24,7 @@ Keys should be defined and documented in sub-projects, since they generally deal The object within a key is typically a ``case class XXXParams``, which defines a set of parameters which some block accepts. For example, the GCD widget's ``GCDParams`` parameterizes its address, operand widths, whether the widget should be connected by Tilelink or AXI4, and whether the widget should use the blackbox-Verilog implementation, or the Chisel implementation. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD params :end-before: DOC include end: GCD params @@ -42,7 +42,7 @@ Top-level traits should be defined and documented in subprojects, alongside thei Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD imp trait @@ -61,14 +61,14 @@ Config fragments set the keys to a non-default value. Together, the collection o For example, the ``WithGCD`` config fragment is parameterized by the type of GCD widget you want to instantiate. When this config fragment is added to a config, the ``GCDKey`` is set to a instance of ``GCDParams``, informing the previously mentioned traits to instantiate and connect the GCD widget appropriately. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD config fragment :end-before: DOC include end: GCD config fragment We can use this config fragment when composing our configs. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDTLRocketConfig :end-before: DOC include end: GCDTLRocketConfig diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index 4801d4d4..f6b429be 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -3,21 +3,21 @@ MMIO Peripherals ================== -The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. +The easiest way to create a MMIO peripheral is to use the ``TLRegisterRouter`` or ``AXI4RegisterRouter`` widgets, which abstracts away the details of handling the interconnect protocols and provides a convenient interface for specifying memory-mapped registers. Since Chipyard and Rocket Chip SoCs primarily use Tilelink as the on-chip interconnect protocol, this section will primarily focus on designing Tilelink-based peripherals. However, see ``generators/chipyard/src/main/scala/example/GCD.scala`` for how an example AXI4 based peripheral is defined and connected to the Tilelink graph through converters. To create a RegisterRouter-based peripheral, you will need to specify a parameter case class for the configuration settings, a bundle trait with the extra top-level ports, and a module implementation containing the actual RTL. For this example, we will show how to connect a MMIO peripheral which computes the GCD. -The full code can be found in ``generators/chipyard/src/main/scala/GCD.scala``. +The full code can be found in ``generators/chipyard/src/main/scala/example/GCD.scala``. In this case we use a submodule ``GCDMMIOChiselModule`` to actually perform the GCD. The ``GCDModule`` class only creates the registers and hooks them up using ``regmap``. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD chisel :end-before: DOC include end: GCD chisel -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD instance regmap :end-before: DOC include end: GCD instance regmap @@ -51,7 +51,7 @@ The second set of arguments is the IO bundle constructor, which we create by ext The final set of arguments is the module constructor, which we create by extends ``TLRegModule`` with our module trait. Notice how we can create an analogous AXI4 version of our peripheral. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD router :end-before: DOC include end: GCD router @@ -69,7 +69,7 @@ In the Rocket Chip cake, there are two kinds of traits: a ``LazyModule`` trait a The ``LazyModule`` trait runs setup code that must execute before all the hardware gets elaborated. For a simple memory-mapped peripheral, this just involves connecting the peripheral's TileLink node to the MMIO crossbar. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD lazy trait @@ -82,7 +82,7 @@ Also observe how we have to place additional AXI4 buffers and converters for the For peripherals which instantiate a concrete module, or which need to be connected to concrete IOs or wires, a matching concrete trait is necessary. We will make our GCD example output a ``gcd_busy`` signal as a top-level port to demonstrate. In the concrete module implementation trait, we instantiate the top level IO (a concrete object) and wire it to the IO of our lazy module. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD imp trait :end-before: DOC include end: GCD imp trait @@ -105,14 +105,14 @@ The ``TopModule`` class is the actual RTL that gets synthesized. -And finally, we create a configuration class in ``generators/chipyard/src/main/scala/Configs.scala`` that uses the ``WithGCD`` config fragment defined earlier. +And finally, we create a configuration class in ``generators/chipyard/src/main/scala/config/RocketConfigs.scala`` that uses the ``WithGCD`` config fragment defined earlier. -.. literalinclude:: ../../generators/chipyard/src/main/scala/GCD.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala - :start-after: DOC include start: GCD fragment - :end-before: DOC include end: GCD fragment + :start-after: DOC include start: GCD config fragment + :end-before: DOC include end: GCD config fragment -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: GCDTLRocketConfig :end-before: DOC include end: GCDTLRocketConfig diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 436a0ea9..6c924ceb 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -29,7 +29,7 @@ you can only use a single core and you cannot give the design an external DRAM. Note that these configurations fully remove the L2 cache and mbus. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: scratchpadrocket :end-before: DOC include end: scratchpadrocket diff --git a/docs/Generators/Gemmini.rst b/docs/Generators/Gemmini.rst index 80767ce0..b2257b1f 100644 --- a/docs/Generators/Gemmini.rst +++ b/docs/Generators/Gemmini.rst @@ -9,7 +9,7 @@ To add a Gemmini unit to an SoC, you should add the ``gemmini.DefaultGemminiConf The example Chipyard config includes the following example SoC configuration which includes Gemmini: -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: GemminiRocketConfig :end-before: DOC include end: GemminiRocketConfig diff --git a/docs/Generators/SHA3.rst b/docs/Generators/SHA3.rst index 92173995..9340caae 100644 --- a/docs/Generators/SHA3.rst +++ b/docs/Generators/SHA3.rst @@ -72,7 +72,7 @@ it can be mixed into a Rocket or BOOM core by overriding the generator. An example configuration highlighting the use of this config fragment is shown here: -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: Sha3Rocket :end-before: DOC include end: Sha3Rocket diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/SiFive-Generators.rst index 68c239c7..7ac0105f 100644 --- a/docs/Generators/SiFive-Generators.rst +++ b/docs/Generators/SiFive-Generators.rst @@ -20,8 +20,8 @@ To integrate one of these devices in your SoC, you will need to define a custom .. literalinclude:: ../../generators/chipyard/src/main/scala/ConfigFragments.scala :language: scala - :start-after: DOC include start: gpio mixin - :end-before: DOC include end: gpio mixin + :start-after: DOC include start: gpio config fragment + :end-before: DOC include end: gpio config fragment Additionally, if the device requires top-level IOs, you will need to define a config fragment to change the top-level configuration of your SoC. When adding a top-level IO, you should also be aware of whether it interacts with the test-harness. @@ -31,7 +31,7 @@ This example instantiates a top-level module with include GPIO ports, and then t Finally, you add the relevant config fragment to the SoC config. For example: -.. literalinclude:: ../../generators/chipyard/src/main/scala/RocketConfigs.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala :language: scala :start-after: DOC include start: GPIORocketConfig :end-before: DOC include end: GPIORocketConfig diff --git a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst index ff80f937..ddb53c9f 100644 --- a/docs/TileLink-Diplomacy-Reference/NodeTypes.rst +++ b/docs/TileLink-Diplomacy-Reference/NodeTypes.rst @@ -17,7 +17,7 @@ The L1 caches and DMA devices in RocketChip/Chipyard have client nodes. You can add a TileLink client node to your LazyModule using the TLHelper object from testchipip like so: -.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala :language: scala :start-after: DOC include start: MyClient :end-before: DOC include end: MyClient @@ -66,7 +66,7 @@ TileLink managers take requests from clients on the A channel and send responses back on the D channel. You can create a manager node using the TLHelper like so: -.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala :language: scala :start-after: DOC include start: MyManager :end-before: DOC include end: MyManager @@ -146,7 +146,7 @@ to the outputs unchanged. This node is mainly used to combine multiple nodes into a single node with multiple edges. For instance, say we have two client lazy modules, each with their own client node. -.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala :language: scala :start-after: DOC include start: MyClient1+MyClient2 :end-before: DOC include end: MyClient1+MyClient2 @@ -154,21 +154,21 @@ client lazy modules, each with their own client node. Now we instantiate these two clients in another lazy module and expose their nodes as a single node. -.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala :language: scala :start-after: DOC include start: MyClientGroup :end-before: DOC include end: MyClientGroup We can also do the same for managers. -.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala :language: scala :start-after: DOC include start: MyManagerGroup :end-before: DOC include end: MyManagerGroup If we want to connect the client and manager groups together, we can now do this. -.. literalinclude:: ../../generators/chipyard/src/main/scala/NodeTypes.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala :language: scala :start-after: DOC include start: MyClientManagerComplex :end-before: DOC include end: MyClientManagerComplex diff --git a/docs/TileLink-Diplomacy-Reference/Register-Router.rst b/docs/TileLink-Diplomacy-Reference/Register-Router.rst index 7e28196f..6f5e1aa0 100644 --- a/docs/TileLink-Diplomacy-Reference/Register-Router.rst +++ b/docs/TileLink-Diplomacy-Reference/Register-Router.rst @@ -18,7 +18,7 @@ This section will focus on the second method. Basic Usage ----------- -.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyDeviceController :end-before: DOC include end: MyDeviceController @@ -56,7 +56,7 @@ register. The ``RegField`` interface also provides support for reading and writing ``DecoupledIO`` interfaces. For instance, you can implement a hardware FIFO like so. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyQueueRegisters :end-before: DOC include end: MyQueueRegisters @@ -71,7 +71,7 @@ You need not specify both read and write for a register. You can also create read-only or write-only registers. So for the previous example, if you wanted enqueue and dequeue to use different addresses, you could write the following. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MySeparateQueueRegisters :end-before: DOC include end: MySeparateQueueRegisters @@ -93,7 +93,7 @@ You can also create registers using functions. Say, for instance, that you want to create a counter that gets incremented on a write and decremented on a read. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyCounterRegisters :end-before: DOC include end: MyCounterRegisters @@ -107,7 +107,7 @@ You can also pass functions that decouple the read/write request and response. The request will appear as a decoupled input and the response as a decoupled output. So for instance, if we wanted to do this for the previous example. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyCounterReqRespRegisters :end-before: DOC include end: MyCounterReqRespRegisters @@ -131,7 +131,7 @@ change the protocol being used. For instance, in the first example in :ref:`Basic Usage`, you could simply change the ``TLRegisterNode`` to and ``AXI4RegisterNode``. -.. literalinclude:: ../../generators/chipyard/src/main/scala/RegisterNodeExample.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/example/RegisterNodeExample.scala :language: scala :start-after: DOC include start: MyAXI4DeviceController :end-before: DOC include end: MyAXI4DeviceController From e94dc287b1ec6e30eee5a446fd7acd1fcb4f1120 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Tue, 17 Mar 2020 10:48:18 -0700 Subject: [PATCH 054/139] [docs/ci] cleanup docs and add ci to check it (#485) --- .circleci/config.yml | 14 ++++++++++++++ docs/Generators/IceNet.rst | 2 +- docs/Makefile | 4 ++-- docs/TileLink-Diplomacy-Reference/Widgets.rst | 18 +++++++++--------- docs/Tools/Barstools.rst | 2 +- docs/VLSI/Building-A-Chip.rst | 4 ++-- 6 files changed, 29 insertions(+), 15 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index dfadcba6..dc018859 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -145,6 +145,17 @@ jobs: name: Check that the tutorial-setup patches apply command: | scripts/tutorial-setup.sh + documentation-check: + executor: main-env + steps: + - checkout + - run: + name: Check that documentation builds with no warnings/errors + command: | + sudo apt-get update -y + sudo apt-get install -y python3-pip + sudo pip3 install -r docs/requirements.txt + make -C docs html install-riscv-toolchain: executor: main-env @@ -357,6 +368,9 @@ workflows: # Attempt to apply the tutorial patches - tutorial-setup-check + # Check that documentation builds + - documentation-check + # Build extra tests - build-extra-tests: requires: diff --git a/docs/Generators/IceNet.rst b/docs/Generators/IceNet.rst index a8595038..f7daa71e 100644 --- a/docs/Generators/IceNet.rst +++ b/docs/Generators/IceNet.rst @@ -78,7 +78,7 @@ Configuration To add IceNIC to your design, add ``HasPeripheryIceNIC`` to your lazy module and ``HasPeripheryIceNICModuleImp`` to the module implementation. If you are confused about the distinction between lazy module and module -implementation, refer to :ref:`Cake Pattern`. +implementation, refer to :ref:`Cake Pattern / Mixin`. Then add the ``WithIceNIC`` config fragment to your configuration. This will define ``NICKey``, which IceNIC uses to determine its parameters. The config fragment diff --git a/docs/Makefile b/docs/Makefile index fe9f0963..a6e1b4fd 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -2,8 +2,8 @@ # # You can set these variables from the command line. -SPHINXOPTS = -w warnings.txt -SPHINXBUILD = python -msphinx +SPHINXOPTS = -w warnings.txt -n -W +SPHINXBUILD = python3 -msphinx SPHINXPROJ = Chipyard SOURCEDIR = . BUILDDIR = _build diff --git a/docs/TileLink-Diplomacy-Reference/Widgets.rst b/docs/TileLink-Diplomacy-Reference/Widgets.rst index 41fc033b..7eba871b 100644 --- a/docs/TileLink-Diplomacy-Reference/Widgets.rst +++ b/docs/TileLink-Diplomacy-Reference/Widgets.rst @@ -169,7 +169,7 @@ transactions. - ``minSize: Int`` - Minimum size of transfers supported by all outward managers. - ``maxSize: Int`` - Maximum size of transfers supported after the Fragmenter is applied. - ``alwaysMin: Boolean`` - (optional) Fragment all requests down to minSize (else fragment to maximum supported by manager). (default: false) - - ``earlyAck: EarlyAck.T`` - (optional) Should a multibeat Put be acknowledged on the first beat or last beat? + - ``earlyAck: EarlyAck.T`` - (optional) Should a multibeat Put be acknowledged on the first beat or last beat? Possible values (default: ``EarlyAck.None``): - ``EarlyAck.AllPuts`` - always acknowledge on first beat. @@ -270,7 +270,7 @@ the client to see a particular width. **Example Usage:** -.. code-block:: +.. code-block:: scala // Assume the manager node sets beatBytes to 8 // With WidthWidget, client sees beatBytes of 4 @@ -398,11 +398,11 @@ package, not the ``freechips.rocketchip.tilelink`` package like the others. - ``size: Int`` - The size of the memory in bytes - ``contentsDelayed: => Seq[Byte]`` - A function which, when called generates the byte contents of the ROM. - - ``executable: Boolean`` - (optional) Specify whether the CPU can fetch + - ``executable: Boolean`` - (optional) Specify whether the CPU can fetch instructions from the ROM (default: ``true``). - - ``beatBytes: Int`` - (optional) The width of the interface in bytes. + - ``beatBytes: Int`` - (optional) The width of the interface in bytes. (default: 4). - - ``resources: Seq[Resource]`` - (optional) Sequence of resources to add to + - ``resources: Seq[Resource]`` - (optional) Sequence of resources to add to the device tree. **Example Usage:** @@ -429,13 +429,13 @@ The TLRAM and AXI4RAM widgets provide read-write memories implemented as SRAMs. **Arguments:** - ``address: AddressSet`` - The address range that this RAM will cover. - - ``cacheable: Boolean`` - (optional) Can the contents of this RAM be cached. + - ``cacheable: Boolean`` - (optional) Can the contents of this RAM be cached. (default: ``true``) - - ``executable: Boolean`` - (optional) Can the contents of this RAM be fetched + - ``executable: Boolean`` - (optional) Can the contents of this RAM be fetched as instructions. (default: ``true``) - - ``beatBytes: Int`` - (optional) Width of the TL/AXI4 interface in bytes. + - ``beatBytes: Int`` - (optional) Width of the TL/AXI4 interface in bytes. (default: 4) - - ``atomics: Boolean`` - (optional, TileLink only) Does the RAM support + - ``atomics: Boolean`` - (optional, TileLink only) Does the RAM support atomic operations? (default: ``false``) **Example Usage:** diff --git a/docs/Tools/Barstools.rst b/docs/Tools/Barstools.rst index 34562227..9089c947 100644 --- a/docs/Tools/Barstools.rst +++ b/docs/Tools/Barstools.rst @@ -131,5 +131,5 @@ This, unfortunately, breaks the process-agnostic RTL abstraction, so it is recom The simplest way to do this is to have a config fragment that when included updates instantiates the IO cells and connects them in the test harness. When simulating chip-specific designs, it is important to include the IO cells. The IO cell behavioral models will often assert if they are connected incorrectly, which is a useful runtime check. -They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the top module from the test harness`) consistent after synthesis and place-and-route, +They also keep the IO interface at the chip and test harness boundary (see :ref:`Separating the Top module from the TestHarness module`) consistent after synthesis and place-and-route, which allows the RTL simulation test harness to be reused. diff --git a/docs/VLSI/Building-A-Chip.rst b/docs/VLSI/Building-A-Chip.rst index b684a07b..9ce283eb 100644 --- a/docs/VLSI/Building-A-Chip.rst +++ b/docs/VLSI/Building-A-Chip.rst @@ -45,8 +45,8 @@ It is possible to write this IR directly, or to generate it using simple python While we certainly look forward to having a more featureful toolkit, we have built many chips to date in this way. -Running the VLSI flow ---------------------- +Running the VLSI tool flow +-------------------------- For the full documentation on how to use the VLSI tool flow, see the `Hammer Documentation `__. For an example of how to use the VLSI in the context of Chipyard, see :ref:`ASAP7 Tutorial`. From a2177ee20989297935939d3e9aabbfaaa1fe88f2 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 18 Mar 2020 11:03:58 -0700 Subject: [PATCH 055/139] Add Gemmini to README [ci skip] (#487) --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 0eec2d87..8d4cccc5 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -64,3 +64,4 @@ These publications cover many of the internal components used in Chipyard. Howev [boom]: https://github.com/ucb-bar/riscv-boom [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ +[gemmini]: https://github.com/ucb-bar/gemmini From 7a17323bed90dc8a7e64dc286b57a1d0fa456e94 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 19 Mar 2020 10:00:17 -0700 Subject: [PATCH 056/139] [firechip] Isolate all firesim-multiclock stuff in a single file --- build.sbt | 3 +- .../firechip/src/main/scala/FireSim.scala | 41 ++----- .../src/main/scala/FireSimMulticlockPOC.scala | 104 ++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 17 +-- .../src/test/scala/ScalaTestSuite.scala | 13 ++- 5 files changed, 122 insertions(+), 56 deletions(-) create mode 100644 generators/firechip/src/main/scala/FireSimMulticlockPOC.scala diff --git a/build.sbt b/build.sbt index a633066f..b0eea0a8 100644 --- a/build.sbt +++ b/build.sbt @@ -204,5 +204,6 @@ lazy val firechip = conditionalDependsOn(project in file("generators/firechip")) .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, - testGrouping in Test := isolateAllTests( (definedTests in Test).value ) + testGrouping in Test := isolateAllTests( (definedTests in Test).value ), + testOptions in Test += Tests.Argument("-oF") ) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index c6293e90..221548c3 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -5,11 +5,9 @@ package firesim.firesim import chisel3._ import freechips.rocketchip.config.{Field, Config, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} -import freechips.rocketchip.subsystem.{HasTiles} -import freechips.rocketchip.util.{ResetCatchAndSync} +import freechips.rocketchip.diplomacy.{LazyModule} -import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} +import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge} import chipyard.{BuildTop} import chipyard.iobinders.{IOBinders} @@ -22,43 +20,20 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => { case NumNodes => n }) -case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { - def numClocks(): Int = additionalClocks.size + 1 -} -case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) - -trait HasAdditionalClocks extends LazyModuleImp { - val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock()))) -} - -trait HasFireSimClockingImp extends HasAdditionalClocks { - val outer: HasTiles - val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { - case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) - case None => (clocks(0), reset) - } - - outer.tiles.foreach({ case tile => - tile.module.clock := tileClock - tile.module.reset := tileReset - }) -} - -class FireSim[T <: LazyModule](implicit val p: Parameters) extends RawModule { - val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) - val refClock = clockBridge.io.clocks(0) +class FireSim(implicit val p: Parameters) extends RawModule { + val clockBridge = Module(new RationalClockBridge) + val clock = clockBridge.io.clocks.head val reset = WireInit(false.B) - withClockAndReset(refClock, reset) { + withClockAndReset(clock, reset) { // Instantiate multiple instances of the DUT to implement supernode val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) - val peekPokeBridge = PeekPokeBridge(refClock, reset) + val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance for ((target) <- targets) { - p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target)) + p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) } - targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala new file mode 100644 index 00000000..318e3547 --- /dev/null +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -0,0 +1,104 @@ +//See LICENSE for license details. + +package firesim.firesim + +import chisel3._ + +import freechips.rocketchip.config.{Field, Config, Parameters} +import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossing} +import freechips.rocketchip.subsystem._ +import freechips.rocketchip.util.{ResetCatchAndSync} + +import boom.common.{BoomTilesKey, BoomCrossingKey} + +import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} +import firesim.configs._ + +import chipyard.{BuildTop, Top, TopModule} +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders} + +// WIP! This file is a sketch of one means of defining a multiclock target-design +// that can be simulated in FireSim, pending a canonicalized form in Chipyard. +// +// Note, the main prerequisite for supporting an additional clock domain in a +// FireSim simulation is to supply an additional clock parameter +// (RationalClock) to the clock bridge (RationalClockBridge). The bridge +// produces a vector of clocks, based on the provided parameter list, which you +// may use freely without further modifications to your target design. + +case class FireSimClockParameters(additionalClocks: Seq[RationalClock]) { + def numClocks(): Int = additionalClocks.size + 1 +} +case object FireSimClockKey extends Field[FireSimClockParameters](FireSimClockParameters(Seq())) + +trait HasAdditionalClocks extends LazyModuleImp { + val clocks = IO(Vec(p(FireSimClockKey).numClocks, Input(Clock()))) +} + +// Presupposes only 1 or 2 clocks. +trait HasFireSimClockingImp extends HasAdditionalClocks { + val outer: HasTiles + val (tileClock, tileReset) = p(FireSimClockKey).additionalClocks.headOption match { + case Some(RationalClock(_, numer, denom)) if numer != denom => (clocks(1), ResetCatchAndSync(clocks(1), reset.toBool)) + case None => (clocks.head, reset) + } + + outer.tiles.foreach({ case tile => + tile.module.clock := tileClock + tile.module.reset := tileReset + }) +} + +// Config Fragment +class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { + case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) + case RocketCrossingKey => up(RocketCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } + case BoomCrossingKey => up(BoomCrossingKey, site) map { r => + r.copy(crossingType = RationalCrossing()) + } +}) + +class HalfRateUncore extends WithSingleRationalTileDomain(2,1) + +class WithFiresimMulticlockTop extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("Top").module) +}) + +// Complete Config +class FireSimQuadRocketMulticlockConfig extends Config( + new HalfRateUncore ++ + new WithFiresimMulticlockTop ++ + new FireSimQuadRocketConfig) + +// Top Definition +class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.Top +{ + override lazy val module = new FiresimMulticlockTopModule(this) +} + +class FiresimMulticlockTopModule[+L <: Top](l: L) extends chipyard.TopModule(l) with HasFireSimClockingImp + +// Harness Definition +class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { + val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) + val refClock = clockBridge.io.clocks.head + val reset = WireInit(false.B) + withClockAndReset(refClock, reset) { + // Instantiate multiple instances of the DUT to implement supernode + val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val peekPokeBridge = PeekPokeBridge(refClock, reset) + // A Seq of partial functions that will instantiate the right bridge only + // if that Mixin trait is present in the target's class instance + // + // Apply each partial function to each DUT instance + for ((target) <- targets) { + p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target)) + } + targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) + } +} + + diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index ae5d7852..1f9791ee 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -12,9 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} -import freechips.rocketchip.diplomacy.{RationalCrossing} import freechips.rocketchip.diplomacy.LazyModule -import boom.common.{BoomTilesKey, BoomCrossingKey} +import boom.common.BoomTilesKey import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import scala.math.{min, max} @@ -24,7 +23,6 @@ import ariane.ArianeTilesKey import testchipip.WithRingSystemBus import firesim.bridges._ -import midas.widgets.{RationalClock} import firesim.configs._ import chipyard.{BuildTop} import chipyard.config.ConfigValName._ @@ -47,18 +45,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) }) -class WithRationalTiles(multiplier: Int, divisor: Int) extends Config((site, here, up) => { - case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) - case RocketCrossingKey => up(RocketCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } - case BoomCrossingKey => up(BoomCrossingKey, site) map { r => - r.copy(crossingType = RationalCrossing()) - } -}) - -class HalfRateUncore extends WithRationalTiles(2,1) - class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( @@ -197,7 +183,6 @@ class SupernodeFireSimRocketConfig extends Config( //********************************************************************************** //* Ariane Configurations //*********************************************************************************/ - class FireSimArianeConfig extends Config( new WithDefaultFireSimBridges ++ new WithDefaultMemModel ++ diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 161167d9..ee368052 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -131,23 +131,24 @@ abstract class FireSimTestSuite( elaborate generateTestSuiteMakefrags runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) - diffTracelog("rv64ui-p-simple.out") + //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "BaseF1Config") +class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") -class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") +// Disabled until RAM optimizations re-enabled in multiclock +//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") +//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") // Multiclock tests class RocketMulticlockF1Tests extends FireSimTestSuite( - "FireSim", - "HalfRateUncore_DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", + "FireSimMulticlockPOC", + "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) From 2528708c15a189c216250b65f95877fce27273aa Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 16 Mar 2020 13:59:06 -0700 Subject: [PATCH 057/139] add documentation on ring network and system bus --- docs/Customization/Memory-Hierarchy.rst | 14 ++++++++++++++ docs/Generators/TestChipIP.rst | 16 +++++++++++++++- .../src/main/scala/config/RocketConfigs.scala | 2 ++ 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 6c924ceb..733e70c6 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -38,6 +38,20 @@ Note that these configurations fully remove the L2 cache and mbus. This configuration fully removes the L2 cache and memory bus by setting the number of channels and number of banks to 0. +The System Bus +-------------- + +The system bus is the TileLink network that sits between the tiles and the L2 +agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, +but TestChipIP provides a version that uses a ring network instead. This can +be useful when taping out larger systems. To use the ring network system +bus, simply add the ``WithRingSystemBus`` config fragment to your configuration. + +.. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala + :language: scala + :start-after: DOC include start: RingSystemBusRocket + :end-before: DOC include end: RingSystemBusRocket + The SiFive L2 Cache ------------------- diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index f85636b1..31f9ce53 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -3,7 +3,8 @@ Test Chip IP Chipyard includes a Test Chip IP library which provides various hardware widgets that may be useful when designing SoCs. This includes a :ref:`Serial Adapter`, -:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, and :ref:`UART Adapter`. +:ref:`Block Device Controller`, :ref:`TileLink SERDES`, :ref:`TileLink Switcher`, +:ref:`TileLink Ring Network`, and :ref:`UART Adapter`. Serial Adapter -------------- @@ -60,6 +61,19 @@ the select signal once TileLink messages have begun sending. For an example of how to use the switcher, take a look at the ``SwitcherTest`` unit test in the `Test Chip IP unit tests `_. +TileLink Ring Network +--------------------- + +TestChipIP provides a TLRingNetwork generator that has a similar interface +to the TLXbar provided by RocketChip, but uses ring networks internally rather +than crossbars. This can be useful for chips with very wide TileLink networks +(many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve +wire routing congestion. Documentation on how to use the ring network can be +found in :ref:`The System Bus`. The implementation itself can be found +`here `_, +and may serve as an example of how to implement your own TileLink network with +a different topology. + UART Adapter ------------ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 954c531b..e25680ca 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -364,6 +364,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket +// DOC include start: RingSystemBusRocket class RingSystemBusRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ @@ -382,3 +383,4 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new freechips.rocketchip.system.BaseConfig) +// DOC include end: RingSystemBusRocket From 1b7158835ae0bb2f09b0b942fd0636a74e55139e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 24 Mar 2020 10:41:17 -0700 Subject: [PATCH 058/139] Bump firesim for CI --- .../src/test/scala/ScalaTestSuite.scala | 69 ++++++++++--------- sims/firesim | 2 +- 2 files changed, 36 insertions(+), 35 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index ee368052..83d57e24 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -151,37 +151,38 @@ class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") -abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) - extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - lazy val generatorArgs = GeneratorArgs( - midasFlowKind = "midas", - targetDir = "generated-src", - topModuleProject = "firesim.firesim", - topModuleClass = "FireSimTraceGen", - targetConfigProject = "firesim.firesim", - targetConfigs = targetConfig ++ "_WithScalaTestFeatures", - platformConfigProject = "firesim.firesim", - platformConfigs = platformConfig) - - // From HasFireSimGeneratorUtilities - // For the firesim utilities to use the same directory as the test suite - override lazy val testDir = genDir - - // From TestSuiteCommon - val targetTuple = generatorArgs.tupleName - val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", - s"TARGET_CONFIG=${generatorArgs.targetConfigs}", - s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") - - it should "pass" in { - assert(make("fsim-tracegen") == 0) - } -} - -class FireSimLLCTraceGenTest extends FireSimTraceGenTest( - "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") - -class FireSimL2TraceGenTest extends FireSimTraceGenTest( - "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") +// Jerry broke these -- damn it Jerry. +//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) +// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { +// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs +// +// lazy val generatorArgs = GeneratorArgs( +// midasFlowKind = "midas", +// targetDir = "generated-src", +// topModuleProject = "firesim.firesim", +// topModuleClass = "FireSimTraceGen", +// targetConfigProject = "firesim.firesim", +// targetConfigs = targetConfig ++ "_WithScalaTestFeatures", +// platformConfigProject = "firesim.firesim", +// platformConfigs = platformConfig) +// +// // From HasFireSimGeneratorUtilities +// // For the firesim utilities to use the same directory as the test suite +// override lazy val testDir = genDir +// +// // From TestSuiteCommon +// val targetTuple = generatorArgs.tupleName +// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", +// s"TARGET_CONFIG=${generatorArgs.targetConfigs}", +// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") +// +// it should "pass" in { +// assert(make("fsim-tracegen") == 0) +// } +//} +// +//class FireSimLLCTraceGenTest extends FireSimTraceGenTest( +// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") +// +//class FireSimL2TraceGenTest extends FireSimTraceGenTest( +// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") diff --git a/sims/firesim b/sims/firesim index ce0d05a1..552a9764 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ce0d05a10a47e58e17e1b081115429dc6328768d +Subproject commit 552a9764a1b5aebfc9b98c11b2cea944b8befbdd From 7704f38d8da2bd38758df2a57d54c789da1eb407 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Mar 2020 00:23:03 -0700 Subject: [PATCH 059/139] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 552a9764..998eeaea 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 552a9764a1b5aebfc9b98c11b2cea944b8befbdd +Subproject commit 998eeaea230884584dd3fe2bd3727c5f30abc3cb From fbc47af67cb8df379347b26e30c3b7ade75306b7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Mar 2020 10:19:51 -0700 Subject: [PATCH 060/139] Bump testchipip to dev [ci skip] --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 582f17da..30d44252 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 582f17da80dbe0e03a35247a385f34bd88a656ce +Subproject commit 30d44252e8a990da38f1fed6ac6c810fb42dae28 From b5b15878279b2ff86b7b1a76d046e9f65deeb622 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Mar 2020 10:34:14 -0700 Subject: [PATCH 061/139] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 998eeaea..3cf0d45e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 998eeaea230884584dd3fe2bd3727c5f30abc3cb +Subproject commit 3cf0d45e07c0685cafaf02f86d91ff114e160b38 From 3d253c0f6751d5da1b4484a219ddec0dd4bff620 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 30 Mar 2020 17:04:45 -0700 Subject: [PATCH 062/139] [make] split up specific make vars/targets into frags (#499) * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder --- common.mk | 45 ++++++++----------- generators/ariane | 2 +- .../scala/{ => config}/ArianeConfigs.scala | 0 generators/tracegen/tracegen.mk | 18 ++++++++ sims/vcs/Makefile | 11 ++--- sims/verilator/Makefile | 25 ++++++++--- variables.mk | 2 +- 7 files changed, 62 insertions(+), 41 deletions(-) rename generators/chipyard/src/main/scala/{ => config}/ArianeConfigs.scala (100%) create mode 100644 generators/tracegen/tracegen.mk diff --git a/common.mk b/common.mk index bf40e602..4fb2cf82 100644 --- a/common.mk +++ b/common.mk @@ -3,6 +3,18 @@ ######################################################################################### SHELL=/bin/bash +######################################################################################### +# extra make variables/rules from subprojects +# +# EXTRA_GENERATOR_REQS - requirements needed for the main generator +# EXTRA_SIM_FLAGS - runtime simulation flags +# EXTRA_SIM_CC_FLAGS - cc flags for simulators +# EXTRA_SIM_SOURCES - simulation sources needed for simulator +# EXTRA_SIM_REQS - requirements to build the simulator +######################################################################################### +include $(base_dir)/generators/ariane/ariane.mk +include $(base_dir)/generators/tracegen/tracegen.mk + ######################################################################################### # variables to get all *.scala files ######################################################################################### @@ -11,7 +23,6 @@ lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -prin SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) -ARIANE_VLOG_SOURCES = $(call lookup_srcs,$(base_dir)/generators/ariane,sv) $(call lookup_srcs,$(base_dir)/generators/ariane,v) ######################################################################################### # rocket and testchipip classes @@ -45,7 +56,7 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp @echo "" > /dev/null # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile -generator_temp: $(SCALA_SOURCES) $(ARIANE_VLOG_SOURCES) $(sim_files) +generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" @@ -105,19 +116,19 @@ verilog: $(sim_vsrcs) ######################################################################################### .PHONY: run-binary run-binary-fast run-binary-debug run-fast run-binary: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) ######################################################################################### # helper rules to run simulator as fast as possible ######################################################################################### run-binary-fast: $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log) run-fast: run-asm-tests-fast run-bmark-tests-fast @@ -129,10 +140,10 @@ $(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/% ln -sf $< $@ $(output_dir)/%.run: $(output_dir)/% $(sim) - (set -o pipefail && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) ######################################################################################### # include build/project specific makefrags made from the generator @@ -141,26 +152,6 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),) -include $(build_dir)/$(long_name).d endif -################################################# -# Rules for running and checking tracegen tests # -################################################# - -AXE_DIR=$(base_dir)/tools/axe/src -AXE=$(AXE_DIR)/axe - -$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh - cd $(AXE_DIR) && ./make.sh - -$(output_dir)/tracegen.out: $(sim) - mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ - -$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) - $(base_dir)/scripts/check-tracegen.sh $< > $@ - -tracegen: $(output_dir)/tracegen.result - -.PHONY: tracegen - ####################################### # Rules for building DRAMSim2 library # ####################################### diff --git a/generators/ariane b/generators/ariane index 145b5ed1..e02436d2 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 145b5ed106efd0b22c2105c20722ab303fa4039b +Subproject commit e02436d2aaf934b6e58d5e11e87276ba0d840f2a diff --git a/generators/chipyard/src/main/scala/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala similarity index 100% rename from generators/chipyard/src/main/scala/ArianeConfigs.scala rename to generators/chipyard/src/main/scala/config/ArianeConfigs.scala diff --git a/generators/tracegen/tracegen.mk b/generators/tracegen/tracegen.mk new file mode 100644 index 00000000..fc4bd246 --- /dev/null +++ b/generators/tracegen/tracegen.mk @@ -0,0 +1,18 @@ +############################################################## +# extra variables/targets ingested by the chipyard make system +############################################################## + +AXE_DIR=$(base_dir)/tools/axe/src +AXE=$(AXE_DIR)/axe + +$(AXE): $(wildcard $(AXE_DIR)/*.[ch]) $(AXE_DIR)/make.sh + cd $(AXE_DIR) && ./make.sh + +$(output_dir)/tracegen.out: $(sim) + mkdir -p $(output_dir) && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none $@ + +$(output_dir)/tracegen.result: $(output_dir)/tracegen.out $(AXE) + $(base_dir)/scripts/check-tracegen.sh $< > $@ + +.PHONY: tracegen +tracegen: $(output_dir)/tracegen.result diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index e829047c..659d1fc0 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -50,7 +50,8 @@ VCS_CC_OPTS = \ -CC "-I$(dramsim_dir)" \ -CC "-std=c++11" \ $(dramsim_lib) \ - $(RISCV)/lib/libfesvr.a + $(RISCV)/lib/libfesvr.a \ + -CC "$(EXTRA_SIM_CC_FLAGS)" VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ @@ -80,16 +81,16 @@ VCS_DEFINES = \ +define+RANDOMIZE_GARBAGE_ASSIGN \ +define+RANDOMIZE_INVALID_ASSIGN -VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) +VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINES) $(EXTRA_SIM_SOURCES) ######################################################################################### # vcs simulator rules ######################################################################################### -$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ -debug_pp -$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) +$(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ +define+DEBUG \ -debug_pp @@ -99,7 +100,7 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) ######################################################################################### .PRECIOUS: $(output_dir)/%.vpd %.vpd $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 13e7d201..8bd4cd75 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -47,14 +47,25 @@ include $(base_dir)/common.mk ######################################################################################### VERILATOR := verilator --cc --exe -CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -I$(dramsim_dir) -D__STDC_FORMAT_MACROS -LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(dramsim_dir) -Wl,-rpath,$(dramsim_dir) -L$(sim_dir) -lfesvr -lpthread -ldramsim +CXXFLAGS := \ + $(CXXFLAGS) -O1 -std=c++11 \ + -I$(RISCV)/include \ + -I$(dramsim_dir) \ + -D__STDC_FORMAT_MACROS \ + $(EXTRA_SIM_CC_FLAGS) + +LDFLAGS := \ + $(LDFLAGS) \ + -L$(sim_dir) \ + -lpthread VERILATOR_CC_OPTS = \ -O3 \ -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \ -CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(build_dir)/verilator.h" \ - -LDFLAGS "$(LDFLAGS)" + -LDFLAGS "$(LDFLAGS)" \ + $(RISCV)/lib/libfesvr.a \ + $(dramsim_lib) # default flags added for ariane ARIANE_VERILATOR_FLAGS = \ @@ -87,7 +98,7 @@ VERILATOR_DEFINES = \ +define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \ +define+STOP_COND=\$$c\(\"done_reset\"\) -VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) +VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS) $(VERILATOR_DEFINES) $(EXTRA_SIM_SOURCES) ######################################################################################### # verilator build paths and file names @@ -104,13 +115,13 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk ######################################################################################### # build makefile fragment that builds the verilator sim rules ######################################################################################### -$(model_mk): $(sim_vsrcs) $(sim_common_files) +$(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ -$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) +$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) rm -rf $(build_dir)/$(long_name) mkdir -p $(build_dir)/$(long_name).debug $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" @@ -132,7 +143,7 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) rm -f $@.vcd && mkfifo $@.vcd vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) +max-cycles=$(timeout_cycles) $(SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule diff --git a/variables.mk b/variables.mk index 8a1bb1df..5692296b 100644 --- a/variables.mk +++ b/variables.mk @@ -143,7 +143,7 @@ output_dir=$(sim_dir)/output/$(long_name) # helper variables to run binaries ######################################################################################### BINARY ?= -SIM_FLAGS ?= +override SIM_FLAGS += +dramsim +max-cycles=$(timeout_cycles) VERBOSE_FLAGS ?= +verbose sim_out_name = $(subst $() $(),_,$(notdir $(basename $(BINARY))).$(long_name)) From 1f98c842100f4fa1e4b39cc0fc95e7b5f19a8829 Mon Sep 17 00:00:00 2001 From: John Wright Date: Wed, 1 Apr 2020 14:03:56 -0700 Subject: [PATCH 063/139] Add ChipTop to enable real chip configs with IO cells, etc. (#480) This adds an additional layer (ChipTop) between the System module and the TestHarness. The IOBinder API is now changed to take only a single parameter (an Any) and return a 3 things: The IO port(s), the IO cell(s), and a function to call inside the test harness, which is analogous to the old IOBinder function, except that it takes a TestHarness object as an argument instead of (clock, reset, success). * A new Top-level module, ChipTop, has been created. ChipTop instantiates a "system" module specified by BuildSystem. * BuildTop now builds a ChipTop dut module in the TestHarness by default * A new BuildSystem key has been added, which by default builds DigitalTop (previously just called Top) * The IOBinders API has changed. IOBinders are now called inside of ChipTop and return a tuple3 of (IO ports, IO cells, harness functions). The harness functions are now called inside the TestHarness (this is analogous to the previous IOBinder functions). * IO cell models have been included in ChipTop. These can be replaced with real IO cells for tapeout, or used as-is for simulation. * The default for the TOP make variable is now ChipTop (was Top) --- build.sbt | 6 +- common.mk | 2 +- docs/Advanced-Concepts/Top-Testharness.rst | 21 +- .../Configs-Parameters-Mixins.rst | 15 +- docs/Customization/DMA-Devices.rst | 6 +- docs/Customization/IOBinders.rst | 24 +- docs/Customization/Keys-Traits-Configs.rst | 16 +- docs/Customization/MMIO-Peripherals.rst | 18 +- .../chipyard/src/main/scala/ChipTop.scala | 102 ++++++++ .../src/main/scala/ConfigFragments.scala | 16 +- .../scala/{Top.scala => DigitalTop.scala} | 10 +- .../chipyard/src/main/scala/IOBinders.scala | 237 +++++++++++++----- .../chipyard/src/main/scala/TestHarness.scala | 28 ++- .../main/scala/config/TracegenConfigs.scala | 10 +- .../src/main/scala/BridgeBinders.scala | 70 ++++-- .../firechip/src/main/scala/FireSim.scala | 6 +- .../src/main/scala/FireSimMulticlockPOC.scala | 12 +- .../src/main/scala/TargetConfigs.scala | 1 - generators/icenet | 2 +- generators/testchipip | 2 +- scripts/tutorial-patches/build.sbt.patch | 2 +- tools/barstools | 2 +- variables.mk | 2 +- 23 files changed, 444 insertions(+), 166 deletions(-) create mode 100644 generators/chipyard/src/main/scala/ChipTop.scala rename generators/chipyard/src/main/scala/{Top.scala => DigitalTop.scala} (86%) diff --git a/build.sbt b/build.sbt index b0eea0a8..05f05d7b 100644 --- a/build.sbt +++ b/build.sbt @@ -122,8 +122,12 @@ lazy val testchipip = (project in file("generators/testchipip")) .dependsOn(rocketchip, sifive_blocks) .settings(commonSettings) +lazy val iocell = (project in file("./tools/barstools/iocell/")) + .dependsOn(chisel) + .settings(commonSettings) + lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches gemmini, icenet, tracegen, ariane) .settings(commonSettings) diff --git a/common.mk b/common.mk index 4fb2cf82..a98e0e24 100644 --- a/common.mk +++ b/common.mk @@ -20,7 +20,7 @@ include $(base_dir)/generators/tracegen/tracegen.mk ######################################################################################### lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) -SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim) +SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) diff --git a/docs/Advanced-Concepts/Top-Testharness.rst b/docs/Advanced-Concepts/Top-Testharness.rst index 8df37769..ebd5b370 100644 --- a/docs/Advanced-Concepts/Top-Testharness.rst +++ b/docs/Advanced-Concepts/Top-Testharness.rst @@ -2,17 +2,28 @@ Tops, Test-Harnesses, and the Test-Driver =========================================== The three highest levels of hierarchy in a Chipyard -SoC are the Top (DUT), ``TestHarness``, and the ``TestDriver``. -The Top and ``TestHarness`` are both emitted by Chisel generators. +SoC are the ``ChipTop`` (DUT), ``TestHarness``, and the ``TestDriver``. +The ``ChipTop`` and ``TestHarness`` are both emitted by Chisel generators. The ``TestDriver`` serves as our testbench, and is a Verilog file in Rocket Chip. -Top/DUT +ChipTop/DUT ------------------------- -The top-level module of a Rocket Chip SoC is composed via cake-pattern. -Specifically, "Tops" extend a ``System``, which extends a ``Subsystem``, which extends a ``BaseSubsystem``. +``ChipTop`` is the top-level module that instantiates the ``System`` submodule, usually an instance of the concrete class ``DigitalTop``. +The vast majority of the design resides in the ``System``. +Other components that exist inside the ``ChipTop`` layer are generally IO cells, clock receivers and multiplexers, reset synchronizers, and other analog IP that needs to exist outside of the ``System``. +The ``IOBinders`` are responsible for instantiating the IO cells and defining the test harness collateral that connects to the top-level ports. +Most of these types of devices can be instantiated using custom ``IOBinders``, so the provided ``ChipTop`` and ``ChipTopCaughtReset`` classes are sufficient. +However, if needed, the ``BaseChipTop`` abstract class can be extended for building more custom ``ChipTop`` designs. + + +System/DigitalTop +------------------------- + +The system module of a Rocket Chip SoC is composed via cake-pattern. +Specifically, ``DigitalTop`` extends a ``System``, which extends a ``Subsystem``, which extends a ``BaseSubsystem``. BaseSubsystem diff --git a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst index 9d7d86d0..94067aa1 100644 --- a/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst +++ b/docs/Chipyard-Basics/Configs-Parameters-Mixins.rst @@ -77,10 +77,10 @@ It is used in the Rocket Chip SoC library and Chipyard framework in merging mult This example shows the Chipyard default top that composes multiple traits together into a fully-featured SoC with many optional components. -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop There are two "cakes" or mixins here. One for the lazy module (ex. ``CanHavePeripherySerial``) and one for the lazy module @@ -88,8 +88,8 @@ implementation (ex. ``CanHavePeripherySerialModuleImp`` where ``Imp`` refers to all the logical connections between generators and exchanges configuration information among them, while the lazy module implementation performs the actual Chisel RTL elaboration. -In the ``Top`` example class, the "outer" ``Top`` instantiates the "inner" -``TopModule`` as a lazy module implementation. This delays immediate elaboration +In the ``DigitalTop`` example class, the "outer" ``DigitalTop`` instantiates the "inner" +``DigitalTopModule`` as a lazy module implementation. This delays immediate elaboration of the module until all logical connections are determined and all configuration information is exchanged. The ``System`` outer base class, as well as the ``CanHavePeriphery`` outer traits contain code to perform high-level logical @@ -102,8 +102,9 @@ For example, the ``CanHavePeripherySerialModuleImp`` trait optionally physically the ``SerialAdapter`` module, and instantiates queues. In the test harness, the SoC is elaborated with -``val dut = Module(LazyModule(Top))``. -After elaboration, the result will be a ``Top`` module, which contains a +``val dut = p(BuildTop)(p)``. + +After elaboration, the system submodule of ``ChipTop`` will be a ``DigitalTop`` module, which contains a ``SerialAdapter`` module (among others), if the config specified for that block to be instantiated. From a high level, classes which extend ``LazyModule`` *must* reference diff --git a/docs/Customization/DMA-Devices.rst b/docs/Customization/DMA-Devices.rst index 554ff2d4..549a1556 100644 --- a/docs/Customization/DMA-Devices.rst +++ b/docs/Customization/DMA-Devices.rst @@ -15,10 +15,10 @@ that writes zeros to the memory at a configured address. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/InitZero.scala :language: scala -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop We use ``TLHelper.makeClientNode`` to create a TileLink client node for us. We then connect the client node to the memory system through the front bus (fbus). diff --git a/docs/Customization/IOBinders.rst b/docs/Customization/IOBinders.rst index 59924a0f..6332d07a 100644 --- a/docs/Customization/IOBinders.rst +++ b/docs/Customization/IOBinders.rst @@ -1,7 +1,7 @@ IOBinders ========= -In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what modules to bind to the IOs of a ``Top`` in the ``TestHarness``. +In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to instantiate IO cells in the ``ChipTop`` layer and determine what modules to bind to the IOs of a ``ChipTop`` in the ``TestHarness``. .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala :language: scala @@ -9,11 +9,27 @@ In Chipyard we use a special ``Parameters`` key, ``IOBinders`` to determine what :end-before: DOC include end: IOBinders -This special key solves the problem of duplicating test-harnesses for each different ``Top`` type. +This special key solves the problem of duplicating test-harnesses for each different ``System`` type. +You could just as well create a custom harness module that attaches IOs explicitly. +Instead, the ``IOBinders`` key provides a map from Scala traits to attachment behaviors. +Each ``IOBinder`` returns a tuple of three values: the list of ``ChipTop`` ports created by the ``IOBinder``, the list of all IO cell modules instantiated by the ``IOBinder``, and an optional function to be called inside the test harness. +This function is responsible for instantiating logic inside the ``TestHarness`` to appropriately drive the ``ChipTop`` IO ports created by the ``IOBinder``. +Conveniently, because the ``IOBinder`` is generating the port, it may also use the port inside this function, which prevents the ``BaseChipTop`` code from ever needing to access the port ``val``, thus having the ``IOBinder`` house all port specific code. +This scheme prevents the need to have two separate binder functions for each ``System`` trait. +When creating custom ``IOBinders`` it is important to use ``suggestName`` to name ports; otherwise Chisel will raise an exception trying to name the IOs. +The example ``IOBinders`` demonstrate this. -You could just as well create a custom harness module that attaches IOs explicitly. Instead, the IOBinders key provides a map from Scala traits to attachment behaviors. +As an example, the ``WithGPIOTiedOff`` IOBinder creates IO cells for the GPIO module(s) instantiated in the ``System``, then punches out new ``Analog`` ports for each one. +The test harness simply ties these off, but additional logic could be inserted to perform some kind of test in the ``TestHarness``. -For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``Top`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected. +.. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala + :language: scala + :start-after: DOC include start: WithGPIOTiedOff + :end-before: DOC include end: WithGPIOTiedOff + + +``IOBinders`` also do not need to create ports. Some ``IOBinders`` can simply insert circuitry inside the ``ChipTop`` layer. +For example, the ``WithSimAXIMemTiedOff`` IOBinder specifies that any ``System`` which matches ``CanHaveMasterAXI4MemPortModuleImp`` will have a ``SimAXIMem`` connected inside ``ChipTop``. .. literalinclude:: ../../generators/chipyard/src/main/scala/IOBinders.scala :language: scala diff --git a/docs/Customization/Keys-Traits-Configs.rst b/docs/Customization/Keys-Traits-Configs.rst index ffa303b7..f4af3746 100644 --- a/docs/Customization/Keys-Traits-Configs.rst +++ b/docs/Customization/Keys-Traits-Configs.rst @@ -34,25 +34,25 @@ Accessing the value stored in the key is easy in Chisel, as long as the ``implic Traits ------ -Typically, most custom blocks will need to modify the behavior of some pre-existing block. For example, the GCD widget needs the ``Top`` module to instantiate and connect the widget via Tilelink, generate a top-level ``gcd_busy`` port, and connect that to the module as well. Traits let us do this without modifying the existing code for the ``Top``, and enables compartmentalization of code for different custom blocks. +Typically, most custom blocks will need to modify the behavior of some pre-existing block. For example, the GCD widget needs the ``DigitalTop`` module to instantiate and connect the widget via Tilelink, generate a top-level ``gcd_busy`` port, and connect that to the module as well. Traits let us do this without modifying the existing code for the ``DigitalTop``, and enables compartmentalization of code for different custom blocks. -Top-level traits specify that the ``Top`` has been parameterized to read some custom key and optionally instantiate and connect a widget defined by that key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the key is unset is a no-op. +Top-level traits specify that the ``DigitalTop`` has been parameterized to read some custom key and optionally instantiate and connect a widget defined by that key. Traits **should not** mandate the instantiation of custom logic. In other words, traits should be written with ``CanHave`` semantics, where the default behavior when the key is unset is a no-op. -Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``Top`` being used by Chipyard. +Top-level traits should be defined and documented in subprojects, alongside their corresponding keys. The traits should then be added to the ``DigitalTop`` being used by Chipyard. -Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``Top`` to instantiate an additional port and concretely connect it to the GCD module. +Below we see the traits for the GCD example. The Lazy trait connects the GCD module to the Diplomacy graph, while the Implementation trait causes the ``DigitalTop`` to instantiate an additional port and concretely connect it to the GCD module. .. literalinclude:: ../../generators/chipyard/src/main/scala/example/GCD.scala :language: scala :start-after: DOC include start: GCD lazy trait :end-before: DOC include end: GCD imp trait -These traits are added to the default ``Top`` in Chipyard. +These traits are added to the default ``DigitalTop`` in Chipyard. -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop Config Fragments ---------------- diff --git a/docs/Customization/MMIO-Peripherals.rst b/docs/Customization/MMIO-Peripherals.rst index f6b429be..15ed5a00 100644 --- a/docs/Customization/MMIO-Peripherals.rst +++ b/docs/Customization/MMIO-Peripherals.rst @@ -87,21 +87,21 @@ For peripherals which instantiate a concrete module, or which need to be connect :start-after: DOC include start: GCD imp trait :end-before: DOC include end: GCD imp trait -Constructing the Top and Config -------------------------------- +Constructing the DigitalTop and Config +-------------------------------------- Now we want to mix our traits into the system as a whole. -This code is from ``generators/chipyard/src/main/scala/Top.scala``. +This code is from ``generators/chipyard/src/main/scala/DigitalTop.scala``. -.. literalinclude:: ../../generators/chipyard/src/main/scala/Top.scala +.. literalinclude:: ../../generators/chipyard/src/main/scala/DigitalTop.scala :language: scala - :start-after: DOC include start: Top - :end-before: DOC include end: Top + :start-after: DOC include start: DigitalTop + :end-before: DOC include end: DigitalTop Just as we need separate traits for ``LazyModule`` and module implementation, we need two classes to build the system. -The ``Top`` class contains the set of traits which parameterize and define the ``Top``. Typically these traits will optionally add IOs or peripherals to the ``Top``. -The ``Top`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``). -The ``TopModule`` class is the actual RTL that gets synthesized. +The ``DigitalTop`` class contains the set of traits which parameterize and define the ``DigitalTop``. Typically these traits will optionally add IOs or peripherals to the ``DigitalTop``. +The ``DigitalTop`` class includes the pre-elaboration code and also a ``lazy val`` to produce the module implementation (hence ``LazyModule``). +The ``DigitalTopModule`` class is the actual RTL that gets synthesized. diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala new file mode 100644 index 00000000..328891a8 --- /dev/null +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -0,0 +1,102 @@ +package chipyard + +import chisel3._ + +import scala.collection.mutable.{ArrayBuffer} + +import freechips.rocketchip.config.{Parameters, Field} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.util.{ResetCatchAndSync} +import chipyard.config.ConfigValName._ +import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} + +import barstools.iocell.chisel._ + +case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module)) + +/** + * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, + * named "system", which is an instance of DigitalTop by default. The default clock and reset for "system" are set by two + * wires, "systemClock" and "systemReset", which are intended to be driven by traits mixed-in with this base class. + */ +abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with HasTestHarnessFunctions { + + // A publicly accessible list of IO cells (useful for a floorplanning tool, for example) + val iocells = ArrayBuffer.empty[IOCell] + // A list of functions to call in the test harness + val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] + // The system clock + val systemClock = Wire(Input(Clock())) + // The system reset (synchronous to clock) + val systemReset = Wire(Input(Bool())) + + // The system module specified by BuildSystem + val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) } + + // Call all of the IOBinders and provide them with a default clock and reset + withClockAndReset(systemClock, systemReset) { + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3 + // We ignore _ports for now... + iocells ++= _iocells.flatten + harnessFunctions ++= _harnessFunctions.flatten + } + +} + +/** + * A simple clock and reset implementation that punches out clock and reset ports with the same + * names as the implicit clock and reset for standard Module classes. Reset is synchronous to + * clock, which may not be a good idea to use for tapeouts. + */ +trait HasChipTopSimpleClockAndReset { this: BaseChipTop => + + val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) + val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) + + iocells ++= systemClockIO + iocells ++= systemResetIO + + // Add a TestHarnessFunction that connects clock and reset + harnessFunctions += { (th: TestHarness) => { + // Connect clock; it's not done implicitly with RawModule + clock := th.clock + // Connect reset; it's not done implicitly with RawModule + // Note that we need to use dutReset, not harnessReset + reset := th.dutReset + Nil + } } + +} + +/** + * Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset + * can be asynchronous with clock, which is useful for tapeout configs. + */ +trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop => + + val asyncResetCore = Wire(Input(Bool())) + systemReset := ResetCatchAndSync(systemClock, asyncResetCore) + + val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) + val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset")) + + iocells ++= systemClockIO + iocells ++= asyncResetIO + + // Add a TestHarnessFunction that connects clock and areset + harnessFunctions += { (th: TestHarness) => { + // Connect clock; it's not done implicitly with RawModule + clock := th.clock + // Connect reset; it's not done implicitly with RawModule + // Note that we need to use dutReset, not harnessReset + areset := th.dutReset + Nil + } } + +} + +class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p) + with HasChipTopSimpleClockAndReset + +class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p) + with HasChipTopSimpleClockAndCaughtReset diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index dae6e055..495c3367 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import chipyard.{BuildTop} +import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset} /** * TODO: Why do we need this? @@ -65,8 +65,8 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { )) }) -class WithTracegenTop extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) +class WithTracegenSystem extends Config((site, here, up) => { + case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) }) @@ -150,3 +150,13 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) + + +/** + * Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to + * the top-level reset, allowing it to be asynchronous with the clock. + * NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config + */ +class WithChipTopCaughtReset extends Config((site, here, up) => { + case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top")) +}) diff --git a/generators/chipyard/src/main/scala/Top.scala b/generators/chipyard/src/main/scala/DigitalTop.scala similarity index 86% rename from generators/chipyard/src/main/scala/Top.scala rename to generators/chipyard/src/main/scala/DigitalTop.scala index d81d779a..c7b3d497 100644 --- a/generators/chipyard/src/main/scala/Top.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -11,8 +11,8 @@ import freechips.rocketchip.devices.tilelink._ // BOOM and/or Rocket Top Level Systems // ------------------------------------ -// DOC include start: Top -class Top(implicit p: Parameters) extends System +// DOC include start: DigitalTop +class DigitalTop(implicit p: Parameters) extends System with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device @@ -23,10 +23,10 @@ class Top(implicit p: Parameters) extends System with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget { - override lazy val module = new TopModule(this) + override lazy val module = new DigitalTopModule(this) } -class TopModule[+L <: Top](l: L) extends SystemModule(l) +class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripherySerialModuleImp @@ -35,4 +35,4 @@ class TopModule[+L <: Top](l: L) extends SystemModule(l) with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch -// DOC include end: Top +// DOC include end: DigitalTop diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 938ecc5f..6388c3db 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -1,19 +1,22 @@ -package chipyard.iobinders +package chipyard +package object iobinders { import chisel3._ +import chisel3.experimental.{Analog, IO} import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ -import freechips.rocketchip.system._ import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ +import barstools.iocell.chisel._ + import testchipip._ -import icenet._ +import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey} import tracegen.{HasTraceGenTilesModuleImp} import scala.reflect.{ClassTag} @@ -26,23 +29,32 @@ import scala.reflect.{ClassTag} // IO connection behavior for tops matching that trait. We use strings to enable // composition and overriding of IOBinders, much like how normal Keys in the config // system are used/ At elaboration, the testharness traverses this set of functions, -// and functions which match the type of the Top are evaluated. +// and functions which match the type of the DigitalTop are evaluated. // You can add your own binder by adding a new (key, fn) pair, typically by using // the OverrideIOBinder or ComposeIOBinder macros + // DOC include start: IOBinders -case object IOBinders extends Field[Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]]( - Map[String, (Clock, Bool, Bool, Any) => Seq[Any]]().withDefaultValue((c: Clock, r: Bool, s: Bool, t: Any) => Nil) +// This type describes a function callable on the TestHarness instance. Its return type is unused. +type TestHarnessFunction = (chipyard.TestHarness) => Seq[Any] +// IOBinders will return a Seq of this tuple, which contains three fields: +// 1. A Seq containing all IO ports created by the IOBinder function +// 2. A Seq containing all IO cell modules created by the IOBinder function +// 3. An optional function to call inside the test harness (e.g. to connect the IOs) +type IOBinderTuple = (Seq[Data], Seq[IOCell], Option[TestHarnessFunction]) + +case object IOBinders extends Field[Map[String, (Any) => Seq[IOBinderTuple]]]( + Map[String, (Any) => Seq[IOBinderTuple]]().withDefaultValue((Any) => Nil) ) // This macro overrides previous matches on some Top mixin. This is useful for // binders which drive IO, since those typically cannot be composed -class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class OverrideIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + ((t: Any) => { t match { - case top: T => fn(clock, reset, success, top) + case system: T => fn(system) case _ => Nil } }) @@ -51,12 +63,12 @@ class OverrideIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit ta // This macro composes with previous matches on some Top mixin. This is useful for // annotation-like binders, since those can typically be composed -class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { +class ComposeIOBinder[T](fn: => (T) => Seq[IOBinderTuple])(implicit tag: ClassTag[T]) extends Config((site, here, up) => { case IOBinders => up(IOBinders, site) + (tag.runtimeClass.toString -> - ((clock: Clock, reset: Bool, success: Bool, t: Any) => { + ((t: Any) => { t match { - case top: T => (up(IOBinders, site)(tag.runtimeClass.toString)(clock, reset, success, top) - ++ fn(clock, reset, success, top)) + case system: T => (up(IOBinders, site)(tag.runtimeClass.toString)(system) + ++ fn(system)) case _ => Nil } }) @@ -65,74 +77,146 @@ class ComposeIOBinder[T](fn: => (Clock, Bool, Bool, T) => Seq[Any])(implicit tag // DOC include end: IOBinders +object AddIOCells { + /** + * Add IO cells to a SiFive GPIO devices and name the IO ports. + * @param gpios A Seq of GPIO port bundles + * @param genFn A callable function to generate a DigitalGPIOCell module to use + * @return Returns a tuple of (a 2D Seq of Analog IOs corresponding to individual GPIO pins; a 2D Seq of IOCell module references) + */ + def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = { + gpios.zipWithIndex.map({ case (gpio, i) => + gpio.pins.zipWithIndex.map({ case (pin, j) => + val g = IO(Analog(1.W)) + g.suggestName("gpio_${i}_${j}") + val iocell = genFn() + iocell.suggestName(s"iocell_gpio_${i}_${j}") + iocell.io.o := pin.o.oval + iocell.io.oe := pin.o.oe + iocell.io.ie := pin.o.ie + pin.i.ival := iocell.io.i + iocell.io.pad <> g + (g, iocell) + }).unzip + }).unzip + } + + /** + * Add IO cells to a SiFive UART devices and name the IO ports. + * @param gpios A Seq of UART port bundles + * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references) + */ + def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = { + uartPins.zipWithIndex.map({ case (u, i) => + val (port, ios) = IOCell.generateIOFromSignal(u, Some(s"iocell_uart_${i}")) + port.suggestName(s"uart_${i}") + (port, ios) + }).unzip + } + + /** + * Add IO cells to a debug module and name the IO ports. + * @param gpios A PSDIO bundle + * @param debugOpt An optional DebugIO bundle + * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) + */ + def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = { + val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd")) + val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug"))) + val debugPortOpt: Option[DebugIO] = optTuple.map(_._1) + val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten + debugPortOpt.foreach(_.suggestName("debug")) + psdPort.suggestName("psd") + (psdPort, debugPortOpt, psdIOs ++ debugIOs) + } + + /** + * Add IO cells to a serial module and name the IO ports. + * @param serial A SerialIO bundle + * @return Returns a tuple of (Top-level SerialIO IO; a list of IOCell module references) + */ + def serial(serial: SerialIO): (SerialIO, Seq[IOCell]) = { + val (port, ios) = IOCell.generateIOFromSignal(serial, Some("iocell_serial")) + port.suggestName("serial") + (port, ios) + } +} + +// DOC include start: WithGPIOTiedOff class WithGPIOTiedOff extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryGPIOModuleImp) => top.gpio.map(gpio => gpio.pins.map(p => p.i.ival := false.B)); Nil + (system: HasPeripheryGPIOModuleImp) => { + val (ports2d, ioCells2d) = AddIOCells.gpio(system.gpio) + val harnessFn = (th: chipyard.TestHarness) => { ports2d.flatten.foreach(_ <> AnalogConst(0)); Nil } + Seq((ports2d.flatten, ioCells2d.flatten, Some(harnessFn))) + } +}) +// DOC include end: WithGPIOTiedOff + +class WithUARTAdapter extends OverrideIOBinder({ + (system: HasPeripheryUARTModuleImp) => { + val (ports, ioCells2d) = AddIOCells.uart(system.uart) + val harnessFn = (th: chipyard.TestHarness) => { UARTAdapter.connect(ports)(system.p); Nil } + Seq((ports, ioCells2d.flatten, Some(harnessFn))) + } }) class WithSimBlockDevice extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectSimBlockDevice(c, r); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil }) class WithBlockDeviceModel extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryBlockDeviceModuleImp) => top.connectBlockDeviceModel(); Nil + (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectBlockDeviceModel(); Nil }) class WithLoopbackNIC extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectNicLoopback(); Nil + (system: CanHavePeripheryIceNICModuleImp) => system.connectNicLoopback(); Nil }) class WithSimNIC extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripheryIceNICModuleImp) => top.connectSimNetwork(c, r); Nil -}) - -class WithUARTAdapter extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryUARTModuleImp) => { - val defaultBaudRate = 115200 // matches sifive-blocks uart baudrate - top.uart.zipWithIndex.foreach{ case (dut_io, i) => - val uart_sim = Module(new UARTAdapter(i, defaultBaudRate)(top.p)) - uart_sim.io.uart.txd := dut_io.txd - dut_io.rxd := uart_sim.io.uart.rxd - } - Nil - } + (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (c, r, s, top: CanHaveMasterAXI4MemPortModuleImp) => top.connectSimAXIMem(); Nil + (system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil }) // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (clock, reset, _, top: CanHaveMasterAXI4MemPortModuleImp) => { - (top.mem_axi4 zip top.outer.memAXI4Node).foreach { case (io, node) => - val memSize = top.p(ExtMem).get.master.size - val lineSize = top.p(CacheBlockBytes) + (system: CanHaveMasterAXI4MemPortModuleImp) => { + (system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) => + val memSize = system.p(ExtMem).get.master.size + val lineSize = system.p(CacheBlockBytes) (io zip node.in).foreach { case (axi4, (_, edge)) => val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) mem.io.axi <> axi4 - mem.io.clock := clock - mem.io.reset := reset + mem.io.clock := system.clock + mem.io.reset := system.reset } }; Nil } }) class WithSimAXIMMIO extends OverrideIOBinder({ - (c, r, s, top: CanHaveMasterAXI4MMIOPortModuleImp) => top.connectSimAXIMMIO(); Nil + (system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil }) class WithDontTouchPorts extends OverrideIOBinder({ - (c, r, s, top: DontTouch) => top.dontTouchPorts(); Nil + (system: DontTouch) => system.dontTouchPorts(); Nil }) class WithTieOffInterrupts extends OverrideIOBinder({ - (c, r, s, top: HasExtInterruptsBundle) => top.tieOffInterrupts(); Nil + (system: HasExtInterruptsModuleImp) => { + val (port, ioCells) = IOCell.generateIOFromSignal(system.interrupts, Some("iocell_interrupts")) + port.suggestName("interrupts") + val harnessFn = (th: chipyard.TestHarness) => { port := 0.U; Nil } + Seq((Seq(port), ioCells, Some(harnessFn))) + } }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (c, r, s, top: CanHaveSlaveAXI4PortModuleImp) => { - top.l2_frontend_bus_axi4.foreach(axi => { + (system: CanHaveSlaveAXI4PortModuleImp) => { + system.l2_frontend_bus_axi4.foreach(axi => { axi.tieoff() experimental.DataMirror.directionOf(axi.ar.ready) match { case ActualDirection.Input => @@ -142,6 +226,7 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ axi.aw.bits := DontCare axi.ar.bits := DontCare axi.w.bits := DontCare + case _ => throw new Exception("Unknown AXI port direction") } }) Nil @@ -149,38 +234,62 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ }) class WithTiedOffDebug extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(top.debug, top.psd) - // tieoffDebug doesn't actually tie everything off :/ - top.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) - Nil + (system: HasPeripheryDebugModuleImp) => { + val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val harnessFn = (th: chipyard.TestHarness) => { + Debug.tieoffDebug(debugPortOpt, psdPort) + // tieoffDebug doesn't actually tie everything off :/ + debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } + Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) } }) -class WithSimSerial extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripherySerialModuleImp) => { - val ser_success = top.connectSimSerial() - when (ser_success) { s := true.B } - Nil +class WithSimDebug extends OverrideIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val harnessFn = (th: chipyard.TestHarness) => { + val dtm_success = Wire(Bool()) + Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) + when (dtm_success) { th.success := true.B } + th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) + Nil + } + Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) } }) class WithTiedOffSerial extends OverrideIOBinder({ - (c, r, s, top: CanHavePeripherySerialModuleImp) => top.tieoffSerial(); Nil + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + val (port, ioCells) = AddIOCells.serial(serial) + val harnessFn = (th: chipyard.TestHarness) => { + SerialAdapter.tieoff(port) + Nil + } + Seq((Seq(port), ioCells, Some(harnessFn))) + }).getOrElse(Nil) }) +class WithSimSerial extends OverrideIOBinder({ + (system: CanHavePeripherySerialModuleImp) => system.serial.map({ serial => + val (port, ioCells) = AddIOCells.serial(serial) + val harnessFn = (th: chipyard.TestHarness) => { + val ser_success = SerialAdapter.connectSimSerial(port, th.clock, th.harnessReset) + when (ser_success) { th.success := true.B } + Nil + } + Seq((Seq(port), ioCells, Some(harnessFn))) + }).getOrElse(Nil) +}) -class WithSimDebug extends OverrideIOBinder({ - (c, r, s, top: HasPeripheryDebugModuleImp) => { - val dtm_success = Wire(Bool()) - top.reset := r | top.debug.map { debug => AsyncResetReg(debug.ndreset) }.getOrElse(false.B) - Debug.connectDebug(top.debug, top.psd, c, r, dtm_success)(top.p) - when (dtm_success) { s := true.B } - Nil +class WithTraceGenSuccessBinder extends OverrideIOBinder({ + (system: HasTraceGenTilesModuleImp) => { + val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) + successPort.suggestName("success") + val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } + Seq((Seq(successPort), ioCells, Some(harnessFn))) } }) - -class WithTraceGenSuccessBinder extends OverrideIOBinder({ - (c, r, s, top: HasTraceGenTilesModuleImp) => when (top.success) { s := true.B }; Nil -}) +} diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index ca861288..4aaef747 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -1,23 +1,21 @@ package chipyard import chisel3._ -import chisel3.experimental._ -import firrtl.transforms.{BlackBoxResourceAnno, BlackBoxSourceHelper} - -import freechips.rocketchip.diplomacy.LazyModule +import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.util.GeneratorApp -import freechips.rocketchip.devices.debug.{Debug} - +import chipyard.iobinders.{TestHarnessFunction} import chipyard.config.ConfigValName._ -import chipyard.iobinders.{IOBinders} // ------------------------------- // BOOM and/or Rocket Test Harness // ------------------------------- -case object BuildTop extends Field[Parameters => Any]((p: Parameters) => Module(LazyModule(new Top()(p)).suggestName("top").module)) +case object BuildTop extends Field[Parameters => HasTestHarnessFunctions]((p: Parameters) => Module(new ChipTop()(p))) + +trait HasTestHarnessFunctions { + val harnessFunctions: Seq[TestHarnessFunction] +} class TestHarness(implicit val p: Parameters) extends Module { val io = IO(new Bundle { @@ -26,5 +24,15 @@ class TestHarness(implicit val p: Parameters) extends Module { val dut = p(BuildTop)(p) io.success := false.B - p(IOBinders).values.map(fn => fn(clock, reset.asBool, io.success, dut)) + + // dutReset can be overridden via a harnessFunction, but by default it is just reset + val dutReset = Wire(Bool()) + dutReset := reset + + dut.harnessFunctions.foreach(_(this)) + + def success = io.success + def harnessReset = this.reset.asBool + } + diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index ead38869..fefa271d 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -6,21 +6,21 @@ import freechips.rocketchip.rocket.{DCacheParams} class TraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) @@ -28,7 +28,7 @@ class BoomTraceGenConfig extends Config( class NonBlockingTraceGenL2Config extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.system.BaseConfig) @@ -36,7 +36,7 @@ class NonBlockingTraceGenL2Config extends Config( class NonBlockingTraceGenL2RingConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++ - new chipyard.config.WithTracegenTop ++ + new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index ebd12d1b..ae6c82fa 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -7,10 +7,11 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp +import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} import icenet.CanHavePeripheryIceNICModuleImp @@ -29,56 +30,55 @@ import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.HasChipyardTilesModuleImp class WithSerialBridge extends OverrideIOBinder({ - (c, r, s, target: CanHavePeripherySerialModuleImp) => - target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq + (system: CanHavePeripherySerialModuleImp) => + system.serial.foreach(s => SerialBridge(system.clock, s)(system.p)); Nil }) class WithNICBridge extends OverrideIOBinder({ - (c, r, s, target: CanHavePeripheryIceNICModuleImp) => - target.net.map(n => NICBridge(target.clock, n)(target.p)).toSeq + (system: CanHavePeripheryIceNICModuleImp) => + system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil }) class WithUARTBridge extends OverrideIOBinder({ - (c, r, s, target: HasPeripheryUARTModuleImp) => - target.uart.map(u => UARTBridge(target.clock, u)(target.p)).toSeq + (system: HasPeripheryUARTModuleImp) => + system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil }) class WithBlockDeviceBridge extends OverrideIOBinder({ - (c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => - target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq + (system: CanHavePeripheryBlockDeviceModuleImp) => + system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil }) class WithFASEDBridge extends OverrideIOBinder({ - (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { - implicit val p = t.p - (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => + (system: CanHaveMasterAXI4MemPortModuleImp) => { + implicit val p = system.p + (system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDBridge(t.clock, axi4Bundle, t.reset.toBool, + FASEDBridge(system.clock, axi4Bundle, system.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) - }).toSeq + }) + Nil } }) class WithTracerVBridge extends OverrideIOBinder({ - (c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO match { - case Some(t) => t.traces.map(tileTrace => TracerVBridge(tileTrace)(target.p)) - case None => Nil - } + (system: CanHaveTraceIOModuleImp) => + system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil }) class WithTraceGenBridge extends OverrideIOBinder({ - (c, r, s, target: HasTraceGenTilesModuleImp) => - Seq(GroundTestBridge(target.clock, target.success)(target.p)) + (system: HasTraceGenTilesModuleImp) => + GroundTestBridge(system.clock, system.success)(system.p); Nil }) class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ - (c, r, s, target: HasChipyardTilesModuleImp) => { - target.outer.tiles.map { + (system: HasChipyardTilesModuleImp) => { + system.outer.tiles.map { case r: RocketTile => { annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) @@ -100,13 +100,31 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ } }) +class WithTiedOffSystemGPIO extends OverrideIOBinder({ + (system: HasPeripheryGPIOModuleImp) => + system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil +}) + +class WithTiedOffSystemDebug extends OverrideIOBinder({ + (system: HasPeripheryDebugModuleImp) => { + Debug.tieoffDebug(system.debug, system.psd) + // tieoffDebug doesn't actually tie everything off :/ + system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + Nil + } +}) + +class WithTiedOffSystemInterrupts extends OverrideIOBinder({ + (system: HasExtInterruptsModuleImp) => + system.interrupts := 0.U; Nil +}) // Shorthand to register all of the provided bridges above class WithDefaultFireSimBridges extends Config( - new chipyard.iobinders.WithGPIOTiedOff ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithTieOffInterrupts ++ + new WithTiedOffSystemGPIO ++ + new WithTiedOffSystemDebug ++ + new WithTiedOffSystemInterrupts ++ new WithSerialBridge ++ new WithNICBridge ++ new WithUARTBridge ++ diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 221548c3..157b8907 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge} -import chipyard.{BuildTop} +import chipyard.{BuildSystem} import chipyard.iobinders.{IOBinders} // Determines the number of times to instantiate the DUT in the harness. @@ -26,14 +26,14 @@ class FireSim(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(clock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance for ((target) <- targets) { - p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) + p(IOBinders).values.map(_(target)) } } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 318e3547..b16f99c7 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -14,7 +14,7 @@ import boom.common.{BoomTilesKey, BoomCrossingKey} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} import firesim.configs._ -import chipyard.{BuildTop, Top, TopModule} +import chipyard.{BuildSystem, DigitalTop, DigitalTopModule} import chipyard.config.ConfigValName._ import chipyard.iobinders.{IOBinders} @@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config class HalfRateUncore extends WithSingleRationalTileDomain(2,1) class WithFiresimMulticlockTop extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("Top").module) + case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module) }) // Complete Config @@ -74,12 +74,12 @@ class FireSimQuadRocketMulticlockConfig extends Config( new FireSimQuadRocketConfig) // Top Definition -class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.Top +class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop { override lazy val module = new FiresimMulticlockTopModule(this) } -class FiresimMulticlockTopModule[+L <: Top](l: L) extends chipyard.TopModule(l) with HasFireSimClockingImp +class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp // Harness Definition class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { @@ -88,14 +88,14 @@ class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(refClock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildTop)(p)) + val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) val peekPokeBridge = PeekPokeBridge(refClock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance for ((target) <- targets) { - p(IOBinders).values.map(fn => fn(refClock, reset.asBool, false.B, target)) + p(IOBinders).values.map(_(target)) } targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) } diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 1f9791ee..04d9a8f6 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -24,7 +24,6 @@ import testchipip.WithRingSystemBus import firesim.bridges._ import firesim.configs._ -import chipyard.{BuildTop} import chipyard.config.ConfigValName._ class WithBootROM extends Config((site, here, up) => { diff --git a/generators/icenet b/generators/icenet index f2272284..b1f957e6 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit f22722847444ecfcd5369f1b33547727d051b834 +Subproject commit b1f957e6eb022c662f0fb33c7ddfbddc686bfde5 diff --git a/generators/testchipip b/generators/testchipip index 30d44252..d06d7c7d 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 30d44252e8a990da38f1fed6ac6c810fb42dae28 +Subproject commit d06d7c7dc274420a5fc5600ba8bdb2003cc9b0cd diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 422c59c8..6f20a3ce 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -5,7 +5,7 @@ index a633066..3df8b74 100644 @@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) - .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, + .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches gemmini, icenet, tracegen, ariane) diff --git a/tools/barstools b/tools/barstools index 63d74bc1..db677636 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 63d74bc177cb070126eb0e662ff0ea500722a8d7 +Subproject commit db6776367c7a8f4850266d72f81cd4c90561731a diff --git a/variables.mk b/variables.mk index 5692296b..4953c968 100644 --- a/variables.mk +++ b/variables.mk @@ -36,7 +36,7 @@ ifeq ($(SUB_PROJECT),chipyard) CONFIG_PACKAGE ?= $(SBT_PROJECT) GENERATOR_PACKAGE ?= $(SBT_PROJECT) TB ?= TestDriver - TOP ?= Top + TOP ?= ChipTop endif # for Rocket-chip developers ifeq ($(SUB_PROJECT),rocketchip) From ea8b3487dc6e7e67677e5c8211fce336516b0bea Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 1 Apr 2020 22:25:48 -0700 Subject: [PATCH 064/139] [ci-skip] Bump spec2017 marshal workloads --- software/spec2017 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/spec2017 b/software/spec2017 index b8643136..a4333f24 160000 --- a/software/spec2017 +++ b/software/spec2017 @@ -1 +1 @@ -Subproject commit b86431364360a9e64487e5dec2962c48bafb67ff +Subproject commit a4333f243cef6bfff08bcbb08f3ec467b4c720d0 From ba199879844ccb163203f39b0ead3ec1393157c5 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 1 Dec 2019 22:27:12 -0800 Subject: [PATCH 065/139] [firechip] Label FASED instances with an associated memory region name --- .../src/main/scala/BridgeBinders.scala | 26 ++++++++++++++++--- .../firechip/src/main/scala/FireSim.scala | 11 +++++++- 2 files changed, 33 insertions(+), 4 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index ebd12d1b..4276890b 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -28,9 +28,14 @@ import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.HasChipyardTilesModuleImp +object MainMemoryConsts { + val regionNamePrefix = "MainMemory" + def globalName(): String = s"${regionNamePrefix}_${NodeIdx()}" +} + class WithSerialBridge extends OverrideIOBinder({ (c, r, s, target: CanHavePeripherySerialModuleImp) => - target.serial.map(s => SerialBridge(target.clock, s)(target.p)).toSeq + target.serial.map(s => SerialBridge(target.clock, s, MainMemoryConsts.globalName)(target.p)).toSeq }) class WithNICBridge extends OverrideIOBinder({ @@ -48,7 +53,19 @@ class WithBlockDeviceBridge extends OverrideIOBinder({ target.bdev.map(b => BlockDevBridge(target.clock, b, target.reset.toBool)(target.p)).toSeq }) -class WithFASEDBridge extends OverrideIOBinder({ +// Assign a unique name to each target memory space, consisting of one or more +// memory channels. In the multi-node case, serial widgets can then disambiguate +// each memory region using this string instead of relying on the assumption +// the target has a single memory channel. +object MemoryRegionNames { + var idx = -1 + def getName(): String = { + idx += 1 + s"memory_${idx}" + } +} + +class WithFASEDBridge extends OverrideIOBinder ({ (c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => { implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -57,7 +74,10 @@ class WithFASEDBridge extends OverrideIOBinder({ axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) FASEDBridge(t.clock, axi4Bundle, t.reset.toBool, - CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) }) }).toSeq } diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 221548c3..0cd8f410 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -20,6 +20,14 @@ class WithNumNodes(n: Int) extends Config((pname, site, here) => { case NumNodes => n }) +// Hacky: Set before each node is generated. Ideally we'd give IO binders +// accesses to the the Harness's parameters instance. We could then alter that. +object NodeIdx { + private var idx = 0 + def increment(): Unit = {idx = idx + 1 } + def apply(): Int = idx +} + class FireSim(implicit val p: Parameters) extends RawModule { val clockBridge = Module(new RationalClockBridge) val clock = clockBridge.io.clocks.head @@ -32,8 +40,9 @@ class FireSim(implicit val p: Parameters) extends RawModule { // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance - for ((target) <- targets) { + for (target <- targets) { p(IOBinders).values.map(fn => fn(clock, reset.asBool, false.B, target)) + NodeIdx.increment() } } } From 64d563d493daad928a43f08c716f52ffb411eab6 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 7 Apr 2020 12:04:39 -0700 Subject: [PATCH 066/139] Bump FireSim for Pow2 fix --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index a4f0a18c..b1ff973a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a4f0a18c0aa1690a57dd888be6bc48f52fbc074c +Subproject commit b1ff973a2541f58c30d99ed170bd30527c216414 From 87739a9fe3de48227ebd15812322a8724df520fd Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Wed, 8 Apr 2020 21:18:06 -0700 Subject: [PATCH 067/139] toolchains: Bump libgloss for trap handler support --- toolchains/libgloss | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/libgloss b/toolchains/libgloss index 117b9997..e0a2cf5a 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit 117b9997bf46b93687e52f8ea102bd89478de493 +Subproject commit e0a2cf5a6e317d58fd9c9de5c07a00dae8c5ec36 From 543121972dec2bae6df862df1af5de03950581aa Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 10 Apr 2020 22:01:00 +0000 Subject: [PATCH 068/139] Bump FireSIm --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index b1ff973a..f04c08a7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit b1ff973a2541f58c30d99ed170bd30527c216414 +Subproject commit f04c08a713014d8835331ed8f8c64525c0d5f2e4 From 4ef3b1a5466202338e0e9db0b37a8d04b4c7166a Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 10 Apr 2020 22:26:17 +0000 Subject: [PATCH 069/139] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index f04c08a7..7c121894 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f04c08a713014d8835331ed8f8c64525c0d5f2e4 +Subproject commit 7c121894e97f32b2fdaf719673c2a2f2ecbe5312 From ada8410ab2e14b0ddd02db6552997efea1d7dda2 Mon Sep 17 00:00:00 2001 From: alonamid Date: Sat, 11 Apr 2020 12:52:55 -0700 Subject: [PATCH 070/139] bump esp spike --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 9163c430..3c930b40 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 9163c430be06d43dc0ecc43698791fc36cc3402d +Subproject commit 3c930b403140ac0cd1fc5578a21998f6875459c6 From dc01b4da4b3c8b1539135bd181263f0aec074c13 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 13 Apr 2020 16:31:14 -0700 Subject: [PATCH 071/139] add documentation on baremetal tool flow --- docs/Software/Baremetal.rst | 25 +++++++++++++++++++++++++ docs/Software/index.rst | 1 + 2 files changed, 26 insertions(+) create mode 100644 docs/Software/Baremetal.rst diff --git a/docs/Software/Baremetal.rst b/docs/Software/Baremetal.rst new file mode 100644 index 00000000..2f0961e9 --- /dev/null +++ b/docs/Software/Baremetal.rst @@ -0,0 +1,25 @@ +.. _baremetal-programs: + +Baremetal RISC-V Programs +========================== + +To build baremetal RISC-V programs to run in simulation, we use the riscv64-unknown-elf cross-compiler and a fork of the libgloss board support package. To build such a program yourself, simply invoke the cross-compiler with the flags "-fno-common -fno-builtin-printf -specs=htif_nano.specs" and the link with the arguments "-static -specs=htif_nano.specs". For instance, if we want to run a "Hello, World" program in baremetal, we could do the following. + +.. code:: c + + #include + + int main(void) + { + printf("Hello, World!\n"); + return 0; + } + +.. code:: bash + + $ riscv64-unknown-elf-gcc -fno-common -fno-builtin-printf -specs=htif_nano.specs -c hello.c + $ riscv64-unknown-elf-gcc -static -specs=htif_nano.specs hello.o -o hello.riscv + $ spike hello.riscv + Hello, World! + +For more examples, look at the `tests/ directory `_ in the chipyard repository. diff --git a/docs/Software/index.rst b/docs/Software/index.rst index e7fe9925..04b5a5fd 100644 --- a/docs/Software/index.rst +++ b/docs/Software/index.rst @@ -19,3 +19,4 @@ challenging to modify. FireMarshal Spike + Baremetal From a6d9589ed8fbc22288eeb40503d213af964a1e43 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 15 Apr 2020 13:38:49 -0700 Subject: [PATCH 072/139] [ci] add approval button (#510) --- .circleci/config.yml | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index dc018859..5469c56c 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -356,20 +356,35 @@ workflows: build-and-test-chipyard-integration: jobs: + - ci-approval: + type: approval + # Make the toolchains - - install-riscv-toolchain + - install-riscv-toolchain: + requires: + - ci-approval - - install-esp-toolchain + - install-esp-toolchain: + requires: + - ci-approval - - install-verilator + - install-verilator: + requires: + - ci-approval - - commit-on-master-check + - commit-on-master-check: + requires: + - ci-approval # Attempt to apply the tutorial patches - - tutorial-setup-check + - tutorial-setup-check: + requires: + - ci-approval # Check that documentation builds - - documentation-check + - documentation-check: + requires: + - ci-approval # Build extra tests - build-extra-tests: From e6ff6874d411351b3477517d050f157d555e8595 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 15 Apr 2020 14:21:12 -0700 Subject: [PATCH 073/139] add link to libgloss-htif README --- docs/Software/Baremetal.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Software/Baremetal.rst b/docs/Software/Baremetal.rst index 2f0961e9..4bfeaef4 100644 --- a/docs/Software/Baremetal.rst +++ b/docs/Software/Baremetal.rst @@ -23,3 +23,5 @@ To build baremetal RISC-V programs to run in simulation, we use the riscv64-unkn Hello, World! For more examples, look at the `tests/ directory `_ in the chipyard repository. + +For more information about the libgloss port, take a look at `its README `_. From 24b63c95773ff9d27521ca777284c8e273de5149 Mon Sep 17 00:00:00 2001 From: Tynan McAuley <16469394+tymcauley@users.noreply.github.com> Date: Wed, 15 Apr 2020 20:35:56 -0700 Subject: [PATCH 074/139] Fix bug in verilator Makefile for 'debug' rule (#513) The 'debug' rule is currently cleaning out the non-debug-model directory rather than the debug-model directory. This commit fixes that, and changes both the debug and non-debug rules to use the variables defined for referring to these two model directories. Co-authored-by: Tynan McAuley --- sims/verilator/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 8bd4cd75..0ab0016c 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -116,14 +116,14 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk # build makefile fragment that builds the verilator sim rules ######################################################################################### $(model_mk): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) - rm -rf $(build_dir)/$(long_name) - mkdir -p $(build_dir)/$(long_name) + rm -rf $(model_dir) + mkdir -p $(model_dir) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)" touch $@ $(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(EXTRA_SIM_REQS) - rm -rf $(build_dir)/$(long_name) - mkdir -p $(build_dir)/$(long_name).debug + rm -rf $(model_dir_debug) + mkdir -p $(model_dir_debug) $(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)" touch $@ From 629a0449d6e18b7ba1ef0541c82873de7b85b909 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 16 Apr 2020 15:43:18 -0700 Subject: [PATCH 075/139] toolchains: Bump libgloss for trap handler fix (#516) --- toolchains/libgloss | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/libgloss b/toolchains/libgloss index e0a2cf5a..a88e50f2 160000 --- a/toolchains/libgloss +++ b/toolchains/libgloss @@ -1 +1 @@ -Subproject commit e0a2cf5a6e317d58fd9c9de5c07a00dae8c5ec36 +Subproject commit a88e50f2e1b0411e0a7d5e5c29d5b40117560912 From b303cf6e81fe3c12431a019b81c12d1c2cce5056 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 8 Apr 2020 14:47:57 -0700 Subject: [PATCH 076/139] Rocket Chip Stage/Phase Bump (#503) [WIP] Minimally elaborating design Bring up a feature-complete Chipyard stage Pull in Makefrag generation; Bump submodules Update config generation, and global reset scheme Bump submodules; clean up Bump FireSim Remove some unhygenic comments / WS Remove the rocketchip subproject [CI] Lengthen ariane tests timeout Address some remaining reviewer comments [firechip] Refresh a Field that cannot be used across repeated instantiations Bump all submodules --- .circleci/config.yml | 1 + .circleci/defaults.sh | 1 - build.sbt | 1 + common.mk | 6 +- generators/ariane | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/ChipTop.scala | 95 +++++++++++-------- .../src/main/scala/ConfigFragments.scala | 14 +-- .../chipyard/src/main/scala/Generator.scala | 40 +------- .../chipyard/src/main/scala/IOBinders.scala | 68 ++++++++----- .../chipyard/src/main/scala/Subsystem.scala | 16 +--- .../chipyard/src/main/scala/System.scala | 3 - .../chipyard/src/main/scala/TestHarness.scala | 5 +- .../chipyard/src/main/scala/TestSuites.scala | 83 ++++++++-------- .../scala/stage/ChipyardAnnotations.scala | 20 ++++ .../src/main/scala/stage/ChipyardCli.scala | 15 +++ .../src/main/scala/stage/ChipyardStage.scala | 36 +++++++ .../scala/stage/phases/AddDefaultTests.scala | 62 ++++++++++++ .../phases/GenerateTestSuiteMakefrags.scala | 49 ++++++++++ .../src/main/scala/BridgeBinders.scala | 31 +++--- .../firechip/src/main/scala/FireSim.scala | 18 +++- .../src/main/scala/FireSimMulticlockPOC.scala | 13 ++- .../firechip/src/main/scala/Generator.scala | 21 ++-- .../src/main/scala/TargetConfigs.scala | 2 +- .../src/test/scala/ScalaTestSuite.scala | 2 +- generators/hwacha | 2 +- generators/icenet | 2 +- generators/rocket-chip | 2 +- generators/sifive-blocks | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/System.scala | 1 - project/build.properties | 2 +- project/plugins.sbt | 1 + sims/firesim | 2 +- tools/barstools | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- variables.mk | 34 +------ 38 files changed, 406 insertions(+), 256 deletions(-) create mode 100644 generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala create mode 100644 generators/chipyard/src/main/scala/stage/ChipyardCli.scala create mode 100644 generators/chipyard/src/main/scala/stage/ChipyardStage.scala create mode 100644 generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala create mode 100644 generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala diff --git a/.circleci/config.yml b/.circleci/config.yml index dc018859..d91e7115 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -338,6 +338,7 @@ jobs: steps: - run-tests: project-key: "chipyard-ariane" + timeout: "30m" # Order and dependencies of jobs to run workflows: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 552ac1db..7d4fdaa3 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,6 @@ mapping["chipyard-rocket"]="SUB_PROJECT=chipyard" mapping["chipyard-sha3"]="SUB_PROJECT=chipyard CONFIG=Sha3RocketConfig" mapping["chipyard-hetero"]="SUB_PROJECT=chipyard CONFIG=LargeBoomAndRocketConfig" mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" -mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" diff --git a/build.sbt b/build.sbt index 05f05d7b..b0e8c84d 100644 --- a/build.sbt +++ b/build.sbt @@ -166,6 +166,7 @@ lazy val gemmini = (project in file("generators/gemmini")) lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) .settings(commonSettings) + .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0")) lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/")) .settings(commonSettings) diff --git a/common.mk b/common.mk index a98e0e24..696e0f83 100644 --- a/common.mk +++ b/common.mk @@ -58,7 +58,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) mkdir -p $(build_dir) - cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)" + cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \ + --target-dir $(build_dir) \ + --name $(long_name) \ + --top-module $(MODEL_PACKAGE).$(MODEL) \ + --legacy-configs $(CONFIG_PACKAGE).$(CONFIG)" .PHONY: firrtl firrtl: $(FIRRTL_FILE) diff --git a/generators/ariane b/generators/ariane index e02436d2..621201b1 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit e02436d2aaf934b6e58d5e11e87276ba0d840f2a +Subproject commit 621201b1d5a929ab0e89f1a857b76a33e7e2e8a8 diff --git a/generators/boom b/generators/boom index a26504f3..90911dde 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit a26504f34db8327a5d4d9bb3a342dddf79e02b35 +Subproject commit 90911dde1b8730f10c958d172f26f72d718be5ae diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala index 328891a8..d0b4df02 100644 --- a/generators/chipyard/src/main/scala/ChipTop.scala +++ b/generators/chipyard/src/main/scala/ChipTop.scala @@ -12,7 +12,42 @@ import chipyard.iobinders.{IOBinders, TestHarnessFunction, IOBinderTuple} import barstools.iocell.chisel._ -case object BuildSystem extends Field[Parameters => RawModule]((p: Parameters) => Module(LazyModule(new DigitalTop()(p)).suggestName("system").module)) +case object BuildSystem extends Field[Parameters => LazyModule]((p: Parameters) => LazyModule(new DigitalTop()(p))) + +/** + * Chipyard provides three baseline, top-level reset schemes, set using the + * [[GlobalResetSchemeKey]] in a Parameters instance. These are: + * + * 1) Synchronous: The input coming to the chip is synchronous to the provided + * clocks and will be used without modification as a synchronous reset. + * This is safe only for use in FireSim and SW simulation. + * + * 2) Asynchronous: The input reset is asynchronous to the input clock, but it + * is caught and synchronized to that clock before it is dissemenated. + * Thus, downsteam modules will be emitted with synchronously reset state + * elements. + * + * 3) Asynchronous Full: The input reset is asynchronous to the input clock, + * and is used globally as an async reset. Downstream modules will be emitted + * with asynchronously reset state elements. + * + */ +sealed trait GlobalResetScheme { + def pinIsAsync: Boolean +} +sealed trait HasAsyncInput { self: GlobalResetScheme => + def pinIsAsync = true +} + +sealed trait HasSyncInput { self: GlobalResetScheme => + def pinIsAsync = false +} + +case object GlobalResetSynchronous extends GlobalResetScheme with HasSyncInput +case object GlobalResetAsynchronous extends GlobalResetScheme with HasAsyncInput +case object GlobalResetAsynchronousFull extends GlobalResetScheme with HasAsyncInput +case object GlobalResetSchemeKey extends Field[GlobalResetScheme](GlobalResetSynchronous) + /** * The base class used for building chips. This constructor instantiates a module specified by the BuildSystem parameter, @@ -26,16 +61,21 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with // A list of functions to call in the test harness val harnessFunctions = ArrayBuffer.empty[TestHarnessFunction] // The system clock + // These are given so that IOCell can use DataMirror and generate ports with + // the right flow (Input/Output) val systemClock = Wire(Input(Clock())) - // The system reset (synchronous to clock) - val systemReset = Wire(Input(Bool())) + val systemReset = Wire(Input(Reset())) // The system module specified by BuildSystem - val system = withClockAndReset(systemClock, systemReset) { p(BuildSystem)(p) } + val lSystem = p(BuildSystem)(p).suggestName("system") + val system = withClockAndReset(systemClock, systemReset) { Module(lSystem.module) } // Call all of the IOBinders and provide them with a default clock and reset withClockAndReset(systemClock, systemReset) { - val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.map(_(system)).flatten.unzip3 + // Call each IOBinder on both the lazyModule instance and the module + // instance. Generally, an IOBinder PF should only be defined on one, so + // this should not lead to two invocations. + val (_ports, _iocells, _harnessFunctions) = p(IOBinders).values.flatMap(f => f(lSystem) ++ f(system)).unzip3 // We ignore _ports for now... iocells ++= _iocells.flatten harnessFunctions ++= _harnessFunctions.flatten @@ -45,13 +85,22 @@ abstract class BaseChipTop()(implicit val p: Parameters) extends RawModule with /** * A simple clock and reset implementation that punches out clock and reset ports with the same - * names as the implicit clock and reset for standard Module classes. Reset is synchronous to - * clock, which may not be a good idea to use for tapeouts. + * names as the implicit clock and reset for standard Module classes. Three basic reset schemes + * are provided. See [[GlobalResetScheme]]. */ trait HasChipTopSimpleClockAndReset { this: BaseChipTop => val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) - val (reset, systemResetIO) = IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) + val (reset, systemResetIO) = p(GlobalResetSchemeKey) match { + case GlobalResetSynchronous => + IOCell.generateIOFromSignal(systemReset, Some("iocell_reset")) + case GlobalResetAsynchronousFull => + IOCell.generateIOFromSignal(systemReset, Some("iocell_reset"), abstractResetAsAsync = true) + case GlobalResetAsynchronous => + val asyncResetCore = Wire(Input(AsyncReset())) + systemReset := ResetCatchAndSync(systemClock, asyncResetCore.asBool) + IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_reset"), abstractResetAsAsync = true) + } iocells ++= systemClockIO iocells ++= systemResetIO @@ -68,35 +117,5 @@ trait HasChipTopSimpleClockAndReset { this: BaseChipTop => } -/** - * Variant of HasChipTopSimpleClockAndReset that adds a reset synchronizer so that the top-level reset - * can be asynchronous with clock, which is useful for tapeout configs. - */ -trait HasChipTopSimpleClockAndCaughtReset { this: BaseChipTop => - - val asyncResetCore = Wire(Input(Bool())) - systemReset := ResetCatchAndSync(systemClock, asyncResetCore) - - val (clock, systemClockIO) = IOCell.generateIOFromSignal(systemClock, Some("iocell_clock")) - val (areset, asyncResetIO) = IOCell.generateIOFromSignal(asyncResetCore, Some("iocell_areset")) - - iocells ++= systemClockIO - iocells ++= asyncResetIO - - // Add a TestHarnessFunction that connects clock and areset - harnessFunctions += { (th: TestHarness) => { - // Connect clock; it's not done implicitly with RawModule - clock := th.clock - // Connect reset; it's not done implicitly with RawModule - // Note that we need to use dutReset, not harnessReset - areset := th.dutReset - Nil - } } - -} - class ChipTop()(implicit p: Parameters) extends BaseChipTop()(p) with HasChipTopSimpleClockAndReset - -class ChipTopCaughtReset()(implicit p: Parameters) extends BaseChipTop()(p) - with HasChipTopSimpleClockAndCaughtReset diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 495c3367..dee1a40a 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -21,7 +21,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ -import chipyard.{BuildTop, BuildSystem, ChipTopCaughtReset} +import chipyard.{BuildTop, BuildSystem} /** * TODO: Why do we need this? @@ -66,7 +66,7 @@ class WithL2TLBs(entries: Int) extends Config((site, here, up) => { }) class WithTracegenSystem extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => Module(LazyModule(new tracegen.TraceGenSystem()(p)).suggestName("Top").module) + case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) }) @@ -150,13 +150,3 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) - - -/** - * Config fragment to use ChipTopCaughtReset as the top module, which adds a reset synchronizer to - * the top-level reset, allowing it to be asynchronous with the clock. - * NOTE: You must remember to set TOP=WithChipTopCaughtReset when building with this config - */ -class WithChipTopCaughtReset extends Config((site, here, up) => { - case BuildTop => (p: Parameters) => Module(new ChipTopCaughtReset()(p).suggestName("top")) -}) diff --git a/generators/chipyard/src/main/scala/Generator.scala b/generators/chipyard/src/main/scala/Generator.scala index 4baba357..d5a53a06 100644 --- a/generators/chipyard/src/main/scala/Generator.scala +++ b/generators/chipyard/src/main/scala/Generator.scala @@ -1,40 +1,6 @@ package chipyard -import scala.util.Try +import firrtl.options.{StageMain} +import chipyard.stage.ChipyardStage -import chisel3._ - -import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{GeneratorApp} -import freechips.rocketchip.system.{TestGeneration} - -object Generator extends GeneratorApp { - // add unique test suites - override def addTestSuites { - implicit val p: Parameters = params - TestSuiteHelper.addRocketTestSuites - TestSuiteHelper.addBoomTestSuites - TestSuiteHelper.addArianeTestSuites - - // if hwacha parameter exists then generate its tests - // TODO: find a more elegant way to do this. either through - // trying to disambiguate BuildRoCC, having a AccelParamsKey, - // or having the Accelerator/Tile add its own tests - import hwacha.HwachaTestSuites._ - if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) { - TestGeneration.addSuites(rv64uv.map(_("p"))) - TestGeneration.addSuites(rv64uv.map(_("vp"))) - TestGeneration.addSuite(rv64sv("p")) - TestGeneration.addSuite(hwachaBmarks) - } - } - - // specify the name that the generator outputs files as - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - - // generate files - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} +object Generator extends StageMain(new ChipyardStage) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 6388c3db..e3c79f3a 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -8,6 +8,7 @@ import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug._ import freechips.rocketchip.subsystem._ +import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ @@ -117,17 +118,28 @@ object AddIOCells { /** * Add IO cells to a debug module and name the IO ports. * @param gpios A PSDIO bundle + * @param resetctrlOpt An optional ResetCtrlIO bundle * @param debugOpt An optional DebugIO bundle * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) */ - def debug(psd: PSDIO, debugOpt: Option[DebugIO]): (PSDIO, Option[DebugIO], Seq[IOCell]) = { - val (psdPort, psdIOs) = IOCell.generateIOFromSignal(psd, Some("iocell_psd")) - val optTuple = debugOpt.map(d => IOCell.generateIOFromSignal(d, Some("iocell_debug"))) - val debugPortOpt: Option[DebugIO] = optTuple.map(_._1) - val debugIOs: Seq[IOCell] = optTuple.map(_._2).toSeq.flatten + def debug(psd: PSDIO, resetctrlOpt: Option[ResetCtrlIO], debugOpt: Option[DebugIO])(implicit p: Parameters): + (PSDIO, Option[ResetCtrlIO], Option[DebugIO], Seq[IOCell]) = { + val (psdPort, psdIOs) = IOCell.generateIOFromSignal( + psd, Some("iocell_psd"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync) + val debugTuple = debugOpt.map(d => + IOCell.generateIOFromSignal(d, Some("iocell_debug"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)) + val debugPortOpt: Option[DebugIO] = debugTuple.map(_._1) + val debugIOs: Seq[IOCell] = debugTuple.map(_._2).toSeq.flatten debugPortOpt.foreach(_.suggestName("debug")) + + val resetctrlTuple = resetctrlOpt.map(d => + IOCell.generateIOFromSignal(d, Some("iocell_resetctrl"), abstractResetAsAsync = p(GlobalResetSchemeKey).pinIsAsync)) + val resetctrlPortOpt: Option[ResetCtrlIO] = resetctrlTuple.map(_._1) + val resetctrlIOs: Seq[IOCell] = resetctrlTuple.map(_._2).toSeq.flatten + resetctrlPortOpt.foreach(_.suggestName("resetctrl")) + psdPort.suggestName("psd") - (psdPort, debugPortOpt, psdIOs ++ debugIOs) + (psdPort, resetctrlPortOpt, debugPortOpt, psdIOs ++ debugIOs ++ resetctrlIOs) } /** @@ -176,29 +188,32 @@ class WithSimNIC extends OverrideIOBinder({ (system: CanHavePeripheryIceNICModuleImp) => system.connectSimNetwork(system.clock, system.reset.asBool); Nil }) +// Note: The parameters instance is accessible only through the BaseSubsystem +// or some parent class (IsAttachable, BareSubsystem -> LazyModule). The +// self-type requirement in CanHaveMasterAXI4MemPort is insufficient to make it +// accessible to the IOBinder // DOC include start: WithSimAXIMem class WithSimAXIMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPortModuleImp) => system.connectSimAXIMem(); Nil + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => SimAXIMem.connectMem(system)(system.p); Nil }) // DOC include end: WithSimAXIMem class WithBlackBoxSimMem extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPortModuleImp) => { - (system.mem_axi4 zip system.outer.memAXI4Node).foreach { case (io, node) => + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { + (system.mem_axi4 zip system.memAXI4Node.in).foreach { case (io, (_, edge)) => val memSize = system.p(ExtMem).get.master.size val lineSize = system.p(CacheBlockBytes) - (io zip node.in).foreach { case (axi4, (_, edge)) => - val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) - mem.io.axi <> axi4 - mem.io.clock := system.clock - mem.io.reset := system.reset - } - }; Nil + val mem = Module(new SimDRAM(memSize, lineSize, edge.bundle)) + mem.io.axi <> io + mem.io.clock := system.module.clock + mem.io.reset := system.module.reset + } + Nil } }) class WithSimAXIMMIO extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MMIOPortModuleImp) => system.connectSimAXIMMIO(); Nil + (system: CanHaveMasterAXI4MMIOPort with BaseSubsystem) => SimAXIMem.connectMMIO(system)(system.p); Nil }) class WithDontTouchPorts extends OverrideIOBinder({ @@ -215,7 +230,7 @@ class WithTieOffInterrupts extends OverrideIOBinder({ }) class WithTieOffL2FBusAXI extends OverrideIOBinder({ - (system: CanHaveSlaveAXI4PortModuleImp) => { + (system: CanHaveSlaveAXI4Port with BaseSubsystem) => { system.l2_frontend_bus_axi4.foreach(axi => { axi.tieoff() experimental.DataMirror.directionOf(axi.ar.ready) match { @@ -235,23 +250,28 @@ class WithTieOffL2FBusAXI extends OverrideIOBinder({ class WithTiedOffDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val (psdPort, resetctrlOpt, debugPortOpt, ioCells) = + AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { - Debug.tieoffDebug(debugPortOpt, psdPort) + Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ - debugPortOpt.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + debugPortOpt.foreach { d => + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.dmactiveAck := DontCare + } Nil } - Seq((Seq(psdPort) ++ debugPortOpt.toSeq, ioCells, Some(harnessFn))) + Seq((Seq(psdPort) ++ resetctrlOpt ++ debugPortOpt.toSeq, Nil, Some(harnessFn))) } }) class WithSimDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - val (psdPort, debugPortOpt, ioCells) = AddIOCells.debug(system.psd, system.debug) + val (psdPort, resetctrlPortOpt, debugPortOpt, ioCells) = + AddIOCells.debug(system.psd, system.resetctrl, system.debug)(system.p) val harnessFn = (th: chipyard.TestHarness) => { val dtm_success = Wire(Bool()) - Debug.connectDebug(debugPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) + Debug.connectDebug(debugPortOpt, resetctrlPortOpt, psdPort, th.clock, th.harnessReset, dtm_success)(system.p) when (dtm_success) { th.success := true.B } th.dutReset := th.harnessReset | debugPortOpt.map { debug => AsyncResetReg(debug.ndreset).asBool }.getOrElse(false.B) Nil diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 96443a9f..8fe0871b 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -52,26 +52,20 @@ trait HasChipyardTiles extends HasTiles // TODO: investigate why val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { case (param, crossing) => { - val (tile, rocketLogicalTree) = param match { + + val tile = param match { case r: RocketTileParams => { - val t = LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) - (t, t.rocketLogicalTree) + LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode)) } case b: BoomTileParams => { - val t = LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) - (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately + LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode)) } case a: ArianeTileParams => { - val t = LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) - (t, t.rocketLogicalTree) // TODO FIX rocketLogicalTree is not a member of the superclass, both child classes define it separately + LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode)) } } connectMasterPortsToSBus(tile, crossing) connectSlavePortsToCBus(tile, crossing) - - def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocketLogicalTree.getOMInterruptTargets) - LogicalModuleTree.add(logicalTreeNode, rocketLogicalTree) - connectInterrupts(tile, debugOpt, clintOpt, plicOpt) tile diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index f18a2068..6d99ca6a 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -38,8 +38,5 @@ class System(implicit p: Parameters) extends Subsystem class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) with HasRTCModuleImp with HasExtInterruptsModuleImp - with CanHaveMasterAXI4MemPortModuleImp - with CanHaveMasterAXI4MMIOPortModuleImp - with CanHaveSlaveAXI4PortModuleImp with HasPeripheryBootROMModuleImp with DontTouch diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 4aaef747..a82d3a33 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -25,9 +25,8 @@ class TestHarness(implicit val p: Parameters) extends Module { val dut = p(BuildTop)(p) io.success := false.B - // dutReset can be overridden via a harnessFunction, but by default it is just reset - val dutReset = Wire(Bool()) - dutReset := reset + // dutReset assignment can be overridden via a harnessFunction, but by default it is just reset + val dutReset = WireDefault(if (p(GlobalResetSchemeKey).pinIsAsync) reset.asAsyncReset else reset) dut.harnessFunctions.foreach(_(this)) diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 7d901c62..9fdef05a 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -5,8 +5,7 @@ import scala.collection.mutable.{LinkedHashSet} import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.config.{Parameters} -import freechips.rocketchip.util.{GeneratorApp} -import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} +import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} import boom.common.{BoomTilesKey} import ariane.{ArianeTilesKey} @@ -56,10 +55,13 @@ object RegressionTestSuites /** * Helper functions to add BOOM or Rocket tests */ -object TestSuiteHelper +class TestSuiteHelper { import freechips.rocketchip.system.DefaultTestSuites._ import RegressionTestSuites._ + val suites = collection.mutable.ListMap[String, RocketTestSuite]() + def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) } + def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) } /** * Add BOOM tests (asm, bmark, regression) @@ -72,33 +74,33 @@ object TestSuiteHelper val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) + addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) { - TestGeneration.addSuites(env.map(rv32ud)) + addSuites(env.map(rv32ud)) } } else if (cfg.fLen >= 64) { - TestGeneration.addSuites(env.map(rv64ud)) - TestGeneration.addSuites(env.map(rv64uf)) - TestGeneration.addSuite(rv32udBenchmarks) + addSuites(env.map(rv64ud)) + addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) } } if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) { - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) } else { - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) } } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites(rvu.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites(rvu.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } @@ -113,31 +115,31 @@ object TestSuiteHelper val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) + addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv32ud)) + addSuites(env.map(rv32ud)) } else { - TestGeneration.addSuite(rv32udBenchmarks) - TestGeneration.addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv64ud)) + addSuites(env.map(rv64ud)) } } if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) else - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } @@ -152,32 +154,31 @@ object TestSuiteHelper val env = if (vm) List("p","v") else List("p") coreParams.fpu foreach { case cfg => if (xlen == 32) { - TestGeneration.addSuites(env.map(rv32uf)) + addSuites(env.map(rv32uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv32ud)) + addSuites(env.map(rv32ud)) } else { - TestGeneration.addSuite(rv32udBenchmarks) - TestGeneration.addSuites(env.map(rv64uf)) + addSuite(rv32udBenchmarks) + addSuites(env.map(rv64uf)) if (cfg.fLen >= 64) - TestGeneration.addSuites(env.map(rv64ud)) + addSuites(env.map(rv64ud)) } } if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) - TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) + addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) else - TestGeneration.addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) + addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) } - if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) + if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u) - TestGeneration.addSuites(rvi.map(_("p"))) - TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) - TestGeneration.addSuite(benchmarks) - TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) + addSuites(rvi.map(_("p"))) + addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) + addSuite(benchmarks) + addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) } } - } diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala new file mode 100644 index 00000000..dfee1596 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -0,0 +1,20 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import freechips.rocketchip.stage.ConfigsAnnotation +import firrtl.options.{HasShellOptions, ShellOption} + +/** This hijacks the existing ConfigAnnotation to accept the legacy _-delimited format */ +private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptions { + override val options = Seq( + new ShellOption[String]( + longOption = "legacy-configs", + toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))), + helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", + shortOption = Some("LC") + ) + ) +} + diff --git a/generators/chipyard/src/main/scala/stage/ChipyardCli.scala b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala new file mode 100644 index 00000000..7d293c36 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardCli.scala @@ -0,0 +1,15 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import firrtl.options.Shell + +trait ChipyardCli { this: Shell => + + parser.note("Chipyard Generator Options") + Seq( + UnderscoreDelimitedConfigsAnnotation + ) + .foreach(_.addOptions(parser)) +} diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala new file mode 100644 index 00000000..a24afd43 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -0,0 +1,36 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage + +import chisel3.stage.{ChiselCli, ChiselStage} +import firrtl.options.PhaseManager.PhaseDependency +import firrtl.options.{Phase, PreservesAll, Shell} +import firrtl.stage.FirrtlCli +import freechips.rocketchip.stage.RocketChipCli +import freechips.rocketchip.system.RocketChipStage + +import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.phases.DeletedWrapper + +class ChipyardStage extends ChiselStage with PreservesAll[Phase] { + override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli + override val targets: Seq[PhaseDependency] = Seq( + classOf[freechips.rocketchip.stage.phases.Checks], + classOf[freechips.rocketchip.stage.phases.TransformAnnotations], + classOf[freechips.rocketchip.stage.phases.PreElaboration], + classOf[chisel3.stage.phases.Checks], + classOf[chisel3.stage.phases.Elaborate], + classOf[freechips.rocketchip.stage.phases.GenerateROMs], + classOf[chisel3.stage.phases.AddImplicitOutputFile], + classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + classOf[chisel3.stage.phases.MaybeAspectPhase], + classOf[chisel3.stage.phases.Emitter], + classOf[chisel3.stage.phases.Convert], + classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + classOf[freechips.rocketchip.stage.phases.AddDefaultTests], + classOf[chipyard.stage.phases.AddDefaultTests], + classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags], + classOf[freechips.rocketchip.stage.phases.GenerateArtefacts], + ) +} diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala new file mode 100644 index 00000000..277d04b5 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -0,0 +1,62 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage.phases + +import scala.util.Try +import scala.collection.mutable + +import chipsalliance.rocketchip.config.Parameters +import chisel3.stage.phases.Elaborate +import firrtl.AnnotationSeq +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{Phase, PreservesAll} +import firrtl.options.Viewer.view +import freechips.rocketchip.stage.RocketChipOptions +import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} +import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} +import freechips.rocketchip.util.HasRocketChipStageUtils + +import chipyard.TestSuiteHelper + +class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { + // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase + // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). + override val prerequisites = Seq( + classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + classOf[freechips.rocketchip.stage.phases.AddDefaultTests]) + override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) + + private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { + val annotations = mutable.ArrayBuffer[Annotation]() + val suiteHelper = new TestSuiteHelper + suiteHelper.addRocketTestSuites + suiteHelper.addBoomTestSuites + suiteHelper.addArianeTestSuites + + // if hwacha parameter exists then generate its tests + // TODO: find a more elegant way to do this. either through + // trying to disambiguate BuildRoCC, having a AccelParamsKey, + // or having the Accelerator/Tile add its own tests + import hwacha.HwachaTestSuites._ + if (Try(p(hwacha.HwachaNLanes)).getOrElse(0) > 0) { + suiteHelper.addSuites(rv64uv.map(_("p"))) + suiteHelper.addSuites(rv64uv.map(_("vp"))) + suiteHelper.addSuite(rv64sv("p")) + suiteHelper.addSuite(hwachaBmarks) + annotations += CustomMakefragSnippet( + "SRC_EXTENSION = $(base_dir)/hwacha/$(src_path)/*.scala" + "\nDISASM_EXTENSION = --extension=hwacha") + } + RocketTestSuiteAnnotation(suiteHelper.suites.values.toSeq) +: annotations + } + + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val (testSuiteAnnos, oAnnos) = annotations.partition { + case RocketTestSuiteAnnotation(_) => true + case o => false + } + implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance + addTestSuiteAnnotations ++ oAnnos + } +} diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala new file mode 100644 index 00000000..76f99ab7 --- /dev/null +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -0,0 +1,49 @@ +// See LICENSE for license details. +// Based on Rocket Chip's stage implementation + +package chipyard.stage.phases + +import scala.collection.mutable + +import firrtl.AnnotationSeq +import firrtl.annotations.{Annotation, NoTargetAnnotation} +import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable} +import firrtl.options.Viewer.view +import freechips.rocketchip.stage.RocketChipOptions +import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} +import freechips.rocketchip.system.TestGeneration +import freechips.rocketchip.util.HasRocketChipStageUtils + +trait MakefragSnippet { self: Annotation => + def toMakefrag: String +} + +case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable + +/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */ +class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { + + // Our annotations tend not to be serializable, but are not marked as such. + override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + classOf[chipyard.stage.phases.AddDefaultTests]) + + override def transform(annotations: AnnotationSeq): AnnotationSeq = { + val targetDir = view[StageOptions](annotations).targetDir + val fileName = s"${view[RocketChipOptions](annotations).longName.get}.d" + + val makefragBuilder = new mutable.StringBuilder() + val outputAnnotations = annotations.flatMap { + case RocketTestSuiteAnnotation(tests) => + // Unfortunately the gen method of TestGeneration is rocketchip package + // private, so we either have to copy code in or use the stateful form + TestGeneration.addSuites(tests) + None + case a: MakefragSnippet => + makefragBuilder :+ ("\n" + a.toMakefrag) + None + case a => Some(a) + } + writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString) + outputAnnotations + } +} diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bd19ee98..043f1f4e 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -8,7 +8,7 @@ import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp, HasExtInterruptsModuleImp} +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem} import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} @@ -56,19 +56,17 @@ class WithBlockDeviceBridge extends OverrideIOBinder({ class WithFASEDBridge extends OverrideIOBinder({ - (system: CanHaveMasterAXI4MemPortModuleImp) => { + (system: CanHaveMasterAXI4MemPort with BaseSubsystem) => { implicit val p = system.p - (system.mem_axi4 zip system.outer.memAXI4Node).flatMap({ case (io, node) => - (io zip node.in).map({ case (axi4Bundle, (_, edge)) => - val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, - axi4Bundle.ar.bits.addr.getWidth, - axi4Bundle.ar.bits.id.getWidth) - FASEDBridge(system.clock, axi4Bundle, system.reset.toBool, - CompleteConfig(p(firesim.configs.MemModelKey), - nastiKey, - Some(AXI4EdgeSummary(edge)), - Some(MainMemoryConsts.globalName))) - }) + (system.mem_axi4 zip system.memAXI4Node.in).foreach({ case (axi4, (_, edge)) => + val nastiKey = NastiParameters(axi4.r.bits.data.getWidth, + axi4.ar.bits.addr.getWidth, + axi4.ar.bits.id.getWidth) + FASEDBridge(system.module.clock, axi4, system.module.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), + nastiKey, + Some(AXI4EdgeSummary(edge)), + Some(MainMemoryConsts.globalName))) }) Nil } @@ -116,9 +114,12 @@ class WithTiedOffSystemGPIO extends OverrideIOBinder({ class WithTiedOffSystemDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { - Debug.tieoffDebug(system.debug, system.psd) + Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) // tieoffDebug doesn't actually tie everything off :/ - system.debug.foreach(_.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })) + system.debug.foreach { d => + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.dmactiveAck := DontCare + } Nil } }) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index fc65f136..923e1cd1 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -34,14 +34,24 @@ class FireSim(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(clock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) + val targets = Seq.fill(p(NumNodes)) { + // It's not a RC bump without some hacks... + // Copy the AsyncClockGroupsKey to generate a fresh node on each + // instantiation of the dut, otherwise the initial instance will be + // reused across each node + import freechips.rocketchip.subsystem.AsyncClockGroupsKey + val lazyModule = p(BuildSystem)(p.alterPartial({ + case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy + })) + (lazyModule, Module(lazyModule.module)) + } val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only - // if that Mixin trait is present in the target's class instance + // if that Mixin trait is present in the target's LazyModule class instance // // Apply each partial function to each DUT instance - for ((target) <- targets) { - p(IOBinders).values.map(_(target)) + for ((lazyModule, module) <- targets) { + p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module)) NodeIdx.increment() } } diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index b16f99c7..fdc2939f 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -64,7 +64,7 @@ class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config class HalfRateUncore extends WithSingleRationalTileDomain(2,1) class WithFiresimMulticlockTop extends Config((site, here, up) => { - case BuildSystem => (p: Parameters) => Module(LazyModule(new FiresimMulticlockTop()(p)).suggestName("system").module) + case BuildSystem => (p: Parameters) => LazyModule(new FiresimMulticlockTop()(p)).suggestName("system") }) // Complete Config @@ -88,16 +88,19 @@ class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { val reset = WireInit(false.B) withClockAndReset(refClock, reset) { // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(p(BuildSystem)(p)) + val targets = Seq.fill(p(NumNodes)) { + val lazyModule = p(BuildSystem)(p) + (lazyModule, Module(lazyModule.module)) + } val peekPokeBridge = PeekPokeBridge(refClock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's class instance // // Apply each partial function to each DUT instance - for ((target) <- targets) { - p(IOBinders).values.map(_(target)) + for ((lazyModule, module) <- targets) { + p(IOBinders).values.foreach(f => f(lazyModule) ++ f(module)) } - targets.collect({ case t: HasAdditionalClocks => t.clocks := clockBridge.io.clocks }) + targets.collect({ case (_, t: HasAdditionalClocks) => t.clocks := clockBridge.io.clocks }) } } diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 18aeefc8..852b9fbd 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -9,7 +9,7 @@ import chisel3.internal.firrtl.{Circuit, Port} import freechips.rocketchip.diplomacy.{ValName, AutoBundle} import freechips.rocketchip.devices.debug.DebugIO -import freechips.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} +import midas.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} import freechips.rocketchip.system.DefaultTestSuites._ import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} import freechips.rocketchip.config.Parameters @@ -24,9 +24,11 @@ import chipyard.TestSuiteHelper trait HasTestSuites { def addTestSuites(targetName: String, params: Parameters) { - TestSuiteHelper.addRocketTestSuites(params) - TestSuiteHelper.addBoomTestSuites(params) - TestSuiteHelper.addArianeTestSuites(params) + val suiteHelper = new TestSuiteHelper + suiteHelper.addRocketTestSuites(params) + suiteHelper.addBoomTestSuites(params) + suiteHelper.addArianeTestSuites(params) + TestGeneration.addSuites(suiteHelper.suites.values.toSeq) TestGeneration.addSuite(FastBlockdevTests) TestGeneration.addSuite(SlowBlockdevTests) if (!targetName.contains("NoNIC")) @@ -47,7 +49,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu /** Output software test Makefrags, which provide targets for integration testing. */ def generateTestSuiteMakefrags { addTestSuites(names.topModuleClass, targetParams) - writeOutputFile(s"$longName.d", TestGeneration.generateMakefrag) // Subsystem-specific test suites + writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites } // Output miscellaneous files produced as a side-effect of elaboration @@ -68,12 +70,3 @@ object FireSimGenerator extends App with IsFireSimGeneratorLike { generateTestSuiteMakefrags generateArtefacts } - -// For now, provide a separate generator app when not specifically building for FireSim -object Generator extends freechips.rocketchip.util.GeneratorApp with HasTestSuites { - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - generateFirrtl - generateAnno - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 04d9a8f6..63199c0e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -41,7 +41,7 @@ class WithBootROM extends Config((site, here, up) => { }) class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => { - case PeripheryBusKey => up(PeripheryBusKey).copy(frequency=freq) + case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) }) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 83d57e24..68797432 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -137,7 +137,7 @@ abstract class FireSimTestSuite( } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") -class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } diff --git a/generators/hwacha b/generators/hwacha index ef5e5196..2706502d 160000 --- a/generators/hwacha +++ b/generators/hwacha @@ -1 +1 @@ -Subproject commit ef5e5196b685536890396a08a9f5024eb8b7928e +Subproject commit 2706502daf862c9a7a39126eb7e7209eaf984f76 diff --git a/generators/icenet b/generators/icenet index b1f957e6..4522a397 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit b1f957e6eb022c662f0fb33c7ddfbddc686bfde5 +Subproject commit 4522a3979be092c4221f186bdd93bf330fdca134 diff --git a/generators/rocket-chip b/generators/rocket-chip index 4f0cdea8..9b1907ea 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 4f0cdea85c8a2b849fd582ccc8497892001d06b0 +Subproject commit 9b1907eacbeb268d47e204e3de1818823d605ba4 diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 1bc0ef18..3e35a94d 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 1bc0ef18d6653f1133cb9293e8ee8620f9417c78 +Subproject commit 3e35a94d46d88506d5b14b2c34f05b8651844452 diff --git a/generators/testchipip b/generators/testchipip index d06d7c7d..b8d6f210 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit d06d7c7dc274420a5fc5600ba8bdb2003cc9b0cd +Subproject commit b8d6f2101947e9f80f896dbaa5802946e2a3b9f0 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index 18307678..cb5d0af8 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -49,4 +49,3 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem class TraceGenSystemModuleImp(outer: TraceGenSystem) extends BaseSubsystemModuleImp(outer) with HasTraceGenTilesModuleImp - with CanHaveMasterAXI4MemPortModuleImp diff --git a/project/build.properties b/project/build.properties index c0bab049..8522443d 100644 --- a/project/build.properties +++ b/project/build.properties @@ -1 +1 @@ -sbt.version=1.2.8 +sbt.version=1.3.2 diff --git a/project/plugins.sbt b/project/plugins.sbt index 3321d801..a30249c9 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -14,5 +14,6 @@ addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6") addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") +addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" diff --git a/sims/firesim b/sims/firesim index 7c121894..f82e115c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 7c121894e97f32b2fdaf719673c2a2f2ecbe5312 +Subproject commit f82e115c6641c5fe33f756abeb8093f64b0d0a80 diff --git a/tools/barstools b/tools/barstools index db677636..e230e8cf 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit db6776367c7a8f4850266d72f81cd4c90561731a +Subproject commit e230e8cf3f7c0bc3c958cab22c5d90d195ca6b01 diff --git a/tools/chisel3 b/tools/chisel3 index d1a61262..7a343dce 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit d1a61262630b5ea77ebe21a453df9645cb7e4185 +Subproject commit 7a343dce95a370f6cb7b9cf80e0694ac82dc94f8 diff --git a/tools/firrtl b/tools/firrtl index f738fbe8..eb637777 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit f738fbe8667ed6b76ec00a15960b9c3a42b8654a +Subproject commit eb637777e3c4d77435cfd13358c521ed1b766ba8 diff --git a/variables.mk b/variables.mk index 4953c968..c851cccf 100644 --- a/variables.mk +++ b/variables.mk @@ -38,43 +38,18 @@ ifeq ($(SUB_PROJECT),chipyard) TB ?= TestDriver TOP ?= ChipTop endif -# for Rocket-chip developers -ifeq ($(SUB_PROJECT),rocketchip) - SBT_PROJECT ?= rocketchip - MODEL ?= TestHarness - VLOG_MODEL ?= TestHarness - MODEL_PACKAGE ?= freechips.rocketchip.system - CONFIG ?= DefaultConfig - CONFIG_PACKAGE ?= freechips.rocketchip.system - GENERATOR_PACKAGE ?= freechips.rocketchip.system - TB ?= TestDriver - TOP ?= ExampleRocketSystem -endif # for Hwacha developers ifeq ($(SUB_PROJECT),hwacha) - SBT_PROJECT ?= hwacha + SBT_PROJECT ?= chipyard MODEL ?= TestHarness VLOG_MODEL ?= TestHarness MODEL_PACKAGE ?= freechips.rocketchip.system CONFIG ?= HwachaConfig CONFIG_PACKAGE ?= hwacha - GENERATOR_PACKAGE ?= hwacha + GENERATOR_PACKAGE ?= chipyard TB ?= TestDriver TOP ?= ExampleRocketSystem endif -# Stand-in firechip variables: -# TODO: need a seperate generator and test harnesses for each target -#ifeq ($(SUB_PROJECT),firechip) -# SBT_PROJECT ?= $(SUB_PROJECT) -# MODEL ?= TestHarness -# VLOG_MODEL ?= TestHarness -# MODEL_PACKAGE ?= freechips.rocketchip.system -# CONFIG ?= FireSimRocketChipConfig -# CONFIG_PACKAGE ?= firesim.firesim -# GENERATOR_PACKAGE ?= firesim.firesim -# TB ?= TestDriver -# TOP ?= FireSimNoNIC -#endif ######################################################################################### # path to rocket-chip and testchipip @@ -87,11 +62,6 @@ CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl # names of various files needed to compile and run things ######################################################################################### long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG) - -# match the long_name to what the specific generator will output -ifeq ($(GENERATOR_PACKAGE),freechips.rocketchip.system) - long_name=$(CONFIG_PACKAGE).$(CONFIG) -endif ifeq ($(GENERATOR_PACKAGE),hwacha) long_name=$(MODEL_PACKAGE).$(CONFIG) endif From 0035154168816b4f8d29a87096e740792cfe4175 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 18 Apr 2020 17:09:31 -0700 Subject: [PATCH 077/139] [ci] bypass approval button on dev/master (#519) --- .circleci/config.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index f7bcb507..74a86405 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -358,6 +358,11 @@ workflows: build-and-test-chipyard-integration: jobs: - ci-approval: + filters: + branches: + ignore: + - master + - dev type: approval # Make the toolchains From 8469ce62e1706db102a18b7fa22656a0c506128e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 18 Apr 2020 17:11:13 -0700 Subject: [PATCH 078/139] Revert "[ci] bypass approval button on dev/master (#519)" (#520) This reverts commit 0035154168816b4f8d29a87096e740792cfe4175. --- .circleci/config.yml | 5 ----- 1 file changed, 5 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 74a86405..f7bcb507 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -358,11 +358,6 @@ workflows: build-and-test-chipyard-integration: jobs: - ci-approval: - filters: - branches: - ignore: - - master - - dev type: approval # Make the toolchains From e98ebec30dceec690e13cbb27ee28e217558016f Mon Sep 17 00:00:00 2001 From: KlepD-SAL <61977269+KlepD-SAL@users.noreply.github.com> Date: Mon, 20 Apr 2020 20:47:59 +0200 Subject: [PATCH 079/139] Added note about resource usage during elaboration to docs (#517) On computers with limited resources (like main memory) the elaboration will fail with the message 'make: *** [firrtl_temp] Error 137'. Since no further explaination of the error is given, its meaning should be mentioned in the docs. --- docs/Simulation/Software-RTL-Simulation.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 957913e9..bdafd60f 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -49,6 +49,8 @@ Simulating The Default Example To compile the example design, run ``make`` in the selected verilator or VCS directory. This will elaborate the ``RocketConfig`` in the example project. +.. Note:: The elaboration of ``RocketConfig`` requires about 6.5 GB of main memory. Otherwise the process will fail with ``make: *** [firrtl_temp] Error 137`` which is most likely related to limited resources. Other configurations might require even more main memory. + An executable called ``simulator-chipyard-RocketConfig`` will be produced. This executable is a simulator that has been compiled based on the design that was built. You can then use this executable to run any compatible RV64 code. From 7b6a45a6a8aaa88faf08f4f8e18ad9bbd7743d7f Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 20 Apr 2020 17:08:15 -0700 Subject: [PATCH 080/139] [ci] remove approval button for ci jobs (#521) --- .circleci/config.yml | 27 ++++++--------------------- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index f7bcb507..d91e7115 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -357,35 +357,20 @@ workflows: build-and-test-chipyard-integration: jobs: - - ci-approval: - type: approval - # Make the toolchains - - install-riscv-toolchain: - requires: - - ci-approval + - install-riscv-toolchain - - install-esp-toolchain: - requires: - - ci-approval + - install-esp-toolchain - - install-verilator: - requires: - - ci-approval + - install-verilator - - commit-on-master-check: - requires: - - ci-approval + - commit-on-master-check # Attempt to apply the tutorial patches - - tutorial-setup-check: - requires: - - ci-approval + - tutorial-setup-check # Check that documentation builds - - documentation-check: - requires: - - ci-approval + - documentation-check # Build extra tests - build-extra-tests: From a67461df7a37354e37d973f2738c797039123916 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 23 Apr 2020 16:29:36 -0700 Subject: [PATCH 081/139] [SBT] Quiet down jgit http warnings --- project/plugins.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/plugins.sbt b/project/plugins.sbt index a30249c9..d8d00e35 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,6 +1,6 @@ resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) resolvers += Classpaths.sbtPluginReleases -resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven" +resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2") addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2") From eeafc82d12c98111a2409f6f8d13fdd81e1a18e4 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 23 Apr 2020 16:28:56 -0700 Subject: [PATCH 082/139] Remove ++ per Jack's recommendation --- variables.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variables.mk b/variables.mk index c851cccf..80e10a0c 100644 --- a/variables.mk +++ b/variables.mk @@ -102,7 +102,7 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M SCALA_VERSION=2.12.10 SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) -SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ++$(SCALA_VERSION) +SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar ######################################################################################### # output directory for tests From 9d15f2e4e988be3fa18d9af13b5899070583b28f Mon Sep 17 00:00:00 2001 From: Matthias-Raudonis <33962683+Matthias-Raudonis@users.noreply.github.com> Date: Fri, 24 Apr 2020 19:10:31 +0200 Subject: [PATCH 083/139] Include scripts for dependencies in documentation (#518) --- docs/index.rst | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/docs/index.rst b/docs/index.rst index debfaf99..855929cd 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -37,6 +37,20 @@ Start by fetching Chipyard's sources. Run: This will initialize and checkout all of the necessary git submodules. +Installing Dependencies +------------------------------------------- +Installing the recommended dependencies on Ubuntu/Debian-based platforms: + +.. code-block:: shell + + ./scripts/ubuntu-req.sh + +Installing the recommended dependencies on CentOS-based platforms: + +.. code-block:: shell + + ./scripts/centos-req.sh + Installing the RISC-V Tools ------------------------------------------- From f30daa406319d1761b1c5bb8cb6428c49fefd2b2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 24 Apr 2020 13:33:30 -0700 Subject: [PATCH 084/139] [ci] Lengthen hetero tests timeout --- .circleci/config.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index d91e7115..97a27e7a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -279,6 +279,7 @@ jobs: steps: - run-tests: project-key: "chipyard-hetero" + timeout: "15m" chipyard-boom-run-tests: executor: main-env steps: From b26ed91b7364d79c903f84832539fcda001e371b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 24 Apr 2020 13:35:23 -0700 Subject: [PATCH 085/139] [CI] Convert FireSim tests to use ScalaTest --- .circleci/config.yml | 49 ++++++++----------- .circleci/defaults.sh | 8 +-- ...im-build.sh => run-firesim-scala-tests.sh} | 29 ++--------- .circleci/run-firesim-tests.sh | 29 ----------- generators/ariane | 2 +- .../src/test/scala/ScalaTestSuite.scala | 3 ++ sims/firesim | 2 +- 7 files changed, 35 insertions(+), 87 deletions(-) rename .circleci/{do-firesim-build.sh => run-firesim-scala-tests.sh} (60%) delete mode 100755 .circleci/run-firesim-tests.sh diff --git a/.circleci/config.yml b/.circleci/config.yml index 97a27e7a..801c3b85 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -247,18 +247,6 @@ jobs: steps: - prepare-rtl: project-key: "tracegen-boom" - prepare-firesim: - executor: main-env - steps: - - prepare-rtl: - project-key: "firesim" - build-script: "do-firesim-build.sh" - prepare-fireboom: - executor: main-env - steps: - - prepare-rtl: - project-key: "fireboom" - build-script: "do-firesim-build.sh" prepare-chipyard-ariane: executor: main-env steps: @@ -318,15 +306,24 @@ jobs: - run-tests: extra-cache-restore: "extra-tests" project-key: "firesim" - run-script: "run-firesim-tests.sh" + run-script: "run-firesim-scala-tests.sh" + timeout: "20m" fireboom-run-tests: executor: main-env steps: - run-tests: extra-cache-restore: "extra-tests" project-key: "fireboom" - run-script: "run-firesim-tests.sh" - timeout: "30m" + run-script: "run-firesim-scala-tests.sh" + timeout: "45m" + firesim-multiclock-run-tests: + executor: main-env + steps: + - run-tests: + extra-cache-restore: "extra-tests" + project-key: "firesim-multiclock" + run-script: "run-firesim-scala-tests.sh" + timeout: "20m" midasexamples-run-tests: executor: main-env steps: @@ -429,16 +426,6 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-firesim: - requires: - - install-riscv-toolchain - - install-verilator - - - prepare-fireboom: - requires: - - install-riscv-toolchain - - install-verilator - - prepare-chipyard-ariane: requires: - install-riscv-toolchain @@ -491,12 +478,18 @@ workflows: # Run the firesim tests - firesim-run-tests: requires: - - prepare-firesim + - install-riscv-toolchain + - install-verilator + - build-extra-tests + - firesim-multiclock-run-tests: + requires: + - install-riscv-toolchain + - install-verilator - build-extra-tests - - fireboom-run-tests: requires: - - prepare-fireboom + - install-riscv-toolchain + - install-verilator - build-extra-tests - chipyard-ariane-run-tests: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 7d4fdaa3..f1be9e05 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -50,9 +50,9 @@ mapping["chipyard-boom"]="SUB_PROJECT=chipyard CONFIG=SmallBoomConfig" mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConfig" mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" +mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig PLATFORM_CONFIG=BaseF1Config" -mapping["fireboom"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig PLATFORM_CONFIG=BaseF1Config" -mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" -mapping["fireariane"]="DESIGN=FireSim TARGET_CONFIG=WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig PLATFORM_CONFIG=BaseF1Config" +mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" +mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" +mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" diff --git a/.circleci/do-firesim-build.sh b/.circleci/run-firesim-scala-tests.sh similarity index 60% rename from .circleci/do-firesim-build.sh rename to .circleci/run-firesim-scala-tests.sh index 7d86c779..93c4561d 100755 --- a/.circleci/do-firesim-build.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -22,7 +22,6 @@ cd $LOCAL_CHIPYARD_DIR/sims/firesim ./scripts/build-libdwarf.sh cd $LOCAL_CHIPYARD_DIR - # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" @@ -30,7 +29,9 @@ clean # copy over riscv/esp-tools, and chipyard to remote run "mkdir -p $REMOTE_CHIPYARD_DIR" +run "mkdir -p $REMOTE_RISCV_DIR" copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR +copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" run "cp -r ~/.sbt $REMOTE_WORK_DIR" @@ -38,31 +39,11 @@ run "cp -r ~/.sbt $REMOTE_WORK_DIR" TOOLS_DIR=$REMOTE_RISCV_DIR LD_LIB_DIR=$REMOTE_RISCV_DIR/lib -if [ $1 = "hwacha" ] || [ $1 = "gemmini" ]; then - TOOLS_DIR=$REMOTE_ESP_DIR - LD_LIB_DIR=$REMOTE_ESP_DIR/lib - run "mkdir -p $REMOTE_ESP_DIR" - copy $LOCAL_ESP_DIR/ $SERVER:$REMOTE_ESP_DIR -else - run "mkdir -p $REMOTE_RISCV_DIR" - copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR -fi -# Build MIDAS-level verilator sim -FIRESIM_VARS="${mapping[$1]}" -run "export FIRESIM_ENV_SOURCED=1; make -C $REMOTE_FIRESIM_DIR clean" +# Run Firesim Scala Tests run "export RISCV=\"$TOOLS_DIR\"; \ export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export FIRESIM_ENV_SOURCED=1; \ export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \ - export FIRESIM_ENV_SOURCED=1; \ - make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" $FIRESIM_VARS verilator" -run "rm -rf $REMOTE_CHIPYARD_DIR/project" - -# copy back the final build -mkdir -p $LOCAL_CHIPYARD_DIR -copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR - -# Fix dramsim2_ini symlink -export $FIRESIM_VARS -ln -sf $LOCAL_FIRESIM_DIR/midas/src/main/resources/dramsim2_ini $LOCAL_FIRESIM_DIR/generated-src/f1/${DESIGN}-${TARGET_CONFIG}-${PLATFORM_CONFIG}/dramsim2_ini + make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}" diff --git a/.circleci/run-firesim-tests.sh b/.circleci/run-firesim-tests.sh deleted file mode 100755 index d1111e60..00000000 --- a/.circleci/run-firesim-tests.sh +++ /dev/null @@ -1,29 +0,0 @@ -#!/bin/bash - -# turn echo on and error on earliest command -set -ex - -# get remote exec variables -SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" -source $SCRIPT_DIR/defaults.sh - -export FIRESIM_ENV_SOURCED=1 - -SIMULATION_ARGS="${mapping[$1]}" - -cd $LOCAL_CHIPYARD_DIR/sims/firesim -./scripts/build-libelf.sh -./scripts/build-libdwarf.sh -cd $LOCAL_CHIPYARD_DIR - - -run_test_suite () { - export RISCV=$LOCAL_RISCV_DIR - export LD_LIBRARY_PATH=$LOCAL_RISCV_DIR/lib - make -C $LOCAL_FIRESIM_DIR $SIMULATION_ARGS run-${1}-tests-fast -} - - -run_test_suite bmark -run_test_suite nic -run_test_suite blockdev diff --git a/generators/ariane b/generators/ariane index 621201b1..f4ba64a6 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 621201b1d5a929ab0e89f1a857b76a33e7e2e8a8 +Subproject commit f4ba64a624091600e9d7d40c293b8d5c17f47c56 diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 68797432..c5af5cda 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -141,6 +141,9 @@ class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimL class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } +class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { + runSuite("verilator")(NICLoopbackTests) +} // Disabled until RAM optimizations re-enabled in multiclock //class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") //class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") diff --git a/sims/firesim b/sims/firesim index f82e115c..d5d4f4d6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit f82e115c6641c5fe33f756abeb8093f64b0d0a80 +Subproject commit d5d4f4d6f8cf5a499fee5365eec9eec794bbd08c From 462f4d0f315baca7c9a13b57381c35acb83e7482 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 25 Apr 2020 11:28:21 -0700 Subject: [PATCH 086/139] [CI] Disable SBT supershell --- .circleci/defaults.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index f1be9e05..9dfff4d5 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -30,7 +30,8 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim -REMOTE_JAVA_ARGS="-Xmx8G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" +# Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI +REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-verilator-install # local variables (aka within the docker container) From e22ff880e295eb43f6a4eebf1b3f52165216e22e Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Mon, 27 Apr 2020 20:27:36 -0700 Subject: [PATCH 087/139] [firesim] generate rocket-chip based artefacts (#534) --- generators/firechip/src/main/scala/Generator.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 852b9fbd..01747bb3 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -9,7 +9,7 @@ import chisel3.internal.firrtl.{Circuit, Port} import freechips.rocketchip.diplomacy.{ValName, AutoBundle} import freechips.rocketchip.devices.debug.DebugIO -import midas.rocketchip.util.{HasGeneratorUtilities, ParsedInputNames, ElaborationArtefacts} +import freechips.rocketchip.util.{ElaborationArtefacts} import freechips.rocketchip.system.DefaultTestSuites._ import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} import freechips.rocketchip.config.Parameters @@ -54,6 +54,7 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu // Output miscellaneous files produced as a side-effect of elaboration def generateArtefacts { + // generate RC's artefacts ElaborationArtefacts.files.foreach { case (extension, contents) => writeOutputFile(s"${longName}.${extension}", contents ()) } From b813caf6fd08d294dc73bd98a39097aebaaff5d4 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 22 Apr 2020 19:58:24 -0700 Subject: [PATCH 088/139] get icenet and testchipip unit tests working --- .../src/main/scala/unittest/TestHarness.scala | 9 +++++++ .../main/scala/unittest/UnitTestSuite.scala | 8 +++++++ generators/icenet | 2 +- generators/testchipip | 2 +- sims/vcs/Makefile | 2 +- variables.mk | 24 +++++++++++++++++++ 6 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 generators/chipyard/src/main/scala/unittest/TestHarness.scala create mode 100644 generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala diff --git a/generators/chipyard/src/main/scala/unittest/TestHarness.scala b/generators/chipyard/src/main/scala/unittest/TestHarness.scala new file mode 100644 index 00000000..8bb4bbd9 --- /dev/null +++ b/generators/chipyard/src/main/scala/unittest/TestHarness.scala @@ -0,0 +1,9 @@ +package chipyard.unittest + +import chisel3._ +import freechips.rocketchip.config.Parameters + +class TestHarness(implicit val p: Parameters) extends Module { + val io = IO(new Bundle { val success = Output(Bool()) }) + io.success := Module(new UnitTestSuite).io.finished +} diff --git a/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala new file mode 100644 index 00000000..40e991a2 --- /dev/null +++ b/generators/chipyard/src/main/scala/unittest/UnitTestSuite.scala @@ -0,0 +1,8 @@ +package chipyard.unittest + +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.util.{ElaborationArtefacts, PlusArgArtefacts} + +class UnitTestSuite(implicit p: Parameters) extends freechips.rocketchip.unittest.UnitTestSuite { + ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader) +} diff --git a/generators/icenet b/generators/icenet index 4522a397..705ca506 160000 --- a/generators/icenet +++ b/generators/icenet @@ -1 +1 @@ -Subproject commit 4522a3979be092c4221f186bdd93bf330fdca134 +Subproject commit 705ca50690383aa589dc560a5e7c152af04c46ad diff --git a/generators/testchipip b/generators/testchipip index b8d6f210..ba705408 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit b8d6f2101947e9f80f896dbaa5802946e2a3b9f0 +Subproject commit ba705408fa707d8e4e132fabd59dacb9eb12e985 diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 659d1fc0..c00819c2 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -56,7 +56,7 @@ VCS_CC_OPTS = \ VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ -error=PCWM-L \ - -timescale=1ns/10ps \ + -timescale=1ns/1ps \ -quiet \ -q \ +rad \ diff --git a/variables.mk b/variables.mk index 80e10a0c..ad981245 100644 --- a/variables.mk +++ b/variables.mk @@ -50,6 +50,30 @@ ifeq ($(SUB_PROJECT),hwacha) TB ?= TestDriver TOP ?= ExampleRocketSystem endif +# For TestChipIP developers +ifeq ($(SUB_PROJECT),testchipip) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= TestChipUnitTestConfig + CONFIG_PACKAGE ?= testchipip + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif +# For IceNet developers +ifeq ($(SUB_PROJECT),icenet) + SBT_PROJECT ?= chipyard + MODEL ?= TestHarness + VLOG_MODEL ?= TestHarness + MODEL_PACKAGE ?= chipyard.unittest + CONFIG ?= IceNetUnitTestConfig + CONFIG_PACKAGE ?= icenet + GENERATOR_PACKAGE ?= chipyard + TB ?= TestDriver + TOP ?= UnitTestSuite +endif ######################################################################################### # path to rocket-chip and testchipip From a905dbedcc5d85bfec60c01c7ae934ef9f2f5e75 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 24 Apr 2020 17:08:58 -0700 Subject: [PATCH 089/139] add make rules for running simulator without executable --- common.mk | 14 ++++++++++++++ sims/vcs/Makefile | 4 ++++ sims/verilator/Makefile | 6 ++++++ 3 files changed, 24 insertions(+) diff --git a/common.mk b/common.mk index 696e0f83..b5a5bb07 100644 --- a/common.mk +++ b/common.mk @@ -136,6 +136,12 @@ run-binary-debug: $(sim_debug) run-fast: run-asm-tests-fast run-bmark-tests-fast +run-none: $(output_dir)/none.out + +run-none-fast: $(output_dir)/none.run + +run-none-debug: $(output_dir)/none.vpd + ######################################################################################### # run assembly/benchmarks rules ######################################################################################### @@ -149,6 +155,14 @@ $(output_dir)/%.run: $(output_dir)/% $(sim) $(output_dir)/%.out: $(output_dir)/% $(sim) (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $<.log) +$(output_dir)/none.run: $(sim) + mkdir -p $(output_dir) + (set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< >(spike-dasm > $@) | tee $(output_dir)/none.log) + ######################################################################################### # include build/project specific makefrags made from the generator ######################################################################################### diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index c00819c2..f5b7e5db 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -102,6 +102,10 @@ $(sim_debug): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) +vcdplusfile=$@ $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### # general cleanup rule ######################################################################################### diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 0ab0016c..432169d6 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -145,6 +145,12 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) vcd2vpd $@.vcd $@ > /dev/null & (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) +$(output_dir)/none.vpd: $(sim_debug) + mkdir -p $(output_dir) + rm -f $@.vcd && mkfifo $@.vcd + vcd2vpd $@.vcd $@ > /dev/null & + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) none >(spike-dasm > $(output_dir)/none.out) | tee $(output_dir)/none.log) + ######################################################################################### # general cleanup rule ######################################################################################### From 8df43203a2bff518f0225507bfbe6fc73bad5bf4 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 24 Apr 2020 17:09:05 -0700 Subject: [PATCH 090/139] separate testchipip ClockUtilTests and TestChipUnitTests --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index ba705408..cec2c0b6 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ba705408fa707d8e4e132fabd59dacb9eb12e985 +Subproject commit cec2c0b6d66c3df05d08462167bb8a58c0912d06 From 94628e78b2b2bf7aaa296481d5a63809af065d9f Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Fri, 24 Apr 2020 17:15:15 -0700 Subject: [PATCH 091/139] add icenet and testchipip unit tests to CI --- .circleci/config.yml | 40 ++++++++++++++++++++++++++++++++++++++++ .circleci/defaults.sh | 2 ++ .circleci/run-tests.sh | 6 ++++++ 3 files changed, 48 insertions(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index 801c3b85..ff691e41 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -252,6 +252,16 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" + prepare-icenet: + executor: main-env + steps: + - prepare-rtl: + project-key: "icenet" + prepare-testchipip: + executor: main-env + steps: + - prepare-rtl: + project-key: "testchipip" chipyard-rocket-run-tests: executor: main-env steps: @@ -337,6 +347,18 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" + icenet-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "icenet" + timeout: "30m" + testchipip-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "testchipip" + timeout: "30m" # Order and dependencies of jobs to run workflows: @@ -431,6 +453,16 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-icenet: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-testchipip: + requires: + - install-riscv-toolchain + - install-verilator + # Run the respective tests # Run midasexamples test @@ -495,3 +527,11 @@ workflows: - chipyard-ariane-run-tests: requires: - prepare-chipyard-ariane + + - icenet-run-tests: + requires: + - prepare-icenet + + - testchipip-run-tests: + requires: + - prepare-testchipip diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 9dfff4d5..38da902b 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -57,3 +57,5 @@ mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=Tra mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" +mapping["icenet"]="SUB_PROJECT=icenet" +mapping["testchipip"]="SUB_PROJECT=testchipip" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 480908c9..5f305617 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -71,6 +71,12 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + icenet) + make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} + ;; + testchipip) + make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} + ;; *) echo "No set of tests for $1. Did you spell it right?" exit 1 From 24fada1d9ca4dc8cad7900676ab7b6ebf5c138b8 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 29 Apr 2020 01:24:25 -0700 Subject: [PATCH 092/139] Add WithNoUART fragment (#536) --- generators/chipyard/src/main/scala/ConfigFragments.scala | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index dee1a40a..e1a047dc 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -53,7 +53,11 @@ class WithUART extends Config((site, here, up) => { }) class WithNoGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Seq() + case PeripheryGPIOKey => Nil +}) + +class WithNoUART extends Config((site, here, up) => { + case PeripheryUARTKey => Nil }) class WithL2TLBs(entries: Int) extends Config((site, here, up) => { From 02367022b048500128a3aaefb5c1d64ac7b61ad4 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Wed, 29 Apr 2020 16:25:02 -0700 Subject: [PATCH 093/139] Fix "WithHeterCoresSetup" in hetero. docs (#537) --- docs/Customization/Heterogeneous-SoCs.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index 765a1afe..fd1a6880 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -40,13 +40,13 @@ The config fragment to add to your system would look something like the followin val boomTile1 = BoomTileParams(...) // params for boom core 1 val boomTile2 = BoomTileParams(...) // params for boom core 2 val boomTile3 = BoomTileParams(...) // params for boom core 3 - boomTile0 ++ boomTile1 ++ boomTile2 ++ boomTile3 + Seq(boomTile0, boomTile1, boomTile2, boomTile3) } case RocketTilesKey => { val rocketTile0 = RocketTileParams(...) // params for rocket core 0 val rocketTile1 = RocketTileParams(...) // params for rocket core 1 - rocketTile0 ++ rocketTile1 + Seq(rocketTile0, rocketTile1) } }) From 658e92e951d2368d60c1ed5a2a4f61e7e3b6cf56 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Fri, 1 May 2020 14:23:16 -0700 Subject: [PATCH 094/139] [docs] Make the link to initial setup stand out. (#533) * [docs] Make the link to initial setup stand out. * [docs] Merge the two quick starts * More descriptive text about the setup link Co-authored-by: alonamid --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 42 +++++++++-- docs/_static/css/custom.css | 6 ++ docs/conf.py | 3 + docs/index.rst | 82 +-------------------- docs/requirements.txt | 2 +- 5 files changed, 46 insertions(+), 89 deletions(-) create mode 100644 docs/_static/css/custom.css diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index c4732e8a..08930f50 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -23,10 +23,10 @@ In Ubuntu/Debian-based platforms (Ubuntu), we recommend installing the following .. Note:: When running on an Amazon Web Services EC2 FPGA-development instance (for FireSim), FireSim includes a machine setup script that will install all of the aforementioned dependencies (and some additional ones). -Checking out the sources ------------------------- +Setting up the Chipyard Repo +------------------------------------------- -After cloning this repo, you will need to initialize all of the submodules. +Start by fetching Chipyard's sources. Run: .. code-block:: shell @@ -34,6 +34,8 @@ After cloning this repo, you will need to initialize all of the submodules. cd chipyard ./scripts/init-submodules-no-riscv-tools.sh +This will initialize and checkout all of the necessary git submodules. + When updating Chipyard to a new version, you will also want to rerun this script to update the submodules. Using git directly will try to initialize all submodules; this is not recommended unless you expressly desire this behavior. @@ -46,15 +48,41 @@ The `toolchains` directory contains toolchains that include a cross-compiler too Currently there are two toolchains, one for normal RISC-V programs, and another for Hwacha (``esp-tools``). For custom installations, Each tool within the toolchains contains individual installation procedures within its README file. To get a basic installation (which is the only thing needed for most Chipyard use-cases), just the following steps are necessary. +This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. .. code-block:: shell ./scripts/build-toolchains.sh riscv-tools # for a normal risc-v toolchain - # OR - - ./scripts/build-toolchains.sh esp-tools # for a modified risc-v toolchain with Hwacha vector instructions +.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. + If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. Once the script is run, a ``env.sh`` file is emitted that sets the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables. -You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables. +You can put this in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment: + +.. code-block:: shell + + source ./env.sh + These variables need to be set for the ``make`` system to work properly. + +What's Next? +------------------------------------------- + +This depends on what you are planning to do with Chipyard. + +* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. + +* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. + +* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. + +* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. + +* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. + +* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. + +* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. + +* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. diff --git a/docs/_static/css/custom.css b/docs/_static/css/custom.css new file mode 100644 index 00000000..3fa65d52 --- /dev/null +++ b/docs/_static/css/custom.css @@ -0,0 +1,6 @@ +.important { + font-size: 175%; +} +.important p{ + font-size: 100%; +} diff --git a/docs/conf.py b/docs/conf.py index f4a3272b..e0accb5e 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -106,6 +106,9 @@ html_theme_options = { # relative to this directory. They are copied after the builtin static files, # so a file named "default.css" will overwrite the builtin "default.css". html_static_path = ['_static'] +html_css_files = [ + 'css/custom.css', +] # Custom sidebar templates, must be a dictionary that maps document names # to template names. diff --git a/docs/index.rst b/docs/index.rst index 855929cd..d776b353 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -10,89 +10,9 @@ Welcome to Chipyard's documentation! Chipyard is a framework for designing and evaluating full-system hardware using agile teams. It is composed of a collection of tools and libraries designed to provide an integration between open-source and commercial tools for the development of systems-on-chip. -New to Chipyard? Jump to the :ref:`Chipyard Basics` page for more info. -Quick Start -=============================== +.. IMPORTANT:: **New to Chipyard?** Jump to the :ref:`Initial Repository Setup` page for setup instructions. -System Requirements -------------------------------------------- - -Chipyard is developed and tested on Linux-based systems. - -.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. - -.. Warning:: Working under Windows is not recommended. - -Setting up the Chipyard Repo -------------------------------------------- - -Start by fetching Chipyard's sources. Run: - -.. code-block:: shell - - git clone https://github.com/ucb-bar/chipyard.git - cd chipyard - ./scripts/init-submodules-no-riscv-tools.sh - -This will initialize and checkout all of the necessary git submodules. - -Installing Dependencies -------------------------------------------- -Installing the recommended dependencies on Ubuntu/Debian-based platforms: - -.. code-block:: shell - - ./scripts/ubuntu-req.sh - -Installing the recommended dependencies on CentOS-based platforms: - -.. code-block:: shell - - ./scripts/centos-req.sh - -Installing the RISC-V Tools -------------------------------------------- - -We need to install the RISC-V toolchain in order to be able to run RISC-V programs using the Chipyard infrastructure. -This will take about 20-30 minutes. You can expedite the process by setting a ``make`` environment variable to use parallel cores: ``export MAKEFLAGS=-j8``. -To build the toolchains, you should run: - -.. code-block:: shell - - ./scripts/build-toolchains.sh - -.. Note:: If you are planning to use the Hwacha vector unit, or other RoCC-based accelerators, you should build the esp-tools toolchain by adding the ``esp-tools`` argument to the script above. - If you are running on an Amazon Web Services EC2 instance, intending to use FireSim, you can also use the ``--ec2fast`` flag for an expedited installation of a pre-compiled toolchain. - -Finally, set up Chipyard's environment variables and put the newly built toolchain on your path: - -.. code-block:: shell - - source ./env.sh - -What's Next? -------------------------------------------- - -This depends on what you are planning to do with Chipyard. - -* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions. - -* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions. - -* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions. - -* If you intend to add a new accelerator, go to :ref:`customization` and follow the instructions. - -* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`. - -* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`. - -* If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. - -* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. - - Getting Help ------------ diff --git a/docs/requirements.txt b/docs/requirements.txt index 2abac52d..4b1565b3 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,4 +1,4 @@ -Sphinx==1.7.4 +Sphinx==1.8.5 Pygments==2.2.0 sphinx-autobuild sphinx_rtd_theme==0.2.5b1 From 356de57580f336d4fc6ee533c3d3f24068485655 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 3 May 2020 14:25:12 -0700 Subject: [PATCH 095/139] Bump FireMarshal to disable SiFive uart driver --- software/firemarshal | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/firemarshal b/software/firemarshal index d660c45a..c8e89bbe 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit d660c45ac12df4624d1784c19dab03b92347f878 +Subproject commit c8e89bbeb575be027670afa21c761319c2fd7e33 From 794509aba9ee543d23911d9d4ce6272a50edbed6 Mon Sep 17 00:00:00 2001 From: John Wright Date: Mon, 4 May 2020 14:39:05 -0700 Subject: [PATCH 096/139] [ci skip] Scaladoc and comment fixes (#542) --- generators/chipyard/src/main/scala/IOBinders.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index e3c79f3a..281c5917 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -104,7 +104,7 @@ object AddIOCells { /** * Add IO cells to a SiFive UART devices and name the IO ports. - * @param gpios A Seq of UART port bundles + * @param uartPins A Seq of UART port bundles * @return Returns a tuple of (A Seq of top-level UARTPortIO IOs; a 2D Seq of IOCell module references) */ def uart(uartPins: Seq[UARTPortIO]): (Seq[UARTPortIO], Seq[Seq[IOCell]]) = { @@ -117,7 +117,7 @@ object AddIOCells { /** * Add IO cells to a debug module and name the IO ports. - * @param gpios A PSDIO bundle + * @param psd A PSDIO bundle * @param resetctrlOpt An optional ResetCtrlIO bundle * @param debugOpt An optional DebugIO bundle * @return Returns a tuple3 of (Top-level PSDIO IO; Optional top-level DebugIO IO; a list of IOCell module references) @@ -312,4 +312,4 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ } }) -} +} /* end package object */ From 9b945706484647a7d21ec549df04c38ac088e226 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 5 May 2020 11:02:28 -0700 Subject: [PATCH 097/139] bump rocket chisel (3.3) and firrtl (1.3) --- generators/rocket-chip | 2 +- tools/chisel3 | 2 +- tools/firrtl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/rocket-chip b/generators/rocket-chip index 9b1907ea..1872f5d5 160000 --- a/generators/rocket-chip +++ b/generators/rocket-chip @@ -1 +1 @@ -Subproject commit 9b1907eacbeb268d47e204e3de1818823d605ba4 +Subproject commit 1872f5d501221f13950aa2293939634a1e0d1735 diff --git a/tools/chisel3 b/tools/chisel3 index 7a343dce..21ea734d 160000 --- a/tools/chisel3 +++ b/tools/chisel3 @@ -1 +1 @@ -Subproject commit 7a343dce95a370f6cb7b9cf80e0694ac82dc94f8 +Subproject commit 21ea734d809395962a8d3195a76377f6e44308f3 diff --git a/tools/firrtl b/tools/firrtl index eb637777..7c6f58d9 160000 --- a/tools/firrtl +++ b/tools/firrtl @@ -1 +1 @@ -Subproject commit eb637777e3c4d77435cfd13358c521ed1b766ba8 +Subproject commit 7c6f58d986e67b3d0662a4cd6654a68f9cc52cf9 From 63c46d89c1184d7415e83a32c27608345a25f160 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 5 May 2020 13:58:01 -0700 Subject: [PATCH 098/139] Bump sifive-blocks --- docs/Customization/Heterogeneous-SoCs.rst | 1 - .../src/main/scala/ConfigFragments.scala | 8 -------- .../src/main/scala/config/ArianeConfigs.scala | 2 -- .../src/main/scala/config/BoomConfigs.scala | 8 -------- .../src/main/scala/config/HeteroConfigs.scala | 7 ------- .../src/main/scala/config/RocketConfigs.scala | 18 ------------------ .../main/scala/config/TutorialConfigs.scala | 4 ---- generators/sifive-blocks | 2 +- 8 files changed, 1 insertion(+), 49 deletions(-) diff --git a/docs/Customization/Heterogeneous-SoCs.rst b/docs/Customization/Heterogeneous-SoCs.rst index fd1a6880..c640e31c 100644 --- a/docs/Customization/Heterogeneous-SoCs.rst +++ b/docs/Customization/Heterogeneous-SoCs.rst @@ -56,7 +56,6 @@ Then you could use this new config fragment like the following. class SixCoreConfig extends Config( new WithTSI ++ - new WithNoGPIO ++ new WithBootROM ++ new WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index e1a047dc..2db12ff7 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -52,14 +52,6 @@ class WithUART extends Config((site, here, up) => { UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) -class WithNoGPIO extends Config((site, here, up) => { - case PeripheryGPIOKey => Nil -}) - -class WithNoUART extends Config((site, here, up) => { - case PeripheryUARTKey => Nil -}) - class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nL2TLBEntries = entries) diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index e0cb771e..6dfb4c74 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -15,7 +15,6 @@ class ArianeConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) @@ -31,7 +30,6 @@ class dmiArianeConfig extends Config( new chipyard.iobinders.WithSimAXIMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 35934eab..4c194368 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -13,7 +13,6 @@ class SmallBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -32,7 +31,6 @@ class MediumBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -51,7 +49,6 @@ class LargeBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -70,7 +67,6 @@ class MegaBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -89,7 +85,6 @@ class DualSmallBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -108,7 +103,6 @@ class SmallRV32BoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -129,7 +123,6 @@ class HwachaLargeBoomConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -151,7 +144,6 @@ class LoopbackNICLargeBoomConfig extends Config( new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback new testchipip.WithTSI ++ new icenet.WithIceNIC ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index af2145e7..11835aa4 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -13,7 +13,6 @@ class LargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -35,7 +34,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -58,7 +56,6 @@ class DualLargeBoomAndRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -81,7 +78,6 @@ class LargeBoomAndHwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc @@ -107,7 +103,6 @@ class LargeBoomAndRV32RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -131,7 +126,6 @@ class DualLargeBoomAndDualRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -153,7 +147,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithControlCore ++ // add small control core to last hartid diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index e25680ca..4058fcf4 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -13,7 +13,6 @@ class RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks) new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs @@ -31,7 +30,6 @@ class HwachaRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -51,7 +49,6 @@ class GemminiRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -71,7 +68,6 @@ class RoccRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -91,7 +87,6 @@ class jtagRocketConfig extends Config( new chipyard.iobinders.WithSimDebug ++ // add SimJtag and SimSerial, use both to drive sim new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -111,7 +106,6 @@ class dmiRocketConfig extends Config( new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithTiedOffSerial ++ new chipyard.iobinders.WithSimDebug ++ // add SimDebug and use it to drive simulation - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -131,7 +125,6 @@ class GCDTLRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithUART ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -153,7 +146,6 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new chipyard.config.WithUART ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithL2TLBs(1024) ++ new chipyard.example.WithGCD(useAXI4=true, useBlackBox=true) ++ // Use GCD blackboxed verilog, connect by AXI4->Tilelink @@ -174,7 +166,6 @@ class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to peripherybus - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -194,7 +185,6 @@ class BlockDeviceModelRocketConfig extends Config( new chipyard.iobinders.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel new testchipip.WithTSI ++ new testchipip.WithBlockDevice ++ // add block-device module to periphery bus - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -235,7 +225,6 @@ class QuadRocketConfig extends Config( new testchipip.WithTSI ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithL2TLBs(1024) ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ @@ -251,7 +240,6 @@ class RV32RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ @@ -269,7 +257,6 @@ class GB1MemoryRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -289,7 +276,6 @@ class Sha3RocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -310,7 +296,6 @@ class InitZeroRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -332,7 +317,6 @@ class LoopbackNICRocketConfig extends Config( new chipyard.iobinders.WithLoopbackNIC ++ // drive NIC IOs with loopback new testchipip.WithTSI ++ new icenet.WithIceNIC ++ // add an IceNIC - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -351,7 +335,6 @@ class ScratchpadRocketConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ new testchipip.WithBackingScratchpad ++ // add backing scratchpad - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ @@ -372,7 +355,6 @@ class RingSystemBusRocketConfig extends Config( new chipyard.iobinders.WithTiedOffDebug ++ new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index 0c74b581..e149bd23 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -29,7 +29,6 @@ class TutorialStarterConfig extends Config( // Config fragments below this line affect hardware generation // of the Top new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core - new chipyard.config.WithNoGPIO ++ // Disable GPIOs. new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op new chipyard.config.WithUART ++ // Add a UART @@ -65,7 +64,6 @@ class TutorialMMIOConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -93,7 +91,6 @@ class TutorialSha3Config extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ @@ -119,7 +116,6 @@ class TutorialSha3BlackBoxConfig extends Config( new chipyard.iobinders.WithSimSerial ++ new testchipip.WithTSI ++ - new chipyard.config.WithNoGPIO ++ new chipyard.config.WithBootROM ++ new chipyard.config.WithRenumberHarts ++ new chipyard.config.WithUART ++ diff --git a/generators/sifive-blocks b/generators/sifive-blocks index 3e35a94d..c1dee823 160000 --- a/generators/sifive-blocks +++ b/generators/sifive-blocks @@ -1 +1 @@ -Subproject commit 3e35a94d46d88506d5b14b2c34f05b8651844452 +Subproject commit c1dee8234c23c8fc454108e59ecba20987f95cde From 43f6083b692b4e6c23edd3863f89307eecd13826 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 5 May 2020 14:57:54 -0700 Subject: [PATCH 099/139] Many changes to begin the compilation with RC-1.3 Cores now have an extra CoreParam, useSupervisor which was set to the default false. Whether a core has supervisor mode is the union of this and useVM which defaults true so not change was made by this addition. BusTopologies are now set with the Config system rather than a system mixin and so all configs now include the config most similar to the previous mixin Testchipip was updated to be able to replace the systembus, in this new config system, with a ring bus. The L2 cache repo needed a similar update on how to find the buses. It currently points to the ucb-bar fork Treadle is bumped to its release branch --- .gitmodules | 2 +- generators/ariane | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/System.scala | 1 - .../src/main/scala/config/ArianeConfigs.scala | 2 ++ .../src/main/scala/config/BoomConfigs.scala | 8 ++++++++ .../src/main/scala/config/HeteroConfigs.scala | 7 +++++++ .../src/main/scala/config/RocketConfigs.scala | 19 +++++++++++++++++++ .../main/scala/config/TracegenConfigs.scala | 5 +++++ .../main/scala/config/TutorialConfigs.scala | 4 ++++ generators/sifive-cache | 2 +- generators/testchipip | 2 +- .../tracegen/src/main/scala/System.scala | 1 - tools/treadle | 2 +- 14 files changed, 51 insertions(+), 8 deletions(-) diff --git a/.gitmodules b/.gitmodules index 34846d61..b331ae3f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,7 +33,7 @@ url = https://github.com/firesim/icenet.git [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache - url = https://github.com/sifive/block-inclusivecache-sifive.git + url = https://github.com/ucb-bar/block-inclusivecache-sifive.git [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git diff --git a/generators/ariane b/generators/ariane index f4ba64a6..1086f902 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit f4ba64a624091600e9d7d40c293b8d5c17f47c56 +Subproject commit 1086f90223bc03be6d46d019fcce10d6c27f5c12 diff --git a/generators/boom b/generators/boom index 90911dde..79c0e558 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 90911dde1b8730f10c958d172f26f72d718be5ae +Subproject commit 79c0e5583c37128e8e22591b264f5a7eed605b9a diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala index 6d99ca6a..222ff77c 100644 --- a/generators/chipyard/src/main/scala/System.scala +++ b/generators/chipyard/src/main/scala/System.scala @@ -22,7 +22,6 @@ import freechips.rocketchip.util.{DontTouch} * Base top with periphery devices and ports, and a BOOM + Rocket subsystem */ class System(implicit p: Parameters) extends Subsystem - with HasHierarchicalBusTopology with HasAsyncExtInterrupts with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MMIOPort diff --git a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala index 6dfb4c74..6fb2ef00 100644 --- a/generators/chipyard/src/main/scala/config/ArianeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ArianeConfigs.scala @@ -22,6 +22,7 @@ class ArianeConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new ariane.WithNArianeCores(1) ++ // single Ariane core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class dmiArianeConfig extends Config( @@ -37,4 +38,5 @@ class dmiArianeConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new ariane.WithNArianeCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 4c194368..48a9126e 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -22,6 +22,7 @@ class SmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new boom.common.WithSmallBooms ++ // small boom config new boom.common.WithNBoomCores(1) ++ // single-core boom + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class MediumBoomConfig extends Config( @@ -40,6 +41,7 @@ class MediumBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class LargeBoomConfig extends Config( @@ -58,6 +60,7 @@ class LargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class MegaBoomConfig extends Config( @@ -76,6 +79,7 @@ class MegaBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class DualSmallBoomConfig extends Config( @@ -94,6 +98,7 @@ class DualSmallBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithSmallBooms ++ new boom.common.WithNBoomCores(2) ++ // 2 boom cores + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class SmallRV32BoomConfig extends Config( @@ -114,6 +119,7 @@ class SmallRV32BoomConfig extends Config( new boom.common.WithBoomRV32 ++ // rv32 (32bit) new boom.common.WithSmallBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class HwachaLargeBoomConfig extends Config( @@ -133,6 +139,7 @@ class HwachaLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class LoopbackNICLargeBoomConfig extends Config( @@ -153,5 +160,6 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala index 11835aa4..4388ca2b 100644 --- a/generators/chipyard/src/main/scala/config/HeteroConfigs.scala +++ b/generators/chipyard/src/main/scala/config/HeteroConfigs.scala @@ -24,6 +24,7 @@ class LargeBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system // DOC include start: BoomAndRocketWithHwacha @@ -46,6 +47,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: BoomAndRocketWithHwacha @@ -67,6 +69,7 @@ class DualLargeBoomAndRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: DualBoomAndRocketOneHwacha @@ -91,6 +94,7 @@ class LargeBoomAndHwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocketOneHwacha @@ -115,6 +119,7 @@ class LargeBoomAndRV32RocketConfig extends Config( new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) @@ -137,6 +142,7 @@ class DualLargeBoomAndDualRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DualBoomAndRocket @@ -159,5 +165,6 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 4058fcf4..ac29c662 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -21,6 +21,7 @@ class RocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system class HwachaRocketConfig extends Config( @@ -39,6 +40,7 @@ class HwachaRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GemminiRocketConfig @@ -58,6 +60,7 @@ class GemminiRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GemminiRocketConfig @@ -77,6 +80,7 @@ class RoccRocketConfig extends Config( new freechips.rocketchip.subsystem.WithRoccExample ++ // use example RoCC-based accelerator new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: JtagRocket @@ -96,6 +100,7 @@ class jtagRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: JtagRocket @@ -114,6 +119,7 @@ class dmiRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: DmiRocket @@ -134,6 +140,7 @@ class GCDTLRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDTLRocketConfig @@ -154,6 +161,7 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig @@ -174,6 +182,7 @@ class SimBlockDeviceRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class BlockDeviceModelRocketConfig extends Config( @@ -193,6 +202,7 @@ class BlockDeviceModelRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: GPIORocketConfig @@ -213,6 +223,7 @@ class GPIORocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: GPIORocketConfig @@ -231,6 +242,7 @@ class QuadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(4) ++ // quad-core (4 RocketTiles) + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class RV32RocketConfig extends Config( @@ -248,6 +260,7 @@ class RV32RocketConfig extends Config( new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class GB1MemoryRocketConfig extends Config( @@ -266,6 +279,7 @@ class GB1MemoryRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: Sha3Rocket @@ -285,6 +299,7 @@ class Sha3RocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: Sha3Rocket @@ -305,6 +320,7 @@ class InitZeroRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: InitZeroRocketConfig @@ -325,6 +341,7 @@ class LoopbackNICRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include start: scratchpadrocket @@ -344,6 +361,7 @@ class ScratchpadRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: scratchpadrocket @@ -364,5 +382,6 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala index fefa271d..2a31293f 100644 --- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala @@ -8,6 +8,7 @@ class TraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenConfig extends Config( @@ -15,6 +16,7 @@ class NonBlockingTraceGenConfig extends Config( new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.config.WithTracegenSystem ++ new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class BoomTraceGenConfig extends Config( @@ -23,6 +25,7 @@ class BoomTraceGenConfig extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2Config extends Config( @@ -31,6 +34,7 @@ class NonBlockingTraceGenL2Config extends Config( new chipyard.config.WithTracegenSystem ++ new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) class NonBlockingTraceGenL2RingConfig extends Config( @@ -40,4 +44,5 @@ class NonBlockingTraceGenL2RingConfig extends Config( new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new testchipip.WithRingSystemBus ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) diff --git a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala index e149bd23..c11d103d 100644 --- a/generators/chipyard/src/main/scala/config/TutorialConfigs.scala +++ b/generators/chipyard/src/main/scala/config/TutorialConfigs.scala @@ -50,6 +50,7 @@ class TutorialStarterConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 // BaseConfig configures "bare" rocketchip system new freechips.rocketchip.system.BaseConfig ) @@ -79,6 +80,7 @@ class TutorialMMIOConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) @@ -104,6 +106,7 @@ class TutorialSha3Config extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) @@ -130,5 +133,6 @@ class TutorialSha3BlackBoxConfig extends Config( new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/sifive-cache b/generators/sifive-cache index d3d95ece..9ac1a524 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit d3d95ece5a570b423892bede4fed6cb0030c7701 +Subproject commit 9ac1a5242d1fcbb16495f0289d329be35b28370c diff --git a/generators/testchipip b/generators/testchipip index cec2c0b6..8fbd4f43 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cec2c0b6d66c3df05d08462167bb8a58c0912d06 +Subproject commit 8fbd4f43b6351a7e2eeb27b6096cf4e81aa72bf7 diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala index cb5d0af8..1653ba79 100644 --- a/generators/tracegen/src/main/scala/System.scala +++ b/generators/tracegen/src/main/scala/System.scala @@ -41,7 +41,6 @@ trait HasTraceGenTilesModuleImp extends LazyModuleImp { class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem with HasTraceGenTiles - with HasHierarchicalBusTopology with CanHaveMasterAXI4MemPort { override lazy val module = new TraceGenSystemModuleImp(this) } diff --git a/tools/treadle b/tools/treadle index a03b969a..6ca4fec6 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit a03b969af104770a7662ecdbac80cebf622e674b +Subproject commit 6ca4fec6117b58a58e628f55c3eac46d4b15d03a From a255417513180ab4e4f53ee20b964e9eac701674 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Tue, 5 May 2020 15:24:51 -0700 Subject: [PATCH 100/139] Update stage to use Dependency instead of classof --- .../src/main/scala/stage/ChipyardStage.scala | 34 +++++++++---------- .../scala/stage/phases/AddDefaultTests.scala | 8 ++--- .../phases/GenerateTestSuiteMakefrags.scala | 6 ++-- 3 files changed, 24 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala index a24afd43..4e429618 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardStage.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardStage.scala @@ -10,27 +10,27 @@ import firrtl.stage.FirrtlCli import freechips.rocketchip.stage.RocketChipCli import freechips.rocketchip.system.RocketChipStage -import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain} +import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency} import firrtl.options.phases.DeletedWrapper class ChipyardStage extends ChiselStage with PreservesAll[Phase] { override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli override val targets: Seq[PhaseDependency] = Seq( - classOf[freechips.rocketchip.stage.phases.Checks], - classOf[freechips.rocketchip.stage.phases.TransformAnnotations], - classOf[freechips.rocketchip.stage.phases.PreElaboration], - classOf[chisel3.stage.phases.Checks], - classOf[chisel3.stage.phases.Elaborate], - classOf[freechips.rocketchip.stage.phases.GenerateROMs], - classOf[chisel3.stage.phases.AddImplicitOutputFile], - classOf[chisel3.stage.phases.AddImplicitOutputAnnotationFile], - classOf[chisel3.stage.phases.MaybeAspectPhase], - classOf[chisel3.stage.phases.Emitter], - classOf[chisel3.stage.phases.Convert], - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.AddDefaultTests], - classOf[chipyard.stage.phases.GenerateTestSuiteMakefrags], - classOf[freechips.rocketchip.stage.phases.GenerateArtefacts], + Dependency[freechips.rocketchip.stage.phases.Checks], + Dependency[freechips.rocketchip.stage.phases.TransformAnnotations], + Dependency[freechips.rocketchip.stage.phases.PreElaboration], + Dependency[chisel3.stage.phases.Checks], + Dependency[chisel3.stage.phases.Elaborate], + Dependency[freechips.rocketchip.stage.phases.GenerateROMs], + Dependency[chisel3.stage.phases.AddImplicitOutputFile], + Dependency[chisel3.stage.phases.AddImplicitOutputAnnotationFile], + Dependency[chisel3.stage.phases.MaybeAspectPhase], + Dependency[chisel3.stage.phases.Emitter], + Dependency[chisel3.stage.phases.Convert], + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.AddDefaultTests], + Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags], + Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts], ) } diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index 277d04b5..fce5d432 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -10,7 +10,7 @@ import chipsalliance.rocketchip.config.Parameters import chisel3.stage.phases.Elaborate import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll} +import firrtl.options.{Phase, PreservesAll, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -23,9 +23,9 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such). override val prerequisites = Seq( - classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[freechips.rocketchip.stage.phases.AddDefaultTests]) - override val dependents = Seq(classOf[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) + Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[freechips.rocketchip.stage.phases.AddDefaultTests]) + override val dependents = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateTestSuiteMakefrags]) private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() diff --git a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala index 76f99ab7..0ed5ec11 100644 --- a/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala +++ b/generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala @@ -7,7 +7,7 @@ import scala.collection.mutable import firrtl.AnnotationSeq import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable} +import firrtl.options.{Phase, PreservesAll, StageOptions, Unserializable, Dependency} import firrtl.options.Viewer.view import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} @@ -24,8 +24,8 @@ case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotat class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils { // Our annotations tend not to be serializable, but are not marked as such. - override val prerequisites = Seq(classOf[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], - classOf[chipyard.stage.phases.AddDefaultTests]) + override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos], + Dependency[chipyard.stage.phases.AddDefaultTests]) override def transform(annotations: AnnotationSeq): AnnotationSeq = { val targetDir = view[StageOptions](annotations).targetDir From 006ecd2b7c9e6f13a9067b5c7b2b67293dcad809 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 6 May 2020 21:46:25 +0000 Subject: [PATCH 101/139] Basic changes to barstools to get sim to compile --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index e230e8cf..02ffbd78 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit e230e8cf3f7c0bc3c958cab22c5d90d195ca6b01 +Subproject commit 02ffbd78b9a69e94edd22280da3d80f12b70fb22 From 3c18880064d9bb8d719dfa0d82204cbbf5b287c7 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Wed, 6 May 2020 18:39:42 -0700 Subject: [PATCH 102/139] Increase verilator reset length --- generators/utilities/src/main/resources/csrc/emulator.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index 0e86b836..acec6005 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -283,7 +283,7 @@ done_processing: bool dump; // reset for several cycles to handle pipelined reset - for (int i = 0; i < 10; i++) { + for (int i = 0; i < 100; i++) { tile->reset = 1; tile->clock = 0; tile->eval(); From 596925020f97b10e822247f21444622ee0a74221 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 7 May 2020 11:24:17 -0700 Subject: [PATCH 103/139] Connect debug clocks when debug is tied off --- generators/chipyard/src/main/scala/IOBinders.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 281c5917..ea0f610b 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -256,8 +256,9 @@ class WithTiedOffDebug extends OverrideIOBinder({ Debug.tieoffDebug(debugPortOpt, resetctrlOpt, Some(psdPort))(system.p) // tieoffDebug doesn't actually tie everything off :/ debugPortOpt.foreach { d => - d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) + d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := th.clock }) d.dmactiveAck := DontCare + d.clock := th.clock } Nil } From 0bdf39ffe43791bbff07d47b06983ad66b1749c4 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 9 May 2020 04:21:49 +0000 Subject: [PATCH 104/139] [SBT] Hush up scalasbt resolver http complaint --- project/plugins.sbt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/project/plugins.sbt b/project/plugins.sbt index d8d00e35..8de71081 100644 --- a/project/plugins.sbt +++ b/project/plugins.sbt @@ -1,4 +1,4 @@ -resolvers += Resolver.url("scalasbt", new URL("http://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) +resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns) resolvers += Classpaths.sbtPluginReleases resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven" From 2fa9a41902d2ac0c2df767be4663a924291c7199 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 11 May 2020 03:46:03 +0000 Subject: [PATCH 105/139] [make] Fix firrtl prerequiste lookup --- common.mk | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index b5a5bb07..ddb2a355 100644 --- a/common.mk +++ b/common.mk @@ -16,8 +16,9 @@ include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk ######################################################################################### -# variables to get all *.scala files +# Prerequisite lists ######################################################################################### +# Returns a list of files in directory $1 with file extension $2. lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null) SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) @@ -36,7 +37,7 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class ######################################################################################### FIRRTL_JAR := $(base_dir)/lib/firrtl.jar -$(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) +$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala mkdir -p $(@D) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ @@ -45,7 +46,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala) ######################################################################################### # create list of simulation file inputs ######################################################################################### -$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR) +$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" ######################################################################################### From 2a6bd3bd5c6f8bf0147ae65433d15ba91eeb4bad Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Mon, 11 May 2020 23:02:37 -0700 Subject: [PATCH 106/139] Bump verilator to v4.034 (#547) * Bump verilator to v4.034 * Add new flags to verilator makefile * Conditionally set timescale flag based on Verilator version --- .circleci/defaults.sh | 2 +- .circleci/images/Dockerfile | 2 +- scripts/centos-req.sh | 2 +- scripts/ubuntu-req.sh | 2 +- sims/verilator/Makefile | 3 +++ 5 files changed, 7 insertions(+), 4 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 38da902b..3420a1a2 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -21,7 +21,7 @@ clean () { NPROC=8 # verilator version -VERILATOR_VERSION=v4.028 +VERILATOR_VERSION=v4.034 # remote variables REMOTE_WORK_DIR=$CI_DIR/$CIRCLE_PROJECT_REPONAME-$CIRCLE_BRANCH-$CIRCLE_SHA1-$CIRCLE_JOB diff --git a/.circleci/images/Dockerfile b/.circleci/images/Dockerfile index 807c15f0..3efb4cc9 100644 --- a/.circleci/images/Dockerfile +++ b/.circleci/images/Dockerfile @@ -164,7 +164,7 @@ RUN apt-get install -y \ # Install verilator RUN git clone http://git.veripool.org/git/verilator \ && cd verilator \ - && git checkout v4.028 \ + && git checkout v4.034 \ && autoconf && ./configure && make && make install # Update PATH for Java tools diff --git a/scripts/centos-req.sh b/scripts/centos-req.sh index 30b9fe70..89e8644c 100755 --- a/scripts/centos-req.sh +++ b/scripts/centos-req.sh @@ -22,5 +22,5 @@ sudo yum install -y dtc # install verilator git clone http://git.veripool.org/git/verilator cd verilator -git checkout v4.028 +git checkout v4.034 autoconf && ./configure && make -j16 && sudo make install diff --git a/scripts/ubuntu-req.sh b/scripts/ubuntu-req.sh index ee541e81..f72c48f4 100755 --- a/scripts/ubuntu-req.sh +++ b/scripts/ubuntu-req.sh @@ -23,5 +23,5 @@ sudo apt-get install -y device-tree-compiler # install verilator git clone http://git.veripool.org/git/verilator cd verilator -git checkout v4.028 +git checkout v4.034 autoconf && ./configure && make -j16 && sudo make install diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 432169d6..fd7f1bd6 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -86,7 +86,10 @@ ARIANE_VERILATOR_FLAGS = \ CHIPYARD_VERILATOR_FLAGS = \ --assert +# Use --timescale to approximate timescale behavior of pre-4.034 +TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 >= 4.034) { print "--timescale 1ns/1ps"; }') VERILATOR_NONCC_OPTS = \ + $(TIMESCALE_OPTS) \ --top-module $(VLOG_MODEL) \ $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ From d16c57867d162fcf47feda65f0a61ac7ff0c290c Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 12 May 2020 22:00:43 +0000 Subject: [PATCH 107/139] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index d5d4f4d6..e7bc5351 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit d5d4f4d6f8cf5a499fee5365eec9eec794bbd08c +Subproject commit e7bc535160e5887b7d642fcddcb1479dfcd98463 From 6950ad7cee715e6e935dcb67a9794a031af9ddf8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 12 May 2020 22:01:14 +0000 Subject: [PATCH 108/139] Comment out Ariane from ScalaTests --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index c5af5cda..cf2358d9 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -141,9 +141,9 @@ class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimL class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { - runSuite("verilator")(NICLoopbackTests) -} +//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { +// runSuite("verilator")(NICLoopbackTests) +//} // Disabled until RAM optimizations re-enabled in multiclock //class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") //class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") From 933d03356902cf37b68f664af2d0ffcec69401dc Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 12 May 2020 23:34:01 -0700 Subject: [PATCH 109/139] sifive cache bump to RC firrtl 1.3 --- .gitmodules | 2 +- generators/sifive-cache | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index b331ae3f..34846d61 100644 --- a/.gitmodules +++ b/.gitmodules @@ -33,7 +33,7 @@ url = https://github.com/firesim/icenet.git [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache - url = https://github.com/ucb-bar/block-inclusivecache-sifive.git + url = https://github.com/sifive/block-inclusivecache-sifive.git [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git diff --git a/generators/sifive-cache b/generators/sifive-cache index 9ac1a524..4ebefa3e 160000 --- a/generators/sifive-cache +++ b/generators/sifive-cache @@ -1 +1 @@ -Subproject commit 9ac1a5242d1fcbb16495f0289d329be35b28370c +Subproject commit 4ebefa3e30ec44bd2f4ff82747025fb7b362b954 From 9e95082a8a6484c911b497a061100fdb3d030aae Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 00:10:23 -0700 Subject: [PATCH 110/139] bump testchipip with buffer arg --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 8fbd4f43..5b3f2c96 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8fbd4f43b6351a7e2eeb27b6096cf4e81aa72bf7 +Subproject commit 5b3f2c9654d4cb06a64e8ac5df864c706a07bda8 From f0389bbe66b36c6441ed9c3c3e3e67e724d6ae07 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 10:03:30 -0700 Subject: [PATCH 111/139] bump boom and ariane to master with RC firrtl 1.3 --- generators/ariane | 2 +- generators/boom | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/ariane b/generators/ariane index 1086f902..66cbcd01 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 1086f90223bc03be6d46d019fcce10d6c27f5c12 +Subproject commit 66cbcd0115f8f4e2abb38684532ec945622adcae diff --git a/generators/boom b/generators/boom index 79c0e558..d0077cff 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 79c0e5583c37128e8e22591b264f5a7eed605b9a +Subproject commit d0077cff74140153e314f05f631c5e07b0d694ea From d5c1ad4c1f75058e5f2150501074417fba3ef976 Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Wed, 13 May 2020 10:38:23 -0700 Subject: [PATCH 112/139] Bump barstools --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 02ffbd78..c4e5f66c 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 02ffbd78b9a69e94edd22280da3d80f12b70fb22 +Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 From afb6518ec2f65080c54a6a899e69245697539f25 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 10:40:02 -0700 Subject: [PATCH 113/139] bump barstools to master with firrtl 1.3 --- tools/barstools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/barstools b/tools/barstools index 02ffbd78..c4e5f66c 160000 --- a/tools/barstools +++ b/tools/barstools @@ -1 +1 @@ -Subproject commit 02ffbd78b9a69e94edd22280da3d80f12b70fb22 +Subproject commit c4e5f66c5e795c744b7f3be2780f7f2bb15e9e23 From de617d16edfd1fb509998a7395d99c34696458a2 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 11:31:40 -0700 Subject: [PATCH 114/139] bump firesim with firrtl 1.3 --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index e7bc5351..6482be6d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit e7bc535160e5887b7d642fcddcb1479dfcd98463 +Subproject commit 6482be6d2e435392815f5e24631b5644787e3467 From 3fc205997f24a54c0d5cb436457949e805e7f939 Mon Sep 17 00:00:00 2001 From: alonamid Date: Wed, 13 May 2020 11:41:21 -0700 Subject: [PATCH 115/139] bump treadle to master --- tools/treadle | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/treadle b/tools/treadle index 6ca4fec6..1c67bc84 160000 --- a/tools/treadle +++ b/tools/treadle @@ -1 +1 @@ -Subproject commit 6ca4fec6117b58a58e628f55c3eac46d4b15d03a +Subproject commit 1c67bc846aafc3bdd707f76ead8cefd5f93e0376 From 460455e79084811be7e35ded7b772cbb178d4b18 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Wed, 13 May 2020 13:18:06 -0700 Subject: [PATCH 116/139] extend midas examples timeout in ci --- .circleci/config.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.circleci/config.yml b/.circleci/config.yml index ff691e41..4d849e77 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -341,6 +341,7 @@ jobs: - run: name: Run midasexamples tests command: .circleci/run-midasexamples-tests.sh + no_output_timeout: 20m chipyard-ariane-run-tests: executor: main-env steps: From ebe993cefeab6bd6bff6481e6bb09f460e47b478 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 14 May 2020 03:09:39 +0000 Subject: [PATCH 117/139] Assemble the firrt-test.jar and put it in its own directory --- build.sbt | 2 +- common.mk | 7 +++++++ sims/firesim | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index b0e8c84d..a87496c9 100644 --- a/build.sbt +++ b/build.sbt @@ -2,7 +2,7 @@ import Tests._ // This gives us a nicer handle to the root project instead of using the // implicit one -lazy val chipyardRoot = RootProject(file(".")) +lazy val chipyardRoot = Project("chipyardRoot", file(".")) lazy val commonSettings = Seq( organization := "edu.berkeley.cs", diff --git a/common.mk b/common.mk index ddb2a355..e9248953 100644 --- a/common.mk +++ b/common.mk @@ -36,6 +36,7 @@ TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/class # jar creation variables and rules ######################################################################################### FIRRTL_JAR := $(base_dir)/lib/firrtl.jar +FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar $(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) $(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala @@ -43,6 +44,12 @@ $(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@ touch $@ +$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala) + cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly" + mkdir -p $(@D) + cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ + touch $@ + ######################################################################################### # create list of simulation file inputs ######################################################################################### diff --git a/sims/firesim b/sims/firesim index 6482be6d..4ec7325a 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6482be6d2e435392815f5e24631b5644787e3467 +Subproject commit 4ec7325ac60d3dd5862798cabb823e446040b90e From 7c7b336c3fef8aaf16a7266d95b3fbd9e7d9418b Mon Sep 17 00:00:00 2001 From: John Wright Date: Thu, 14 May 2020 19:19:50 -0700 Subject: [PATCH 118/139] Add SPI flash support (#546) * Add SPI flash configs, IOBinders, CI tests, and docs * Add writable SPI flash support * bump * Fix CI * Fix CI * Update docs/Generators/TestChipIP.rst Co-authored-by: Chick Markley * Maybe actually fix CI * Fix broken merge * Fix the tutorial patch * bump tcip to master * fix GPIO naming bug Co-authored-by: Chick Markley --- .circleci/config.yml | 40 +++- .circleci/defaults.sh | 2 + .circleci/images/Dockerfile | 26 ++- .circleci/run-tests.sh | 9 + docs/Generators/TestChipIP.rst | 8 + .../src/main/scala/ConfigFragments.scala | 7 + .../chipyard/src/main/scala/DigitalTop.scala | 2 + .../chipyard/src/main/scala/IOBinders.scala | 46 ++++- .../src/main/scala/config/RocketConfigs.scala | 40 ++++ generators/testchipip | 2 +- .../src/main/resources/csrc/emulator.cc | 8 +- .../RocketConfigs.scala.patch | 4 +- tests/.gitignore | 1 + tests/Makefile | 9 +- tests/spiflash.h | 174 ++++++++++++++++++ tests/spiflash.py | 11 ++ tests/spiflashread.c | 77 ++++++++ tests/spiflashwrite.c | 55 ++++++ 18 files changed, 505 insertions(+), 16 deletions(-) create mode 100644 tests/spiflash.h create mode 100755 tests/spiflash.py create mode 100644 tests/spiflashread.c create mode 100644 tests/spiflashwrite.c diff --git a/.circleci/config.yml b/.circleci/config.yml index 4d849e77..8e88f7eb 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -12,7 +12,7 @@ parameters: executors: main-env: docker: - - image: ucbbar/chipyard-image:1.0.0 + - image: ucbbar/chipyard-image:1.0.1 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit @@ -262,6 +262,16 @@ jobs: steps: - prepare-rtl: project-key: "testchipip" + prepare-chipyard-spiflashwrite: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-spiflashwrite" + prepare-chipyard-spiflashread: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-spiflashread" chipyard-rocket-run-tests: executor: main-env steps: @@ -300,6 +310,16 @@ jobs: - run-tests: tools-version: "esp-tools" project-key: "chipyard-gemmini" + chipyard-spiflashwrite-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-spiflashwrite" + chipyard-spiflashread-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-spiflashread" tracegen-run-tests: executor: main-env steps: @@ -464,6 +484,16 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-spiflashwrite: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-spiflashread: + requires: + - install-riscv-toolchain + - install-verilator + # Run the respective tests # Run midasexamples test @@ -508,6 +538,14 @@ workflows: requires: - prepare-tracegen-boom + - chipyard-spiflashwrite-run-tests: + requires: + - prepare-chipyard-spiflashwrite + + - chipyard-spiflashread-run-tests: + requires: + - prepare-chipyard-spiflashread + # Run the firesim tests - firesim-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 3420a1a2..e944e7fd 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -52,6 +52,8 @@ mapping["chipyard-blkdev"]="SUB_PROJECT=chipyard CONFIG=SimBlockDeviceRocketConf mapping["chipyard-hwacha"]="SUB_PROJECT=chipyard CONFIG=HwachaRocketConfig" mapping["chipyard-gemmini"]="SUB_PROJECT=chipyard CONFIG=GemminiRocketConfig" mapping["chipyard-ariane"]="SUB_PROJECT=chipyard CONFIG=ArianeConfig" +mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRocketConfig" +mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" diff --git a/.circleci/images/Dockerfile b/.circleci/images/Dockerfile index 3efb4cc9..7d031850 100644 --- a/.circleci/images/Dockerfile +++ b/.circleci/images/Dockerfile @@ -13,6 +13,8 @@ RUN apt-get update \ git \ gnupg \ gzip \ + libfl2 \ + libfl-dev \ locales \ mercurial \ netcat \ @@ -24,7 +26,12 @@ RUN apt-get update \ unzip \ wget \ xvfb \ - zip + xxd \ + zip \ + ccache \ + libgoogle-perftools-dev \ + numactl \ + zlib1g # Set timezone to UTC by default RUN ln -sf /usr/share/zoneinfo/Etc/UTC /etc/localtime @@ -127,34 +134,46 @@ RUN apt-get install -y --no-install-recommends openjfx RUN apt-get install -y build-essential # Add RISCV toolchain necessary dependencies +RUN apt-get update RUN apt-get install -y \ autoconf \ automake \ autotools-dev \ babeltrace \ bc \ - bison \ curl \ device-tree-compiler \ expat \ flex \ gawk \ gperf \ + g++ \ libexpat-dev \ libgmp-dev \ libmpc-dev \ libmpfr-dev \ libtool \ libusb-1.0-0-dev \ + make \ patchutils \ pkg-config \ python \ - python-pexpect \ + python-pexpect-doc \ python3 \ texinfo \ zlib1g-dev \ rsync +# Use specific bison version to bypass Verilator 4.034 issues +# TODO: When Verilator is bumped, use apt to get newest bison +RUN wget https://ftp.gnu.org/gnu/bison/bison-3.5.4.tar.gz \ + && tar -xvf bison-3.5.4.tar.gz \ + && cd bison-3.5.4 \ + && ./configure && make && make install + +# Check bison version is 3.5.4 +RUN bison --version + # Add minimal QEMU dependencies RUN apt-get install -y \ libfdt-dev \ @@ -164,6 +183,7 @@ RUN apt-get install -y \ # Install verilator RUN git clone http://git.veripool.org/git/verilator \ && cd verilator \ + && git pull \ && git checkout v4.034 \ && autoconf && ./configure && make && make install diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 5f305617..c7794173 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -62,6 +62,15 @@ case $1 in (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh) $LOCAL_SIM_DIR/simulator-chipyard-Sha3RocketConfig $LOCAL_CHIPYARD_DIR/generators/sha3/software/benchmarks/bare/sha3-rocc.riscv ;; + chipyard-spiflashread) + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary + ;; + chipyard-spiflashwrite) + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv SIM_FLAGS="+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img" run-binary + [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false + ;; tracegen) run_tracegen ${mapping[$1]} ;; diff --git a/docs/Generators/TestChipIP.rst b/docs/Generators/TestChipIP.rst index 31f9ce53..363e3245 100644 --- a/docs/Generators/TestChipIP.rst +++ b/docs/Generators/TestChipIP.rst @@ -84,3 +84,11 @@ output a UART log to a particular file using ``+uartlog=`` during By default, this UART Adapter is added to all systems within Chipyard by adding the ``WithUART`` and ``WithUARTAdapter`` configs. + +SPI Flash Model +--------------- + +The SPI flash model is a device that models a simple SPI flash device. It currently +only supports single read, quad read, single write, and quad write instructions. The +memory is backed by a file which is provided using ``+spiflash#=``, +where ``#`` is the SPI flash ID (usually ``0``). diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 2db12ff7..c2fec56f 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -20,6 +20,7 @@ import hwacha.{Hwacha} import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ import chipyard.{BuildTop, BuildSystem} @@ -52,6 +53,12 @@ class WithUART extends Config((site, here, up) => { UARTParams(address = 0x54000000L, nTxEntries = 256, nRxEntries = 256)) }) +class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) => { + // Note: the default size matches freedom with the addresses below + case PeripherySPIFlashKey => Seq( + SPIFlashParams(rAddress = 0x10040000, fAddress = 0x20000000, fSize = size)) +}) + class WithL2TLBs(entries: Int) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nL2TLBEntries = entries) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index c7b3d497..e8fb4f4c 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -19,6 +19,7 @@ class DigitalTop(implicit p: Parameters) extends System with testchipip.CanHavePeripherySerial // Enables optionally adding the TSI serial-adapter and port with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs + with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget @@ -32,6 +33,7 @@ class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) with testchipip.CanHavePeripherySerialModuleImp with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp with sifive.blocks.devices.gpio.HasPeripheryGPIOModuleImp + with sifive.blocks.devices.spi.HasPeripherySPIFlashModuleImp with icenet.CanHavePeripheryIceNICModuleImp with chipyard.example.CanHavePeripheryGCDModuleImp with freechips.rocketchip.util.DontTouch diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index ea0f610b..97cc0ba9 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -13,6 +13,7 @@ import freechips.rocketchip.util._ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ +import sifive.blocks.devices.spi._ import barstools.iocell.chisel._ @@ -88,10 +89,8 @@ object AddIOCells { def gpio(gpios: Seq[GPIOPortIO], genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[Seq[Analog]], Seq[Seq[IOCell]]) = { gpios.zipWithIndex.map({ case (gpio, i) => gpio.pins.zipWithIndex.map({ case (pin, j) => - val g = IO(Analog(1.W)) - g.suggestName("gpio_${i}_${j}") - val iocell = genFn() - iocell.suggestName(s"iocell_gpio_${i}_${j}") + val g = IO(Analog(1.W)).suggestName(s"gpio_${i}_${j}") + val iocell = genFn().suggestName(s"iocell_gpio_${i}_${j}") iocell.io.o := pin.o.oval iocell.io.oe := pin.o.oe iocell.io.ie := pin.o.ie @@ -115,6 +114,37 @@ object AddIOCells { }).unzip } + /** + * Add IO cells to a SiFive SPI devices and name the IO ports. + * @param spiPins A Seq of SPI port bundles + * @param basename The base name for this port (defaults to "spi") + * @param genFn A callable function to generate a DigitalGPIOCell module to use + * @return Returns a tuple of (A Seq of top-level SPIChipIO IOs; a 2D Seq of IOCell module references) + */ + def spi(spiPins: Seq[SPIPortIO], basename: String = "spi", genFn: () => DigitalGPIOCell = IOCell.genericGPIO): (Seq[SPIChipIO], Seq[Seq[IOCell]]) = { + spiPins.zipWithIndex.map({ case (s, i) => + val port = IO(new SPIChipIO(s.c.csWidth)).suggestName(s"${basename}_${i}") + val iocellBase = s"iocell_${basename}_${i}" + + // SCK and CS are unidirectional outputs + val sckIOs = IOCell.generateFromSignal(s.sck, port.sck, Some(s"${iocellBase}_sck")) + val csIOs = IOCell.generateFromSignal(s.cs, port.cs, Some(s"${iocellBase}_cs")) + + // DQ are bidirectional, so then need special treatment + val dqIOs = s.dq.zip(port.dq).zipWithIndex.map { case ((pin, ana), j) => + val iocell = genFn().suggestName(s"${iocellBase}_dq_${j}") + iocell.io.o := pin.o + iocell.io.oe := pin.oe + iocell.io.ie := true.B + pin.i := iocell.io.i + iocell.io.pad <> ana + iocell + } + + (port, dqIOs ++ csIOs ++ sckIOs) + }).unzip + } + /** * Add IO cells to a debug module and name the IO ports. * @param psd A PSDIO bundle @@ -172,6 +202,14 @@ class WithUARTAdapter extends OverrideIOBinder({ } }) +class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideIOBinder({ + (system: HasPeripherySPIFlashModuleImp) => { + val (ports, ioCells2d) = AddIOCells.spi(system.qspi, "qspi") + val harnessFn = (th: chipyard.TestHarness) => { SimSPIFlashModel.connect(ports, th.reset, rdOnly)(system.p); Nil } + Seq((ports, ioCells2d.flatten, Some(harnessFn))) + } +}) + class WithSimBlockDevice extends OverrideIOBinder({ (system: CanHavePeripheryBlockDeviceModuleImp) => system.connectSimBlockDevice(system.clock, system.reset.asBool); Nil }) diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index ac29c662..49d22385 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -165,6 +165,46 @@ class GCDAXI4BlackBoxRocketConfig extends Config( new freechips.rocketchip.system.BaseConfig) // DOC include end: GCDAXI4BlackBoxRocketConfig +class LargeSPIFlashROMRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithSPIFlash ++ // add the SPI flash controller + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class SmallSPIFlashRocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable) + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB) + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + class SimBlockDeviceRocketConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ diff --git a/generators/testchipip b/generators/testchipip index 5b3f2c96..888a4547 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 5b3f2c9654d4cb06a64e8ac5df864c706a07bda8 +Subproject commit 888a4547adbf6387da7fb79c85f2f75cdcca6534 diff --git a/generators/utilities/src/main/resources/csrc/emulator.cc b/generators/utilities/src/main/resources/csrc/emulator.cc index acec6005..6ff63d3e 100644 --- a/generators/utilities/src/main/resources/csrc/emulator.cc +++ b/generators/utilities/src/main/resources/csrc/emulator.cc @@ -38,8 +38,8 @@ extern remote_bitbang_t * jtag; extern int dramsim; static uint64_t trace_count = 0; -bool verbose; -bool done_reset; +bool verbose = false; +bool done_reset = false; void handle_sigterm(int sig) { @@ -282,6 +282,10 @@ done_processing: signal(SIGTERM, handle_sigterm); bool dump; + // start reset off low so a rising edge triggers async reset + tile->reset = 0; + tile->clock = 0; + tile->eval(); // reset for several cycles to handle pipelined reset for (int i = 0; i < 100; i++) { tile->reset = 1; diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch index eca5596d..af383b0f 100644 --- a/scripts/tutorial-patches/RocketConfigs.scala.patch +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -1,8 +1,8 @@ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -index bc1dab6..1d84129 100644 +index 49d2238..afaa36d 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -@@ -293,7 +293,7 @@ class Sha3RocketConfig extends Config( +@@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config( new chipyard.config.WithBootROM ++ new chipyard.config.WithUART ++ new chipyard.config.WithL2TLBs(1024) ++ diff --git a/tests/.gitignore b/tests/.gitignore index b8212fd8..5cbdb5a9 100644 --- a/tests/.gitignore +++ b/tests/.gitignore @@ -1,4 +1,5 @@ *.o *.riscv *.dump +*.img libgloss/ diff --git a/tests/Makefile b/tests/Makefile index 6f247e70..8754cbbc 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -5,12 +5,15 @@ LDFLAGS= -static include libgloss.mk -PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd spiflashread spiflashwrite + +spiflash.img: spiflash.py + python3 $< .DEFAULT_GOAL := default .PHONY: default -default: $(addsuffix .riscv,$(PROGRAMS)) +default: $(addsuffix .riscv,$(PROGRAMS)) spiflash.img .PHONY: dumps dumps: $(addsuffix .dump,$(PROGRAMS)) @@ -18,7 +21,7 @@ dumps: $(addsuffix .dump,$(PROGRAMS)) %.o: %.S $(GCC) $(CFLAGS) -D__ASSEMBLY__=1 -c $< -o $@ -%.o: %.c mmio.h +%.o: %.c mmio.h spiflash.h $(GCC) $(CFLAGS) -c $< -o $@ %.riscv: %.o $(libgloss) diff --git a/tests/spiflash.h b/tests/spiflash.h new file mode 100644 index 00000000..94b27e36 --- /dev/null +++ b/tests/spiflash.h @@ -0,0 +1,174 @@ +#ifndef __SPIFLASH_H__ +#define __SPIFLASH_H__ + +// These are configuration-dependent, but for the unit test we'll use the example config +#define SPIFLASH_BASE_MEM 0x20000000 +#define SPIFLASH_BASE_MEM_SIZE 0x10000000 + +#define SPIFLASH_BASE_CTRL 0x10040000 +// Only defining the registers we use; there are more +// Software control +#define SPIFLASH_OFFS_CSMODE 0x18 +#define SPIFLASH_OFFS_FMT 0x40 +#define SPIFLASH_OFFS_TXDATA 0x48 +#define SPIFLASH_OFFS_RXDATA 0x4c +// Hardware state machine control +#define SPIFLASH_OFFS_FLASH_EN 0x60 +#define SPIFLASH_OFFS_FFMT 0x64 + +// chip select modes +#define CSMODE_AUTO 0 +#define CSMODE_HOLD 2 +#define CSMODE_OFF 3 + +// SPI flash protocol settings +#define SPIFLASH_PROTO_SINGLE 0 +#define SPIFLASH_PROTO_DUAL 1 +#define SPIFLASH_PROTO_QUAD 2 + +// SPI flash IO settings +#define SPIFLASH_IODIR_RX 0 +#define SPIFLASH_IODIR_TX 1 + +// SPI flash endianness settings +#define SPIFLASH_ENDIAN_MSB 0 +#define SPIFLASH_ENDIAN_LSB 1 + +static uint8_t test_data[] = {0x13,0x37,0x00,0xff,0xaa,0x55,0xfa,0xce,0x0f,0xf0,0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef}; +static uint8_t test_len = 16; + +typedef union +{ + struct { + unsigned int proto : 2; + unsigned int endian : 1; + unsigned int iodir : 1; + unsigned int : 12; + unsigned int len : 4; + unsigned int : 12; + } fields; + uint32_t bits; +} spi_fmt; + +typedef union +{ + struct { + unsigned int cmd_en : 1; + unsigned int addr_len : 3; + unsigned int pad_cnt : 4; + unsigned int cmd_proto : 2; + unsigned int addr_proto : 2; + unsigned int data_proto : 2; + unsigned int : 2; + unsigned int cmd_code : 8; + unsigned int pad_code : 8; + } fields; + uint32_t bits; +} spiflash_ffmt; + +// send something to the SPI TX +void spi_data_write(uint8_t data) +{ + while (reg_read32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA) >= 0x80000000); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_TXDATA, (uint32_t)data); +} + +// configure the hardware flash controller +void configure_spiflash(spiflash_ffmt data) +{ + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FFMT, data.bits); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1); +} + +// write some data to the flash using software (there is no hardware write controller) +void write_spiflash(uint8_t *data, uint32_t len, uint32_t addr, uint8_t cmd, uint8_t abytes, uint8_t aproto, uint8_t dproto) +{ + + spi_fmt fmt; + fmt.fields.proto = SPIFLASH_PROTO_SINGLE; + fmt.fields.endian = SPIFLASH_ENDIAN_MSB; + fmt.fields.iodir = SPIFLASH_IODIR_TX; + fmt.fields.len = 8; + + uint32_t i; + + // Need to be out of flash mode + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 0); + + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits); + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_HOLD); + + spi_data_write(cmd); + + // need to wait a bit to flush the tx queue before changing fmt + for(i = 0; i < 0x100; i++) asm volatile ("nop"); + + fmt.fields.proto = aproto; + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits); + + for (i = abytes; i > 0; i--) + { + spi_data_write((uint8_t)(addr >> (i*8-8))); + } + + // need to wait a bit to flush the tx queue before changing fmt + for(i = 0; i < 0x100; i++) asm volatile ("nop"); + + fmt.fields.proto = dproto; + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FMT, fmt.bits); + + for (i = 0; i < len; i++) + { + spi_data_write(data[i]); + } + + // need to wait a bit to flush the tx queue before deasserting CS + for(i = 0; i < 0x100; i++) asm volatile ("nop"); + + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_CSMODE, CSMODE_OFF); + + // go back into flash read mode + reg_write32(SPIFLASH_BASE_CTRL + SPIFLASH_OFFS_FLASH_EN, 1); + +} + +// test that a large chunk of memory contains (0xdeadbeef - address) or 0 +int test_spiflash(uint32_t start, uint32_t size, uint8_t zero) +{ + uint32_t i; + + for (i = start; i < (start + size); i += 4) + { + uint32_t data = reg_read32(SPIFLASH_BASE_MEM + i); + uint32_t check = 0; + if (!zero) check = 0xdeadbeef - i; + if(data != check) + { + printf("Error reading address 0x%08x from SPI flash. Got 0x%08x, expected 0x%08x.\n", i, data, check); + return 1; + } + } + + return 0; +} + +// this is a variant of test_spiflash that only tests a small array of values +int check_write(uint8_t *check, uint32_t len, uint32_t addr) +{ + uint32_t i; + for (i = 0; i < len; i += 4) + { + uint32_t data = reg_read32(SPIFLASH_BASE_MEM + addr + i); + uint32_t check32 = ((uint32_t *)check)[i/4]; + if(check32 != data) + { + printf("Error reading address 0x%08x from SPI flash. Got 0x%02x, expected 0x%02x.\n", i + addr, data, check32); + return 1; + } + } + + return 0; +} + +#endif /* __SPIFLASH_H__ */ diff --git a/tests/spiflash.py b/tests/spiflash.py new file mode 100755 index 00000000..126cf1be --- /dev/null +++ b/tests/spiflash.py @@ -0,0 +1,11 @@ +#!/usr/bin/env python3 + +# Generates a binary file that the SPI test uses + +outfile = "spiflash.img" + +with open(outfile, 'wb') as f: + for i in range(0,0x100000,4): + check = 0xdeadbeef - i + f.write(check.to_bytes(4,'little')) + diff --git a/tests/spiflashread.c b/tests/spiflashread.c new file mode 100644 index 00000000..393faa55 --- /dev/null +++ b/tests/spiflashread.c @@ -0,0 +1,77 @@ +#include +#include + +#include "mmio.h" +#include "spiflash.h" + +int main(void) +{ + spiflash_ffmt ffmt; + ffmt.fields.cmd_en = 1; + ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model + ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow + ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands + ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.cmd_code = 0x13; // Slow read 4 byte + ffmt.fields.pad_code = 0x00; // Not used by our model + + printf("Testing SPI flash command 0x13...\n"); + configure_spiflash(ffmt); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x03...\n"); + ffmt.fields.cmd_code = 0x03; // Slow read 3 byte address + ffmt.fields.addr_len = 3; // 3 byte address + configure_spiflash(ffmt); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x0B...\n"); + ffmt.fields.cmd_code = 0x0B; // Fast read 3 byte address + ffmt.fields.pad_cnt = 8; // Needs to be 8 for fast read + configure_spiflash(ffmt); + if (test_spiflash(0x1000, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x0C...\n"); + ffmt.fields.cmd_code = 0x0C; // Fast read 4 byte address + ffmt.fields.addr_len = 4; // 4 byte address + configure_spiflash(ffmt); + if (test_spiflash(0x2340, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x6C...\n"); + ffmt.fields.cmd_code = 0x6C; // Fast read 4 byte address, quad data + ffmt.fields.data_proto = SPIFLASH_PROTO_QUAD; // Quad data + configure_spiflash(ffmt); + if (test_spiflash(0x410c, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0x6B...\n"); + ffmt.fields.cmd_code = 0x6B; // Fast read 3 byte address, quad data + ffmt.fields.addr_len = 3; + configure_spiflash(ffmt); + if (test_spiflash(0x5ff8, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0xEB...\n"); + ffmt.fields.cmd_code = 0xEB; // Fast read 3 byte address, quad data, quad addr + ffmt.fields.addr_proto = SPIFLASH_PROTO_QUAD; + configure_spiflash(ffmt); + if (test_spiflash(0x7c04, 0x100, 0)) return 1; + + printf("Testing SPI flash command 0xEC...\n"); + ffmt.fields.cmd_code = 0xEC; // Fast read 4 byte address, quad data, quad addr + ffmt.fields.addr_len = 4; + configure_spiflash(ffmt); + if (test_spiflash(0x9000, 0x100, 0)) return 1; + + printf("Testing SPI flash extended range...\n"); + // The provided memory image is only 1MiB, but the model has 16MiB of addressable space + // This should return 0 + if (test_spiflash(0x100000, 0x100, 1)) return 1; + + // This write should do nothing, so we can just re-test the first test + printf("Testing that the SPI is not writable...\n"); + write_spiflash(test_data, test_len, 0x0, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + return 0; + +} diff --git a/tests/spiflashwrite.c b/tests/spiflashwrite.c new file mode 100644 index 00000000..f9c17605 --- /dev/null +++ b/tests/spiflashwrite.c @@ -0,0 +1,55 @@ +#include +#include + +#include "mmio.h" +#include "spiflash.h" + +int main(void) +{ + spiflash_ffmt ffmt; + ffmt.fields.cmd_en = 1; + ffmt.fields.addr_len = 4; // Valid options are 3 or 4 for our model + ffmt.fields.pad_cnt = 0; // Our SPI flash model assumes 8 dummy cycles for fast reads, 0 for slow + ffmt.fields.cmd_proto = SPIFLASH_PROTO_SINGLE; // Our SPI flash model only supports single-bit commands + ffmt.fields.addr_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.data_proto = SPIFLASH_PROTO_SINGLE; // We support both single and quad + ffmt.fields.cmd_code = 0x13; // Slow read 4 byte + ffmt.fields.pad_code = 0x00; // Not used by our model + + // Test that we can read + printf("Testing SPI flash command 0x13...\n"); + configure_spiflash(ffmt); + if (test_spiflash(0x0, 0x100, 0)) return 1; + + // 0x02: 3 byte addr, single/single + printf("Testing SPI flash command 0x02...\n"); + write_spiflash(test_data, test_len, 0x200, 0x02, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE); + if (check_write(test_data, test_len, 0x200)) return 1; + + // 0x32: 3 byte addr, single/quad + printf("Testing SPI flash command 0x32...\n"); + write_spiflash(test_data, test_len, 0x300, 0x32, 3, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x300)) return 1; + + // 0x38: 3 byte addr, quad/quad + printf("Testing SPI flash command 0x38...\n"); + write_spiflash(test_data, test_len, 0x400, 0x38, 3, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x400)) return 1; + + // 0x12: 4 byte addr, single/single + printf("Testing SPI flash command 0x12...\n"); + write_spiflash(test_data, test_len, 0x500, 0x12, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_SINGLE); + if (check_write(test_data, test_len, 0x500)) return 1; + + // 0x34: 4 byte addr, single/quad + printf("Testing SPI flash command 0x34...\n"); + write_spiflash(test_data, test_len, 0x600, 0x34, 4, SPIFLASH_PROTO_SINGLE, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x600)) return 1; + + // 0x3E: 4 byte addr, quad/quad + printf("Testing SPI flash command 0x3E...\n"); + write_spiflash(test_data, test_len, 0x700, 0x3E, 4, SPIFLASH_PROTO_QUAD, SPIFLASH_PROTO_QUAD); + if (check_write(test_data, test_len, 0x700)) return 1; + + return 0; +} From 3f5a204fd0f7b280001e6a950430740c8542f9a6 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 16 May 2020 00:21:24 -0700 Subject: [PATCH 119/139] BOOM Bump w. Fromajo (#523) * [uart] add uart adapter | add uart + adapter to all configs * [uart] change pty define name | add uart to all configs that need it * [uart] default to 115200 baudrate * [dromajo] first working commit * [dromajo] bump boom for commit-width > 1 fix * [dromajo] adjust dromajo commits * [dromajo] bump boom * commit dromajo changes * extra * [dromajo] add block device to configs * rebump older modules * bump firesim * [chipyard] enable dromajo in midas level simulation * [testchipip] forgot to bump * get rid of breaking things * bump firesim * bump boom * Bump BOOM to ifu3 WIP * bump firesim * fix how memory is passed to dromajo * bump boom and firesim * fix merge issues * add dromajo cosim bridge in chipyard * move traceio back into testchipip (#488) * refer to testchipip traceio in firechip (#490) * Move TraceIO fragment to chipyard (#492) * fix chipyard dromajo bridge (#493) * Sboom dromajo bump (#501) * [FireChip] Use clock in BridgeBinders * [firesim] Update TraceGen BridgeBinder * [Firechip] Add support for Tile <-> Uncore rational division * [firesim] Update the multiclock test * [firechip] Commit some Eagle X-related mock configs * [firechip] Instantiate multiple TracerV bridges * [Firechip] Include reset in tracerv tokens * [TracerV] Drop the first token in comparison tests * [Firechip] Make reverse instruction order in trace printf * WARNING: Point at a fork of boom @ davidbiancolin * [firesim] Update ClockBridge API * Add Gemmini to README [ci skip] (#487) * [firechip] Isolate all firesim-multiclock stuff in a single file * add documentation on ring network and system bus * Bump firesim for CI * Bump FireSim * Bump testchipip to dev [ci skip] * Bump FireSim * [make] split up specific make vars/targets into frags (#499) * [make] split up specific make vars/targets into frags * [make] move dramsim and max-cycles into SIM_FLAGS * [misc] move ariane configs to configs/ folder * [dromajo] add dromajo * [dromajo] bump for new traceio changes * bump firesim * bump firesim * point to chipyard traceio * bump boom Co-authored-by: David Biancolin Co-authored-by: Howard Mao * Support Dromajo + TracerV configurations * [docs] add documentation for Dromajo in FireSim + Chipyard * add a bit more docs * [docs] bump docs * [firesim] dump artefacts in firesim * [firesim] update firesim * [testchipip] remove extraneous items in testchipip * [dromajo] prevent dromajo from breaking when params unset * update firesim, dromajo, and testchipip * [firesim] bump firesim * [firesim] bump firesim * [misc] bump firesim and testchipip for reviewer comments * remove WithNoGPIO fragment * bump firesim * bump dromajo boom config * bump firesim * generate artefacts in firesim testsuite Co-authored-by: abejgonzalez Co-authored-by: Abraham Gonzalez Co-authored-by: David Biancolin Co-authored-by: Howard Mao --- .circleci/run-firesim-scala-tests.sh | 2 + .circleci/run-midasexamples-tests.sh | 4 ++ .gitmodules | 3 + build.sbt | 2 +- common.mk | 1 + docs/Advanced-Concepts/Debugging-RTL.rst | 25 +++++++- docs/Chipyard-Basics/Chipyard-Components.rst | 4 ++ docs/Tools/Dromajo.rst | 22 +++++++ docs/Tools/index.rst | 2 +- generators/boom | 2 +- .../src/main/scala/ConfigFragments.scala | 8 ++- .../chipyard/src/main/scala/IOBinders.scala | 8 +++ .../chipyard/src/main/scala/Subsystem.scala | 25 ++++++++ .../src/main/scala/config/BoomConfigs.scala | 21 +++++++ .../src/main/scala/BridgeBinders.scala | 17 ++++-- .../firechip/src/main/scala/FireSim.scala | 1 + .../src/main/scala/FireSimMulticlockPOC.scala | 1 + .../src/main/scala/TargetConfigs.scala | 10 +--- .../src/test/scala/ScalaTestSuite.scala | 3 +- generators/testchipip | 2 +- generators/tracegen/src/main/scala/Tile.scala | 13 +++- scripts/build-toolchains.sh | 3 + sims/firesim | 2 +- tools/dromajo/dromajo-src | 1 + tools/dromajo/dromajo.mk | 59 +++++++++++++++++++ 25 files changed, 217 insertions(+), 24 deletions(-) create mode 100644 docs/Tools/Dromajo.rst create mode 160000 tools/dromajo/dromajo-src create mode 100644 tools/dromajo/dromajo.mk diff --git a/.circleci/run-firesim-scala-tests.sh b/.circleci/run-firesim-scala-tests.sh index 93c4561d..3e2bb87f 100755 --- a/.circleci/run-firesim-scala-tests.sh +++ b/.circleci/run-firesim-scala-tests.sh @@ -22,6 +22,8 @@ cd $LOCAL_CHIPYARD_DIR/sims/firesim ./scripts/build-libdwarf.sh cd $LOCAL_CHIPYARD_DIR +make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src + # set stricthostkeychecking to no (must happen before rsync) run "echo \"Ping $SERVER\"" diff --git a/.circleci/run-midasexamples-tests.sh b/.circleci/run-midasexamples-tests.sh index 467dc0e9..092d011e 100755 --- a/.circleci/run-midasexamples-tests.sh +++ b/.circleci/run-midasexamples-tests.sh @@ -12,6 +12,10 @@ trap clean EXIT cd $LOCAL_CHIPYARD_DIR ./scripts/init-submodules-no-riscv-tools.sh + +# build libdromajo_cosim +make -C $LOCAL_CHIPYARD_DIR/tools/dromajo/dromajo-src/src + cd sims/firesim/sim/midas # set stricthostkeychecking to no (must happen before rsync) diff --git a/.gitmodules b/.gitmodules index 34846d61..04f1a20e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -119,3 +119,6 @@ [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git +[submodule "tools/dromajo/dromajo-src"] + path = tools/dromajo/dromajo-src + url = https://github.com/abejgonzalez/dromajo.git diff --git a/build.sbt b/build.sbt index a87496c9..8cf8e688 100644 --- a/build.sbt +++ b/build.sbt @@ -147,7 +147,7 @@ lazy val hwacha = (project in file("generators/hwacha")) .dependsOn(rocketchip) .settings(commonSettings) -lazy val boom = (project in file("generators/boom")) +lazy val boom = conditionalDependsOn(project in file("generators/boom")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/common.mk b/common.mk index e9248953..991a8db6 100644 --- a/common.mk +++ b/common.mk @@ -14,6 +14,7 @@ SHELL=/bin/bash ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk +include $(base_dir)/tools/dromajo/dromajo.mk ######################################################################################### # Prerequisite lists diff --git a/docs/Advanced-Concepts/Debugging-RTL.rst b/docs/Advanced-Concepts/Debugging-RTL.rst index df1c1c55..86e5ced3 100644 --- a/docs/Advanced-Concepts/Debugging-RTL.rst +++ b/docs/Advanced-Concepts/Debugging-RTL.rst @@ -86,9 +86,32 @@ identical program behavior. The torture utility can also be configured to run continuously for stress-testing. The torture utility exists within the ``utilities`` directory. +Dromajo Co-simulation for BOOM designs +-------------------------------------- +Dromajo co-simulation is setup to work when two config. fragments are added to a BOOM config. +First, a ``chipyard.config.WithTraceIO`` config. fragment must be added so that BOOM's traceport is enabled. +Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config. fragment must be added to +connect the Dromajo co-simulator to the traceport. +Once both config. fragments are added Dromajo should be enabled. + +To build/run Dromajo with a BOOM design, run your configuration the following make commands: + +.. code-block:: shell + + # build the default Dromajo BOOM config. without waveform dumps + # replace "DromajoBoomConfig" with your particular config + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 + + # run a simulation with Dromajo + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary + +.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. + +.. warning:: Dromajo currently only works in VCS simulation and FireSim. + Firesim Debugging --------------------------- -Chisel printfs, asserts, and waveform generation are also available in FireSim +Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim FPGA-accelerated simulation. See the FireSim `documentation `__ for more detail. diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index d3ec9a95..7a89e93a 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -79,6 +79,10 @@ Tools **Dsptools** A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). +**Dromajo** + A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technology. + See :ref:`Dromajo` for more information. + Toolchains ------------------------------------------- diff --git a/docs/Tools/Dromajo.rst b/docs/Tools/Dromajo.rst new file mode 100644 index 00000000..2266bac1 --- /dev/null +++ b/docs/Tools/Dromajo.rst @@ -0,0 +1,22 @@ +Dromajo +=============================== + +`Dromajo `__ is a RV64GC functional simulator designed for co-simulation. +To use it as a co-simulator, it requires you to pass the committed trace of instructions coming from the core into the tool. +Within Chipyard, this is done by connecting to the `TracePort`` signals that are piped to the top level of the DUT. +While the Rocket core does have a `TracePort`, it does not provide the committed write data that Dromajo requires. +Thus, Dromajo uses the `ExtendedTracePort` only probided by BOOM (BOOM is the only core that supports Dromajo co-simulation). +An example of a divergence and Dromajo's printout is shown below. + +.. code-block:: shell + + [error] EMU PC ffffffe001055d84, DUT PC ffffffe001055d84 + [error] EMU INSN 14102973, DUT INSN 14102973 + [error] EMU WDATA 00000000000220d6, DUT WDATA 00000000000220d4 + [error] EMU MSTATUS a000000a0, DUT MSTATUS 00000000 + [error] DUT pending exception -1 pending interrupt -1 + +Dromajo shows the divergence compared to simulation (PC, inst, inst-bits, write data, etc) and also provides the register state on failure. +It is useful to catch bugs that affect architectural state before a simulation hangs or crashes. + +To use Dromajo with BOOM, refer to :ref:`Debugging RTL` section on Dromajo. diff --git a/docs/Tools/index.rst b/docs/Tools/index.rst index 09fd0d04..fecb2043 100644 --- a/docs/Tools/index.rst +++ b/docs/Tools/index.rst @@ -14,4 +14,4 @@ The following pages will introduce them, and how we can use them in order to gen Chisel-Testers Dsptools Barstools - + Dromajo diff --git a/generators/boom b/generators/boom index d0077cff..8c4ac6fd 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit d0077cff74140153e314f05f631c5e07b0d694ea +Subproject commit 8c4ac6fd40b455387cec369080b9b47d6fd1466e diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index c2fec56f..69cedb6f 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams import freechips.rocketchip.util.{AsyncResetReg} import boom.common.{BoomTilesKey} - +import ariane.{ArianeTilesKey} import testchipip._ import hwacha.{Hwacha} @@ -153,3 +153,9 @@ class WithControlCore extends Config((site, here, up) => { ) case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1) }) + +class WithTraceIO extends Config((site, here, up) => { + case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) + case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) + case TracePortKey => Some(TracePortParams()) +}) diff --git a/generators/chipyard/src/main/scala/IOBinders.scala b/generators/chipyard/src/main/scala/IOBinders.scala index 97cc0ba9..4c27a65a 100644 --- a/generators/chipyard/src/main/scala/IOBinders.scala +++ b/generators/chipyard/src/main/scala/IOBinders.scala @@ -351,4 +351,12 @@ class WithTraceGenSuccessBinder extends OverrideIOBinder({ } }) +class WithSimDromajoBridge extends ComposeIOBinder({ + (system: CanHaveTraceIOModuleImp) => { + system.traceIO match { case Some(t) => t.traces.map(tileTrace => SimDromajoBridge(tileTrace)(system.p)) } + Nil + } +}) + + } /* end package object */ diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 8fe0871b..4dfa7d73 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -104,4 +104,29 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule // create file with boom params ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) + + // Generate C header with relevant information for Dromajo + // THIS IS INCLUDED IN THE `dromajo_params.h` header file + var dromajoParams: String = "" + dromajoParams += "#ifndef DROMAJO_PARAMS_H" + dromajoParams += "\n#define DROMAJO_PARAMS_H" + dromajoParams += "\n\n" + "#define DROMAJO_RESET_VECTOR " + "\"" + "0x" + f"${p(BootROMParams).hang}%X" + "\"" + dromajoParams += "\n" + "#define DROMAJO_MMIO_START " + "\"" + "0x" + f"${p(BootROMParams).address + p(BootROMParams).size}%X" + "\"" + p(ExtMem) map { eP => + dromajoParams += "\n" + "#define DROMAJO_MMIO_END " + "\"" + "0x" + f"${eP.master.base}%X" + "\"" + // dromajo memory is in MiB chunks + dromajoParams += "\n" + "#define DROMAJO_MEM_SIZE " + "\"" + "0x" + f"${eP.master.size >> 20}%X" + "\"" + } + p(PLICKey) map { pP => + dromajoParams += "\n" + "#define DROMAJO_PLIC_BASE " + "\"" + "0x" + f"${pP.baseAddress}%X" + "\"" + dromajoParams += "\n" + "#define DROMAJO_PLIC_SIZE " + "\"" + "0x" + f"${PLICConsts.size(pP.maxHarts)}%X" + "\"" + } + p(CLINTKey) map { cP => + dromajoParams += "\n" + "#define DROMAJO_CLINT_BASE " + "\"" + "0x" + f"${cP.baseAddress}%X" + "\"" + dromajoParams += "\n" + "#define DROMAJO_CLINT_SIZE " + "\"" + "0x" + f"${CLINTConsts.size}%X" + "\"" + } + dromajoParams += "\n\n#endif" + + ElaborationArtefacts.add("""dromajo_params.h""", dromajoParams) + } diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala index 48a9126e..e8358e95 100644 --- a/generators/chipyard/src/main/scala/config/BoomConfigs.scala +++ b/generators/chipyard/src/main/scala/config/BoomConfigs.scala @@ -163,3 +163,24 @@ class LoopbackNICLargeBoomConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) +class DromajoBoomConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new chipyard.iobinders.WithSimDromajoBridge ++ // attach Dromajo + new testchipip.WithTSI ++ + new chipyard.config.WithTraceIO ++ // enable the traceio + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new boom.common.WithSmallBooms ++ + new boom.common.WithNBoomCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 043f1f4e..772d0b8d 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -13,7 +13,7 @@ import freechips.rocketchip.tile.{RocketTile} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} -import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp} +import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp} import icenet.CanHavePeripheryIceNICModuleImp import junctions.{NastiKey, NastiParameters} @@ -27,7 +27,8 @@ import ariane.ArianeTile import boom.common.{BoomTile} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} -import chipyard.HasChipyardTilesModuleImp +import chipyard.{HasChipyardTilesModuleImp} +import testchipip.{CanHaveTraceIOModuleImp} object MainMemoryConsts { val regionNamePrefix = "MainMemory" @@ -72,12 +73,20 @@ class WithFASEDBridge extends OverrideIOBinder({ } }) -class WithTracerVBridge extends OverrideIOBinder({ +class WithTracerVBridge extends ComposeIOBinder({ (system: CanHaveTraceIOModuleImp) => system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil }) + +class WithDromajoBridge extends ComposeIOBinder({ + (system: CanHaveTraceIOModuleImp) => { + system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil + } +}) + + class WithTraceGenBridge extends OverrideIOBinder({ (system: HasTraceGenTilesModuleImp) => GroundTestBridge(system.clock, system.success)(system.p); Nil @@ -116,7 +125,7 @@ class WithTiedOffSystemDebug extends OverrideIOBinder({ (system: HasPeripheryDebugModuleImp) => { Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p) // tieoffDebug doesn't actually tie everything off :/ - system.debug.foreach { d => + system.debug.foreach { d => d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare }) d.dmactiveAck := DontCare } diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 923e1cd1..50f6f658 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -45,6 +45,7 @@ class FireSim(implicit val p: Parameters) extends RawModule { })) (lazyModule, Module(lazyModule.module)) } + val peekPokeBridge = PeekPokeBridge(clock, reset) // A Seq of partial functions that will instantiate the right bridge only // if that Mixin trait is present in the target's LazyModule class instance diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index fdc2939f..758cb055 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -79,6 +79,7 @@ class FiresimMulticlockTop(implicit p: Parameters) extends chipyard.DigitalTop override lazy val module = new FiresimMulticlockTopModule(this) } + class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.DigitalTopModule(l) with HasFireSimClockingImp // Harness Definition diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 63199c0e..1a0dcd69 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -73,13 +73,6 @@ class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) -// Enables tracing on all cores -class WithTraceIO extends Config((site, here, up) => { - case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) - case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) - case TracePortKey => Some(TracePortParams()) -}) - // Tweaks that are generally applied to all firesim configs class WithFireSimConfigTweaks extends Config( @@ -92,7 +85,7 @@ class WithFireSimConfigTweaks extends Config( // Required*: Removes thousands of assertions that would be synthesized (* pending PriorityMux bugfix) new WithoutTLMonitors ++ // Optional: Adds IO to attach tracerV bridges - new WithTraceIO ++ + new chipyard.config.WithTraceIO ++ // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 32 GiB on F1) new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // Required: Adds IO to attach SerialBridge. The SerialBridges is responsible @@ -143,7 +136,6 @@ class FireSimLargeBoomConfig extends Config( new WithFireSimConfigTweaks ++ new chipyard.LargeBoomConfig) - //******************************************************************** // Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig //******************************************************************** diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index cf2358d9..3ab4162c 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -75,7 +75,7 @@ abstract class FireSimTestSuite( case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv" case _ => "" } - val results = suite.names.toSeq sliding (N, N) map { t => + val results = suite.names.toSeq sliding (N, N) map { t => val subresults = t map (name => Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug))) Await result (Future sequence subresults, Duration.Inf) @@ -130,6 +130,7 @@ abstract class FireSimTestSuite( mkdirs elaborate generateTestSuiteMakefrags + generateArtefacts runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) diff --git a/generators/testchipip b/generators/testchipip index 888a4547..e43e818f 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 888a4547adbf6387da7fb79c85f2f75cdcca6534 +Subproject commit e43e818f443764cb1a1bdaa243b5adc795083217 diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala index 28974e1b..d395211f 100644 --- a/generators/tracegen/src/main/scala/Tile.scala +++ b/generators/tracegen/src/main/scala/Tile.scala @@ -86,7 +86,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) io.lsu.dis_uops(0).valid := io.tracegen.req.fire() io.lsu.dis_uops(0).bits := tracegen_uop - + when (io.tracegen.req.fire()) { rob_tail := WrapInc(rob_tail, rob_sz) rob_bsy(rob_tail) := true.B @@ -165,8 +165,15 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) io.lsu.rob_pnr_idx := rob_tail io.lsu.commit_load_at_rob_head := false.B - io.lsu.brinfo := DontCare - io.lsu.brinfo.valid := false.B + io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.exu.BrUpdateMasks) + io.lsu.brupdate.b2.uop := DontCare + io.lsu.brupdate.b2.mispredict := false.B + io.lsu.brupdate.b2.taken := false.B + io.lsu.brupdate.b2.cfi_type := 0.U + io.lsu.brupdate.b2.pc_sel := 0.U + io.lsu.brupdate.b2.jalr_target := 0.U + io.lsu.brupdate.b2.target_offset := 0.S(2.W) + io.lsu.rob_head_idx := rob_head diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index b5d767c0..cbe15161 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -130,6 +130,9 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu +# make Dromajo +make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src + cd "$RDIR" # create specific env.sh diff --git a/sims/firesim b/sims/firesim index 4ec7325a..4e94c1a0 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4ec7325ac60d3dd5862798cabb823e446040b90e +Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a diff --git a/tools/dromajo/dromajo-src b/tools/dromajo/dromajo-src new file mode 160000 index 00000000..56e2ff46 --- /dev/null +++ b/tools/dromajo/dromajo-src @@ -0,0 +1 @@ +Subproject commit 56e2ff46b70521916c362799517f4ed8e67e9e88 diff --git a/tools/dromajo/dromajo.mk b/tools/dromajo/dromajo.mk new file mode 100644 index 00000000..067faa2f --- /dev/null +++ b/tools/dromajo/dromajo.mk @@ -0,0 +1,59 @@ +############################################################## +# extra variables/targets ingested by the chipyard make system +############################################################## + +DROMAJO_DIR = $(base_dir)/tools/dromajo/dromajo-src/src +DROMAJO_LIB_NAME = dromajo_cosim +DROMAJO_LIB = $(DROMAJO_DIR)/lib$(DROMAJO_LIB_NAME).a + +# Dromajo assumes using the default bootrom +DROMAJO_ROM = $(base_dir)/bootrom/bootrom.rv64.img + +DTS_FILE = $(build_dir)/$(long_name).dts +DROMAJO_DTB = $(build_dir)/$(long_name).dtb + +$(DTS_FILE): $(FIRRTL_FILE) + +$(DROMAJO_DTB): $(DTS_FILE) + dtc -I dts -O dtb -o $(DROMAJO_DTB) $(DTS_FILE) + +DROMAJO_SRCS = $(call lookup_srcs,$(DROMAJO_DIR),cc) $(call lookup_srcs,$(DROMAJO_DIR),h) + +$(DROMAJO_LIB): $(DROMAJO_SRCS) + $(MAKE) -C $(DROMAJO_DIR) + +# depending on where the simulation is done, use the auto-variable or the hardcoded defined one +ifeq ($(BINARY),) +DROMAJO_BIN = $(<) +else +DROMAJO_BIN = $(BINARY) +endif + +DROMAJO_FLAGS = +drj_dtb=$(DROMAJO_DTB) +drj_rom=$(DROMAJO_ROM) +drj_bin=$(DROMAJO_BIN) + +DROMAJO_PARAMS_FILE = $(build_dir)/$(long_name).dromajo_params.h +DROMAJO_PARAMS_SYMLINK = $(build_dir)/dromajo_params.h + +$(DROMAJO_PARAMS_FILE): $(FIRRTL_FILE) + +$(DROMAJO_PARAMS_SYMLINK): $(DROMAJO_PARAMS_FILE) + rm -rf $(DROMAJO_PARAMS_SYMLINK) + ln -s $(DROMAJO_PARAMS_FILE) $(DROMAJO_PARAMS_SYMLINK) + +################################################################## +# THE FOLLOWING MUST BE += operators +################################################################## + +# simargs needed (i.e. like +drj_test=hello) +ifdef ENABLE_DROMAJO +EXTRA_SIM_FLAGS += $(DROMAJO_FLAGS) + +# CC flags needed for all simulations +EXTRA_SIM_CC_FLAGS += -I$(DROMAJO_DIR) + +# sourced needed for simulation +EXTRA_SIM_SOURCES += $(DROMAJO_LIB) + +# requirements needed for simulation +EXTRA_SIM_REQS += $(DROMAJO_PARAMS_SYMLINK) $(DROMAJO_LIB) $(DROMAJO_DTB) +endif From 85b555dbcefba32ce286c133951b47cf85faf63c Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Sat, 16 May 2020 12:22:30 -0700 Subject: [PATCH 120/139] NVDLA Integration + Cleanup Ariane Preprocessing (#505) * [nvdla] initial nvdla integration * [nvdla] add firesim configs * [nvdla] re-add accidentally deleted line * [nvdla] works on master with small * [nvdla] use master branch of nvdla * [nvdla] remove extra sources * [nvdla] bump * [nvdla + ariane] bump and use insert-includes for pre-processing * [nvdla] add ci | remove target configs in FireChip | update naming * [nvdla] bump nvdla | fix ci run-tests error * [nvdla] re-enable PCWM-L error | fix/update makefile(s) * [nvdla] bump nvdla fragments in FireChip * [misc] bump tutorial patches * [chipyard] remove extra import * [nvdla] bump nvdla for pbus [ci skip] * [nvdla] update firemarshal and add nvdla workload * [nvdla] bump nvdla-workload * [nvdla] bump hw * [docs] add basic documentation * [docs] adjustments to documentation * [misc] update docs | bump firesim with recipe * [misc] disable error on warnings in verilator | bump number width to match RC * [docs] fix doc build error * [verilator] move no fail on warning to be global * [ci skip] [nvdla] bump submodule urls * [misc] move firesim specific configs into nvdla dir [ci skip] * [nvdla] fix run-tests in ci * update RC configs | bump marshal | bump nvdla-workload * [nvdla] bump nvdla-workload [ci skip] * add topology mixin to nvdla configs * update tutorial patches --- .circleci/config.yml | 18 + .circleci/defaults.sh | 1 + .circleci/run-tests.sh | 4 + .gitmodules | 6 + README.md | 3 +- build.sbt | 6 +- common.mk | 1 + docs/Generators/NVDLA.rst | 16 + docs/Generators/index.rst | 1 + generators/ariane | 2 +- .../src/main/scala/ConfigFragments.scala | 7 - .../chipyard/src/main/scala/DigitalTop.scala | 1 + .../src/main/scala/config/RocketConfigs.scala | 38 + .../src/main/scala/TargetConfigs.scala | 7 +- generators/nvdla | 1 + scripts/insert-includes.py | 51 + .../RocketConfigs.scala.patch | 2 +- scripts/tutorial-patches/build.sbt.patch | 8 +- sims/vcs/Makefile | 8 +- sims/verilator/Makefile | 3 +- software/firemarshal | 2 +- software/nvdla-workload | 1 + tests/Makefile | 2 +- tests/nvdla.c | 468 ++ tests/nvdla.h | 6433 +++++++++++++++++ 25 files changed, 7063 insertions(+), 27 deletions(-) create mode 100644 docs/Generators/NVDLA.rst create mode 160000 generators/nvdla create mode 100755 scripts/insert-includes.py create mode 160000 software/nvdla-workload create mode 100644 tests/nvdla.c create mode 100644 tests/nvdla.h diff --git a/.circleci/config.yml b/.circleci/config.yml index 8e88f7eb..5361a944 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,6 +262,11 @@ jobs: steps: - prepare-rtl: project-key: "testchipip" + prepare-chipyard-nvdla: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-nvdla" prepare-chipyard-spiflashwrite: executor: main-env steps: @@ -368,6 +373,11 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" + chipyard-nvdla-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-nvdla" icenet-run-tests: executor: main-env steps: @@ -484,6 +494,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-nvdla: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-chipyard-spiflashwrite: requires: - install-riscv-toolchain @@ -567,6 +582,9 @@ workflows: requires: - prepare-chipyard-ariane + - chipyard-nvdla-run-tests: + requires: + - prepare-chipyard-nvdla - icenet-run-tests: requires: - prepare-icenet diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e944e7fd..d9699df8 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -56,6 +56,7 @@ mapping["chipyard-spiflashread"]="SUB_PROJECT=chipyard CONFIG=LargeSPIFlashROMRo mapping["chipyard-spiflashwrite"]="SUB_PROJECT=chipyard CONFIG=SmallSPIFlashRocketConfig" mapping["tracegen"]="SUB_PROJECT=chipyard CONFIG=NonBlockingTraceGenL2Config TOP=TraceGenSystem" mapping["tracegen-boom"]="SUB_PROJECT=chipyard CONFIG=BoomTraceGenConfig TOP=TraceGenSystem" +mapping["chipyard-nvdla"]="SUB_PROJECT=chipyard CONFIG=SmallNVDLARocketConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index c7794173..19a0e566 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -80,6 +80,10 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + chipyard-nvdla) + make -C $LOCAL_CHIPYARD_DIR/tests + make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary + ;; icenet) make run-none-fast -C $LOCAL_SIM_DIR ${mapping[$1]} ;; diff --git a/.gitmodules b/.gitmodules index 04f1a20e..cae791dd 100644 --- a/.gitmodules +++ b/.gitmodules @@ -119,6 +119,12 @@ [submodule "tools/DRAMSim2"] path = tools/DRAMSim2 url = https://github.com/firesim/DRAMSim2.git +[submodule "generators/nvdla"] + path = generators/nvdla + url = https://github.com/ucb-bar/nvdla-wrapper.git +[submodule "software/nvdla-workload"] + path = software/nvdla-workload + url = https://github.com/ucb-bar/nvdla-workload.git [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/abejgonzalez/dromajo.git diff --git a/README.md b/README.md index 8d4cccc5..5d44edb3 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ To get started using Chipyard, see the documentation on the Chipyard documentati Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators. -Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini]), memory systems, and additional peripherals and tooling to help create a full featured SoC. +Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [Ariane][ariane]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]). Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley]. @@ -65,3 +65,4 @@ These publications cover many of the internal components used in Chipyard. Howev [firemarshal]: https://github.com/firesim/FireMarshal/ [ariane]: https://github.com/pulp-platform/ariane/ [gemmini]: https://github.com/ucb-bar/gemmini +[nvdla]: http://nvdla.org/ diff --git a/build.sbt b/build.sbt index 8cf8e688..17fdbba5 100644 --- a/build.sbt +++ b/build.sbt @@ -129,7 +129,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen, ariane) + gemmini, icenet, tracegen, ariane, nvdla) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -163,6 +163,10 @@ lazy val gemmini = (project in file("generators/gemmini")) .dependsOn(rocketchip, chisel_testers, testchipip) .settings(commonSettings) +lazy val nvdla = (project in file("generators/nvdla")) + .dependsOn(rocketchip) + .settings(commonSettings) + lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/")) .dependsOn(chisel_testers, chipyard) .settings(commonSettings) diff --git a/common.mk b/common.mk index 991a8db6..f07342de 100644 --- a/common.mk +++ b/common.mk @@ -14,6 +14,7 @@ SHELL=/bin/bash ######################################################################################### include $(base_dir)/generators/ariane/ariane.mk include $(base_dir)/generators/tracegen/tracegen.mk +include $(base_dir)/generators/nvdla/nvdla.mk include $(base_dir)/tools/dromajo/dromajo.mk ######################################################################################### diff --git a/docs/Generators/NVDLA.rst b/docs/Generators/NVDLA.rst new file mode 100644 index 00000000..d3e85286 --- /dev/null +++ b/docs/Generators/NVDLA.rst @@ -0,0 +1,16 @@ +NVDLA +==================================== + +`NVDLA `_ is an open-source deep learning accelerator developed by NVIDIA. +The `NVDLA` is attached as a TileLink peripheral so it can be used as a component within the `Rocket Chip SoC generator`. +The accelerator by itself exposes an AXI memory interface (or two if you use the "Large" configuration), a control interface, and an interrupt line. +The main way to use the accelerator in Chipyard is to use the `NVDLA SW repository `_ that was ported to work on FireSim Linux. +However, you can also use the accelerator in baremetal simulations (refer to ``tests/nvdla.c``). + +For more information on both the HW architecture and the SW, please visit their `website `_. + +NVDLA Software with FireMarshal +------------------------------- + +Located at ``software/nvdla-workload`` is a FireMarshal-based workload to boot Linux with the proper NVDLA drivers. +Refer to that ``README.md`` for more information on how to run a simulation. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index 675318d9..be9c5e55 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -28,4 +28,5 @@ so changes to the generators themselves will automatically be used when building SiFive-Generators SHA3 Ariane + NVDLA diff --git a/generators/ariane b/generators/ariane index 66cbcd01..d914fc8f 160000 --- a/generators/ariane +++ b/generators/ariane @@ -1 +1 @@ -Subproject commit 66cbcd0115f8f4e2abb38684532ec945622adcae +Subproject commit d914fc8f0320ba5b087d515b25baf98959b0facb diff --git a/generators/chipyard/src/main/scala/ConfigFragments.scala b/generators/chipyard/src/main/scala/ConfigFragments.scala index 69cedb6f..72eaa414 100644 --- a/generators/chipyard/src/main/scala/ConfigFragments.scala +++ b/generators/chipyard/src/main/scala/ConfigFragments.scala @@ -72,7 +72,6 @@ class WithTracegenSystem extends Config((site, here, up) => { case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) }) - class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) => r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length)) @@ -83,12 +82,6 @@ class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size) }) - - -// ------------------ -// Multi-RoCC Support -// ------------------ - /** * Map from a hartId to a particular RoCC accelerator */ diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index e8fb4f4c..a61594f2 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -23,6 +23,7 @@ class DigitalTop(implicit p: Parameters) extends System with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget + with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA { override lazy val module = new DigitalTopModule(this) } diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 49d22385..f29c5804 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -425,3 +425,41 @@ class RingSystemBusRocketConfig extends Config( new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.system.BaseConfig) // DOC include end: RingSystemBusRocket + +class SmallNVDLARocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new nvidia.blocks.dla.WithNVDLA("small") ++ // add a small NVDLA + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class LargeNVDLARocketConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithBlackBoxSimMem ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new chipyard.config.WithL2TLBs(1024) ++ + new nvidia.blocks.dla.WithNVDLA("large", true) ++ // add a large NVDLA with synth. rams + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new freechips.rocketchip.subsystem.WithNBigCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 1a0dcd69..63b4d2fe 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -44,14 +44,12 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) }) - class WithPerfCounters extends Config((site, here, up) => { case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( core = tile.core.copy(nPerfCounters = 29) )) }) - // Disables clock-gating; doesn't play nice with our FAME-1 pass class WithoutClockGating extends Config((site, here, up) => { case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) @@ -63,7 +61,6 @@ class WithScalaTestFeatures extends Config((site, here, up) => { case TracePortKey => up(TracePortKey, site).map(_.copy(print = true)) }) - // FASED Config Aliases. This to enable config generation via "_" concatenation // which requires that all config classes be defined in the same package class DDR3FRFCFS extends FRFCFS16GBQuadRank @@ -71,7 +68,9 @@ class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) - +// Adds a small/large NVDLA to the system +class WithNVDLALarge extends nvidia.blocks.dla.WithNVDLA("large") +class WithNVDLASmall extends nvidia.blocks.dla.WithNVDLA("small") // Tweaks that are generally applied to all firesim configs diff --git a/generators/nvdla b/generators/nvdla new file mode 160000 index 00000000..b2b78c9f --- /dev/null +++ b/generators/nvdla @@ -0,0 +1 @@ +Subproject commit b2b78c9f892a6196634eb3f1fbc443436c897a00 diff --git a/scripts/insert-includes.py b/scripts/insert-includes.py new file mode 100755 index 00000000..1e8a43ac --- /dev/null +++ b/scripts/insert-includes.py @@ -0,0 +1,51 @@ +#!/usr/bin/python + +# replaces a `include with the full include file +# +# args +# $1 - file to remove includes from +# $2 - file to write output to +# $3 - list of directories to search for includes in (note: NON-RECURSIVE must specify all dirs) +# includes are found relative to this path +# this is equivalent to something like +incdir+ + +import sys +import re +import os + +inVlog = sys.argv[1] +outVlog = sys.argv[2] +print("[INFO] Replaces includes from: " + str(inVlog)) + +if inVlog == outVlog: + sys.exit("[ERROR] The input and output file cannot be the same.") + +# add directories to search list +incDirs = sys.argv[3:] +print("[INFO] Searching following dirs for includes: " + str(incDirs)) + +# open file +with open(inVlog, 'r') as inFile: + with open(outVlog, 'w') as outFile: + # for each include found, search through all dirs and replace if found, error if not + for num, line in enumerate(inFile, 1): + match = re.match(r"^ *`include +\"(.*)\"", line) + if match: + # search for include and replace + found = False + for d in incDirs: + potentialIncFileName = d + "/" + match.group(1) + if os.path.exists(potentialIncFileName): + found = True + with open(potentialIncFileName, 'r') as incFile: + for iline in incFile: + outFile.write(iline) + break + + # must find something to include with + if not found: + sys.exit("[ERROR] Couldn't replace include \"" + str(match.group(1)) + "\" found on line " + str(num)) + else: + outFile.write(line) + +print("[INFO] Success. Writing output to: " + str(outVlog)) diff --git a/scripts/tutorial-patches/RocketConfigs.scala.patch b/scripts/tutorial-patches/RocketConfigs.scala.patch index af383b0f..cc9910c7 100644 --- a/scripts/tutorial-patches/RocketConfigs.scala.patch +++ b/scripts/tutorial-patches/RocketConfigs.scala.patch @@ -1,5 +1,5 @@ diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala -index 49d2238..afaa36d 100644 +index f29c580..0bd36ca 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -333,7 +333,7 @@ class Sha3RocketConfig extends Config( diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 6f20a3ce..40e773fe 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -1,17 +1,17 @@ diff --git a/build.sbt b/build.sbt -index a633066..3df8b74 100644 +index 0c4581f..ff0597c 100644 --- a/build.sbt +++ b/build.sbt -@@ -124,7 +124,7 @@ lazy val testchipip = (project in file("generators/testchipip")) +@@ -128,7 +128,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/")) lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches - gemmini, icenet, tracegen, ariane) + gemmini, icenet, tracegen, ariane, nvdla) .settings(commonSettings) -@@ -151,9 +151,9 @@ lazy val ariane = (project in file("generators/ariane")) +@@ -155,9 +155,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index f5b7e5db..80e5a1a8 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -55,18 +55,16 @@ VCS_CC_OPTS = \ VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ - -error=PCWM-L \ -timescale=1ns/1ps \ -quiet \ -q \ +rad \ - +v2k \ +vcs+lic+wait \ +vc+list \ -error=noZMMCM \ - -assert svaext \ - -sverilog \ - +libext+.v \ + -error=PCWM-L \ + -sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \ + +v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \ +incdir+$(build_dir) \ -f $(sim_common_files) \ $(sim_vsrcs) diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index fd7f1bd6..9d99f78c 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -72,7 +72,6 @@ ARIANE_VERILATOR_FLAGS = \ --unroll-count 256 \ -Werror-PINMISSING \ -Werror-IMPLICIT \ - -Wno-fatal \ -Wno-PINCONNECTEMPTY \ -Wno-ASSIGNDLY \ -Wno-DECLFILENAME \ @@ -91,9 +90,11 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 VERILATOR_NONCC_OPTS = \ $(TIMESCALE_OPTS) \ --top-module $(VLOG_MODEL) \ + -Wno-fatal \ $(shell if ! grep -iq "module.*ariane" $(build_dir)/*.*v; then echo "$(CHIPYARD_VERILATOR_FLAGS)"; else echo "$(ARIANE_VERILATOR_FLAGS)"; fi) \ --output-split 10000 \ --output-split-cfuncs 100 \ + --max-num-width 1048576 \ -f $(sim_common_files) \ $(sim_vsrcs) diff --git a/software/firemarshal b/software/firemarshal index c8e89bbe..a40f0252 160000 --- a/software/firemarshal +++ b/software/firemarshal @@ -1 +1 @@ -Subproject commit c8e89bbeb575be027670afa21c761319c2fd7e33 +Subproject commit a40f0252c4e426e794313ba02b0015e5f22133f4 diff --git a/software/nvdla-workload b/software/nvdla-workload new file mode 160000 index 00000000..02faf596 --- /dev/null +++ b/software/nvdla-workload @@ -0,0 +1 @@ +Subproject commit 02faf59692f88b66f8720d4eefa85aae385288a0 diff --git a/tests/Makefile b/tests/Makefile index 8754cbbc..af1bbd9c 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -5,7 +5,7 @@ LDFLAGS= -static include libgloss.mk -PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd spiflashread spiflashwrite +PROGRAMS = pwm blkdev accum charcount nic-loopback big-blkdev pingd nvdla spiflashread spiflashwrite spiflash.img: spiflash.py python3 $< diff --git a/tests/nvdla.c b/tests/nvdla.c new file mode 100644 index 00000000..5cf57f15 --- /dev/null +++ b/tests/nvdla.c @@ -0,0 +1,468 @@ +#include + +#include "nvdla.h" +#include "mmio.h" +#include + +#define NVDLA_BASE 0x10040000 +#define reg_write(addr,val) reg_write32(NVDLA_BASE+addr,val) +#define reg_read(addr) reg_read32(NVDLA_BASE+addr) + +int main(void) +{ + //----------## Layer:CDP_0: cross layer dependency, begin---------- + //----------## Layer:CDP_0: cross layer dependency, end---------- + //----------## Layer:CDP_0: set producer pointer, begin---------- + reg_write(CDP_S_POINTER_0, 0); + reg_write(CDP_RDMA_S_POINTER_0, 0); + //----------## Layer:CDP_0: set producer pointer, end---------- + //----------## Layer:CDP_0: LUT programming, begin---------- + reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x30000); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x41); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x42); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x43); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x44); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x45); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x46); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x47); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x48); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x49); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x50); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x51); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x52); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x53); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x54); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x55); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x56); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x57); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x58); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x59); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x60); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x61); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x62); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x63); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x64); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x65); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x66); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x67); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x68); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x69); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x70); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x71); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x72); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x73); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x74); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x75); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x76); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x77); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x78); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x79); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x80); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x81); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x82); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x83); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x84); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x85); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x86); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x87); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x88); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x89); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x90); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x91); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x92); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x93); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x94); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x95); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x96); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x97); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x98); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x99); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xab); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xac); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xad); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xae); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xaf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xba); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xbf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xca); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xce); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xcf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xda); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xde); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xdf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xea); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xeb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xec); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xed); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xee); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xef); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xfe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xff); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x100); + reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x20000); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x4); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x5); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x6); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x7); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x8); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x9); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xa); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xb); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xc); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xd); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xe); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0xf); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x10); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x11); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x12); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x13); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x14); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x15); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x16); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x17); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x18); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x19); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x1f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x20); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x21); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x22); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x23); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x24); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x25); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x26); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x27); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x28); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x29); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x2f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x30); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x31); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x32); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x33); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x34); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x35); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x36); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x37); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x38); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x39); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3a); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3b); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3c); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3d); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3e); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x3f); + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x40); + reg_write(CDP_S_LUT_LE_START_LOW_0, 0x0); + // CDP_S_LUT_LE_START_LOW_0.LUT_LE_START_LOW:0x0 + reg_write(CDP_S_LUT_LO_END_LOW_0, 0x100); + // CDP_S_LUT_LO_END_LOW_0.LUT_LO_END_LOW:0x100 + reg_write(CDP_S_LUT_ACCESS_CFG_0, 0x0); + // CDP_S_LUT_ACCESS_CFG_0.LUT_ACCESS_TYPE:READ : 0x0 + // CDP_S_LUT_ACCESS_CFG_0.LUT_TABLE_ID:LE : 0x0 + // CDP_S_LUT_ACCESS_CFG_0.LUT_ADDR:0x0 + reg_write(CDP_S_LUT_ACCESS_DATA_0, 0x0); + // CDP_S_LUT_ACCESS_DATA_0.LUT_DATA:0x0 + reg_write(CDP_S_LUT_LE_START_HIGH_0, 0x0); + // CDP_S_LUT_LE_START_HIGH_0.LUT_LE_START_HIGH:0x0 + reg_write(CDP_S_LUT_LO_END_HIGH_0, 0x0); + // CDP_S_LUT_LO_END_HIGH_0.LUT_LO_END_HIGH:0x0 + reg_write(CDP_S_LUT_CFG_0, 0x1); + // CDP_S_LUT_CFG_0.LUT_UFLOW_PRIORITY:LE : 0x0 + // CDP_S_LUT_CFG_0.LUT_OFLOW_PRIORITY:LE : 0x0 + // CDP_S_LUT_CFG_0.LUT_HYBRID_PRIORITY:LE : 0x0 + // CDP_S_LUT_CFG_0.LUT_LE_FUNCTION:LINEAR : 0x1 + reg_write(CDP_S_LUT_LE_SLOPE_SHIFT_0, 0x0); + // CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_OFLOW_SHIFT:0x0 + // CDP_S_LUT_LE_SLOPE_SHIFT_0.LUT_LE_SLOPE_UFLOW_SHIFT:0x0 + reg_write(CDP_S_LUT_LE_SLOPE_SCALE_0, 0x0); + // CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_UFLOW_SCALE:0x0 + // CDP_S_LUT_LE_SLOPE_SCALE_0.LUT_LE_SLOPE_OFLOW_SCALE:0x0 + reg_write(CDP_S_LUT_INFO_0, 0x0); + // CDP_S_LUT_INFO_0.LUT_LE_INDEX_SELECT:0x0 + // CDP_S_LUT_INFO_0.LUT_LE_INDEX_OFFSET:0x0 + // CDP_S_LUT_INFO_0.LUT_LO_INDEX_SELECT:0x0 + reg_write(CDP_S_LUT_LE_END_LOW_0, 0x40); + // CDP_S_LUT_LE_END_LOW_0.LUT_LE_END_LOW:0x40 + reg_write(CDP_S_LUT_LO_SLOPE_SCALE_0, 0x0); + // CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_OFLOW_SCALE:0x0 + // CDP_S_LUT_LO_SLOPE_SCALE_0.LUT_LO_SLOPE_UFLOW_SCALE:0x0 + reg_write(CDP_S_LUT_LE_END_HIGH_0, 0x0); + // CDP_S_LUT_LE_END_HIGH_0.LUT_LE_END_HIGH:0x0 + reg_write(CDP_S_LUT_LO_START_HIGH_0, 0x0); + // CDP_S_LUT_LO_START_HIGH_0.LUT_LO_START_HIGH:0x0 + reg_write(CDP_S_LUT_LO_START_LOW_0, 0x0); + // CDP_S_LUT_LO_START_LOW_0.LUT_LO_START_LOW:0x0 + reg_write(CDP_S_LUT_LO_SLOPE_SHIFT_0, 0x0); + // CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_UFLOW_SHIFT:0x0 + // CDP_S_LUT_LO_SLOPE_SHIFT_0.LUT_LO_SLOPE_OFLOW_SHIFT:0x0 + //----------## Layer:CDP_0: LUT programming, end---------- + //----------## Layer:CDP_0: configuraion, begin---------- + reg_write(CDP_D_DATOUT_OFFSET_0, 0x80); + // CDP_D_DATOUT_OFFSET_0.DATOUT_OFFSET:0x80 + reg_write(CDP_D_DST_SURFACE_STRIDE_0, 0x800); + // CDP_D_DST_SURFACE_STRIDE_0.DST_SURFACE_STRIDE:0x40 + reg_write(CDP_RDMA_D_SRC_BASE_ADDR_LOW_0, 0x90000000); + // CDP_RDMA_D_SRC_BASE_ADDR_LOW_0.SRC_BASE_ADDR_LOW:0x4000000 + reg_write(CDP_D_DST_DMA_CFG_0, 0x1); + // CDP_D_DST_DMA_CFG_0.DST_RAM_TYPE:MC : 0x1 + reg_write(CDP_RDMA_D_DATA_CUBE_WIDTH_0, 0x7); + // CDP_RDMA_D_DATA_CUBE_WIDTH_0.WIDTH:0x7 + reg_write(CDP_RDMA_D_DATA_FORMAT_0, 0x0); + // CDP_RDMA_D_DATA_FORMAT_0.INPUT_DATA:INT8 : 0x0 + reg_write(CDP_D_DATIN_SCALE_0, 0x1); + // CDP_D_DATIN_SCALE_0.DATIN_SCALE:0x1 + reg_write(CDP_D_DATOUT_SHIFTER_0, 0x0); + // CDP_D_DATOUT_SHIFTER_0.DATOUT_SHIFTER:0x0 + reg_write(CDP_D_CYA_0, 0x0); + // CDP_D_CYA_0.CYA:0x0 + reg_write(CDP_RDMA_D_PERF_ENABLE_0, 0x0); + // CDP_RDMA_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0 + reg_write(CDP_D_LRN_CFG_0, 0x0); + // CDP_D_LRN_CFG_0.NORMALZ_LEN:LEN3 : 0x0 + reg_write(CDP_RDMA_D_DATA_CUBE_CHANNEL_0, 0x1f); + // CDP_RDMA_D_DATA_CUBE_CHANNEL_0.CHANNEL:0x1f + reg_write(CDP_D_DATA_FORMAT_0, 0x0); + // CDP_D_DATA_FORMAT_0.INPUT_DATA_TYPE:INT8 : 0x0 + reg_write(CDP_D_DATIN_SHIFTER_0, 0x0); + // CDP_D_DATIN_SHIFTER_0.DATIN_SHIFTER:0x0 + reg_write(CDP_D_PERF_ENABLE_0, 0x0); + // CDP_D_PERF_ENABLE_0.LUT_EN:DISABLE : 0x0 + // CDP_D_PERF_ENABLE_0.DMA_EN:DISABLE : 0x0 + reg_write(CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0, 0x0); + // CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0.SRC_BASE_ADDR_HIGH:0x0 + reg_write(CDP_D_DST_BASE_ADDR_HIGH_0, 0x0); + // CDP_D_DST_BASE_ADDR_HIGH_0.DST_BASE_ADDR_HIGH:0x0 + reg_write(CDP_RDMA_D_SRC_DMA_CFG_0, 0x1); + // CDP_RDMA_D_SRC_DMA_CFG_0.SRC_RAM_TYPE:MC : 0x1 + reg_write(CDP_D_DATOUT_SCALE_0, 0x1); + // CDP_D_DATOUT_SCALE_0.DATOUT_SCALE:0x1 + reg_write(CDP_D_DATIN_OFFSET_0, 0x80); + // CDP_D_DATIN_OFFSET_0.DATIN_OFFSET:0x80 + reg_write(CDP_D_NAN_FLUSH_TO_ZERO_0, 0x0); + // CDP_D_NAN_FLUSH_TO_ZERO_0.NAN_TO_ZERO:DISABLE : 0x0 + reg_write(CDP_D_FUNC_BYPASS_0, 0x3); + // CDP_D_FUNC_BYPASS_0.SQSUM_BYPASS:ENABLE : 0x1 + // CDP_D_FUNC_BYPASS_0.MUL_BYPASS:ENABLE : 0x1 + reg_write(CDP_D_DST_BASE_ADDR_LOW_0, 0x90080000); + // CDP_D_DST_BASE_ADDR_LOW_0.DST_BASE_ADDR_LOW:0x4004000 + reg_write(CDP_RDMA_D_CYA_0, 0x0); + // CDP_RDMA_D_CYA_0.CYA:0x0 + reg_write(CDP_RDMA_D_SRC_SURFACE_STRIDE_0, 0x800); + // CDP_RDMA_D_SRC_SURFACE_STRIDE_0.SRC_SURFACE_STRIDE:0x40 + reg_write(CDP_D_DST_LINE_STRIDE_0, 0x100); + // CDP_D_DST_LINE_STRIDE_0.DST_LINE_STRIDE:0x8 + reg_write(CDP_RDMA_D_SRC_LINE_STRIDE_0, 0x100); + // CDP_RDMA_D_SRC_LINE_STRIDE_0.SRC_LINE_STRIDE:0x8 + reg_write(CDP_RDMA_D_DATA_CUBE_HEIGHT_0, 0x7); + // CDP_RDMA_D_DATA_CUBE_HEIGHT_0.HEIGHT:0x7 + //----------## Layer:CDP_0: configuraion, end---------- + //----------## Layer:CDP_0: operation enable, begin---------- + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, begin -- + reg_write(CDP_RDMA_D_OP_ENABLE_0,0x1); + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP_RDMA, end -- + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, begin -- + reg_write(CDP_D_OP_ENABLE_0,0x1); + //----------#### Layer:CDP_0: operation enable, block:NVDLA_CDP, end -- + //----------## Layer:CDP_0: operation enable, end---------- + + register uint64_t cycle1 = rdcycle(); + + for (register int idx = 0; idx < 32767; idx++) { + if (reg_read(GLB_S_INTR_STATUS_0) != 0) + break; + } + + uint64_t cycle2 = rdcycle(); + printf("cycle1: %lu, cycle2: %lu, diff: %lu\n", cycle1, cycle2, cycle2 - cycle1 ); + + return 0; +} diff --git a/tests/nvdla.h b/tests/nvdla.h new file mode 100644 index 00000000..dfcb3b0f --- /dev/null +++ b/tests/nvdla.h @@ -0,0 +1,6433 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of NVIDIA CORPORATION nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __OPENDLA_SMALL_H_ +#define __OPENDLA_SMALL_H_ + +// Register NVDLA_CFGROM_CFGROM_HW_VERSION_0 +#define NVDLA_CFGROM_CFGROM_HW_VERSION_0 _MK_ADDR_CONST(0x0) +#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_HW_VERSION_0_HW_VERSION_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_GLB_DESC_0 +#define NVDLA_CFGROM_CFGROM_GLB_DESC_0 _MK_ADDR_CONST(0x4) +#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_GLB_DESC_0_GLB_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_DESC_0 +#define NVDLA_CFGROM_CFGROM_CIF_DESC_0 _MK_ADDR_CONST(0x8) +#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_DESC_0_CIF_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xc) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_INCOMPAT_0_CIF_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0 _MK_ADDR_CONST(0x10) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_CAP_COMPAT_0_CIF_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0 _MK_ADDR_CONST(0x14) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_FIELD _MK_FIELD_CONST(0xff, NVDLA_CFGROM_CFGROM_CIF_BASE_WIDTH_0_CIF_BASE_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0 _MK_ADDR_CONST(0x18) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_LATENCY_0_CIF_BASE_LATENCY_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0 _MK_ADDR_CONST(0x1c) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_FIELD _MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_BURST_LENGTH_MAX_0_BASE_BURST_LENGTH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0 _MK_ADDR_CONST(0x20) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_FIELD _MK_FIELD_CONST(0x7ffffff, NVDLA_CFGROM_CFGROM_CIF_BASE_MEM_ADDR_WIDTH_0_CIF_BASE_MEM_ADDR_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0 _MK_ADDR_CONST(0x24) +#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_DESC_0_CDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x28) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_INCOMPAT_0_CDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x2c) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_CAP_COMPAT_0_CDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x30) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_FEATURE_TYPES_0_CDMA_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0x34) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDMA_BASE_WEIGHT_TYPES_0_CDMA_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0x38) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_C_0_CDMA_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0x3c) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_K_0_CDMA_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x40) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_ATOMIC_M_0_CDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0 _MK_ADDR_CONST(0x44) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_NUM_0_CDMA_BASE_CBUF_BANK_NUM_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0 _MK_ADDR_CONST(0x48) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_WIDTH_0_CDMA_BASE_CBUF_BANK_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0 +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0 _MK_ADDR_CONST(0x4c) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_BASE_CBUF_BANK_DEPTH_0_CDMA_BASE_CBUF_BANK_DEPTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0x50) +#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_MULTI_BATCH_MAX_0_CDMA_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0 +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0 _MK_ADDR_CONST(0x54) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_PACKED_0_CDMA_IMAGE_IN_FORMATS_PACKED_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0 +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0 _MK_ADDR_CONST(0x58) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDMA_IMAGE_IN_FORMATS_SEMI_0_CDMA_IMAGE_IN_FORMATS_SEMI_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_DESC_0 +#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0 _MK_ADDR_CONST(0x5c) +#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_DESC_0_CBUF_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x60) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_INCOMPAT_0_CBUF_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0 _MK_ADDR_CONST(0x64) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_CAP_COMPAT_0_CBUF_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0 _MK_ADDR_CONST(0x68) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_NUM_0_CBUF_BASE_CBUF_BANK_NUM_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0 _MK_ADDR_CONST(0x6c) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_WIDTH_0_CBUF_BASE_CBUF_BANK_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0 _MK_ADDR_CONST(0x70) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CBUF_BANK_DEPTH_0_CBUF_BASE_CBUF_BANK_DEPTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0 _MK_ADDR_CONST(0x74) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CBUF_BASE_CDMA_ID_0_CBUF_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_DESC_0 +#define NVDLA_CFGROM_CFGROM_CSC_DESC_0 _MK_ADDR_CONST(0x78) +#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_DESC_0_CSC_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x7c) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_INCOMPAT_0_CSC_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0 _MK_ADDR_CONST(0x80) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_CAP_COMPAT_0_CSC_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x84) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_FEATURE_TYPES_0_CSC_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0x88) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CSC_BASE_WEIGHT_TYPES_0_CSC_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0x8c) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_C_0_CSC_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0x90) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_K_0_CSC_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x94) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_ATOMIC_M_0_CSC_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0 _MK_ADDR_CONST(0x98) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_NUM_0_CSC_BASE_CBUF_BANK_NUM_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0 _MK_ADDR_CONST(0x9c) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_WIDTH_0_CSC_BASE_CBUF_BANK_WIDTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0 _MK_ADDR_CONST(0xa0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CBUF_BANK_DEPTH_0_CSC_BASE_CBUF_BANK_DEPTH_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0 _MK_ADDR_CONST(0xa4) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_BASE_CDMA_ID_0_CSC_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0xa8) +#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CSC_MULTI_BATCH_MAX_0_CSC_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0 _MK_ADDR_CONST(0xac) +#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_DESC_0_CMAC_A_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xb0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_INCOMPAT_0_CMAC_A_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0 _MK_ADDR_CONST(0xb4) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_CAP_COMPAT_0_CMAC_A_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0xb8) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_FEATURE_TYPES_0_CMAC_A_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0xbc) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_WEIGHT_TYPES_0_CMAC_A_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0xc0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_C_0_CMAC_A_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0xc4) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_ATOMIC_K_0_CMAC_A_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0 _MK_ADDR_CONST(0xc8) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_A_BASE_CDMA_ID_0_CMAC_A_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0 _MK_ADDR_CONST(0xcc) +#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_DESC_0_CMAC_B_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xd0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_INCOMPAT_0_CMAC_B_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0 _MK_ADDR_CONST(0xd4) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_CAP_COMPAT_0_CMAC_B_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0xd8) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_FEATURE_TYPES_0_CMAC_B_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0xdc) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_WEIGHT_TYPES_0_CMAC_B_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0xe0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_C_0_CMAC_B_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0xe4) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_ATOMIC_K_0_CMAC_B_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0 _MK_ADDR_CONST(0xe8) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CMAC_B_BASE_CDMA_ID_0_CMAC_B_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_DESC_0 +#define NVDLA_CFGROM_CFGROM_CACC_DESC_0 _MK_ADDR_CONST(0xec) +#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_DESC_0_CACC_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0 _MK_ADDR_CONST(0xf0) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_INCOMPAT_0_CACC_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0 _MK_ADDR_CONST(0xf4) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_CAP_COMPAT_0_CACC_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0xf8) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_FEATURE_TYPES_0_CACC_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0xfc) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CACC_BASE_WEIGHT_TYPES_0_CACC_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0 _MK_ADDR_CONST(0x100) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_C_0_CACC_BASE_ATOMIC_C_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0 _MK_ADDR_CONST(0x104) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_ATOMIC_K_0_CACC_BASE_ATOMIC_K_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0 _MK_ADDR_CONST(0x108) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_BASE_CDMA_ID_0_CACC_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0x10c) +#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CACC_MULTI_BATCH_MAX_0_CACC_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0 _MK_ADDR_CONST(0x110) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_DESC_0_SDP_RDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x114) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_INCOMPAT_0_SDP_RDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x118) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_CAP_COMPAT_0_SDP_RDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x11c) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_ATOMIC_M_0_SDP_RDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0 +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0 _MK_ADDR_CONST(0x120) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_RDMA_BASE_SDP_ID_0_SDP_RDMA_BASE_SDP_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_DESC_0 +#define NVDLA_CFGROM_CFGROM_SDP_DESC_0 _MK_ADDR_CONST(0x124) +#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_DESC_0_SDP_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x128) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_INCOMPAT_0_SDP_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0 _MK_ADDR_CONST(0x12c) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_CAP_COMPAT_0_SDP_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x130) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_FEATURE_TYPES_0_SDP_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0 +#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0 _MK_ADDR_CONST(0x134) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_SDP_BASE_WEIGHT_TYPES_0_SDP_BASE_WEIGHT_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0 +#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0 _MK_ADDR_CONST(0x138) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BASE_CDMA_ID_0_SDP_BASE_CDMA_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0 +#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0 _MK_ADDR_CONST(0x13c) +#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_MULTI_BATCH_MAX_0_SDP_MULTI_BATCH_MAX_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0 _MK_ADDR_CONST(0x140) +#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BS_THROUGHPUT_0_SDP_BS_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0 _MK_ADDR_CONST(0x144) +#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_BN_THROUGHPUT_0_SDP_BN_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0 _MK_ADDR_CONST(0x148) +#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_SDP_EW_THROUGHPUT_0_SDP_EW_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0 _MK_ADDR_CONST(0x14c) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_DESC_0_PDP_RDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x150) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_INCOMPAT_0_PDP_RDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x154) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_CAP_COMPAT_0_PDP_RDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x158) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_ATOMIC_M_0_PDP_RDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0 +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0 _MK_ADDR_CONST(0x15c) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_RDMA_BASE_PDP_ID_0_PDP_RDMA_BASE_PDP_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_DESC_0 +#define NVDLA_CFGROM_CFGROM_PDP_DESC_0 _MK_ADDR_CONST(0x160) +#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_DESC_0_PDP_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x164) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_INCOMPAT_0_PDP_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0 _MK_ADDR_CONST(0x168) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_CAP_COMPAT_0_PDP_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x16c) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_PDP_BASE_FEATURE_TYPES_0_PDP_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0 _MK_ADDR_CONST(0x170) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_PDP_BASE_THROUGHPUT_0_PDP_BASE_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0 _MK_ADDR_CONST(0x174) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_DESC_0_CDP_RDMA_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x178) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_INCOMPAT_0_CDP_RDMA_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0 _MK_ADDR_CONST(0x17c) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_CAP_COMPAT_0_CDP_RDMA_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0 _MK_ADDR_CONST(0x180) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_ATOMIC_M_0_CDP_RDMA_BASE_ATOMIC_M_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0 +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0 _MK_ADDR_CONST(0x184) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_RDMA_BASE_CDP_ID_0_CDP_RDMA_BASE_CDP_ID_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_DESC_0 +#define NVDLA_CFGROM_CFGROM_CDP_DESC_0 _MK_ADDR_CONST(0x188) +#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_DESC_0_CDP_DESC_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0 _MK_ADDR_CONST(0x18c) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_INCOMPAT_0_CDP_CAP_INCOMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0 +#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0 _MK_ADDR_CONST(0x190) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_CAP_COMPAT_0_CDP_CAP_COMPAT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0 +#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0 _MK_ADDR_CONST(0x194) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_FIELD _MK_FIELD_CONST(0xfff, NVDLA_CFGROM_CFGROM_CDP_BASE_FEATURE_TYPES_0_CDP_BASE_FEATURE_TYPES_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0 +#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0 _MK_ADDR_CONST(0x198) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_CDP_BASE_THROUGHPUT_0_CDP_BASE_THROUGHPUT_SHIFT) + + +// Register NVDLA_CFGROM_CFGROM_END_OF_LIST_0 +#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0 _MK_ADDR_CONST(0x19c) +#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_FIELD _MK_FIELD_CONST(0xffffffff, NVDLA_CFGROM_CFGROM_END_OF_LIST_0_END_OF_LIST_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register GLB_S_NVDLA_HW_VERSION_0 +#define GLB_S_NVDLA_HW_VERSION_0 _MK_ADDR_CONST(0x1000) +#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_NVDLA_HW_VERSION_0_MAJOR_FIELD _MK_FIELD_CONST(0xff, GLB_S_NVDLA_HW_VERSION_0_MAJOR_SHIFT) +#define GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_NVDLA_HW_VERSION_0_MINOR_FIELD _MK_FIELD_CONST(0xffff, GLB_S_NVDLA_HW_VERSION_0_MINOR_SHIFT) + + +// Register GLB_S_INTR_MASK_0 +#define GLB_S_INTR_MASK_0 _MK_ADDR_CONST(0x1004) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT _MK_SHIFT_CONST(1) +#define GLB_S_INTR_MASK_0_SDP_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_SDP_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT _MK_SHIFT_CONST(2) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT _MK_SHIFT_CONST(3) +#define GLB_S_INTR_MASK_0_CDP_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDP_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT _MK_SHIFT_CONST(4) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT _MK_SHIFT_CONST(5) +#define GLB_S_INTR_MASK_0_PDP_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_PDP_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT _MK_SHIFT_CONST(6) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT _MK_SHIFT_CONST(7) +#define GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_BDMA_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT _MK_SHIFT_CONST(9) +#define GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_RUBIK_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT _MK_SHIFT_CONST(16) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT _MK_SHIFT_CONST(17) +#define GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_DAT_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT _MK_SHIFT_CONST(18) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT _MK_SHIFT_CONST(19) +#define GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CDMA_WT_DONE_MASK1_SHIFT) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT _MK_SHIFT_CONST(20) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK0_SHIFT) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT _MK_SHIFT_CONST(21) +#define GLB_S_INTR_MASK_0_CACC_DONE_MASK1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_MASK_0_CACC_DONE_MASK1_SHIFT) + + +// Register GLB_S_INTR_SET_0 +#define GLB_S_INTR_SET_0 _MK_ADDR_CONST(0x1008) +#define GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_INTR_SET_0_SDP_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT _MK_SHIFT_CONST(1) +#define GLB_S_INTR_SET_0_SDP_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_SDP_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT _MK_SHIFT_CONST(2) +#define GLB_S_INTR_SET_0_CDP_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT _MK_SHIFT_CONST(3) +#define GLB_S_INTR_SET_0_CDP_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDP_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT _MK_SHIFT_CONST(4) +#define GLB_S_INTR_SET_0_PDP_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT _MK_SHIFT_CONST(5) +#define GLB_S_INTR_SET_0_PDP_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_PDP_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT _MK_SHIFT_CONST(6) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT _MK_SHIFT_CONST(7) +#define GLB_S_INTR_SET_0_BDMA_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_BDMA_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT _MK_SHIFT_CONST(9) +#define GLB_S_INTR_SET_0_RUBIK_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_RUBIK_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT _MK_SHIFT_CONST(16) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT _MK_SHIFT_CONST(17) +#define GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_DAT_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT _MK_SHIFT_CONST(18) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT _MK_SHIFT_CONST(19) +#define GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CDMA_WT_DONE_SET1_SHIFT) +#define GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT _MK_SHIFT_CONST(20) +#define GLB_S_INTR_SET_0_CACC_DONE_SET0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET0_SHIFT) +#define GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT _MK_SHIFT_CONST(21) +#define GLB_S_INTR_SET_0_CACC_DONE_SET1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_SET_0_CACC_DONE_SET1_SHIFT) + + +// Register GLB_S_INTR_STATUS_0 +#define GLB_S_INTR_STATUS_0 _MK_ADDR_CONST(0x100c) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(0) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(1) +#define GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_SDP_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(2) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(3) +#define GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDP_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(4) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(5) +#define GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_PDP_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(6) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(7) +#define GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_BDMA_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(8) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(9) +#define GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_RUBIK_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(16) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(17) +#define GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_DAT_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(18) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(19) +#define GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CDMA_WT_DONE_STATUS1_SHIFT) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT _MK_SHIFT_CONST(20) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS0_SHIFT) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT _MK_SHIFT_CONST(21) +#define GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_FIELD _MK_FIELD_CONST(0x1, GLB_S_INTR_STATUS_0_CACC_DONE_STATUS1_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register NVDLA_MCIF_CFG_RD_WEIGHT_0_0 +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0 _MK_ADDR_CONST(0x2000) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_MCIF_CFG_RD_WEIGHT_1_0 +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0 _MK_ADDR_CONST(0x2004) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT) + + +// Register NVDLA_MCIF_CFG_RD_WEIGHT_2_0 +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0 _MK_ADDR_CONST(0x2008) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_MCIF_CFG_WR_WEIGHT_0_0 +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0 _MK_ADDR_CONST(0x200c) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_MCIF_CFG_WR_WEIGHT_1_0 +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0 _MK_ADDR_CONST(0x2010) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0 _MK_ADDR_CONST(0x2014) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_MCIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT) + + +// Register NVDLA_MCIF_STATUS_0 +#define NVDLA_MCIF_STATUS_0 _MK_ADDR_CONST(0x2018) +#define NVDLA_MCIF_STATUS_0_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_MCIF_STATUS_0_IDLE_FIELD _MK_FIELD_CONST(0x1, NVDLA_MCIF_STATUS_0_IDLE_SHIFT) +#define NVDLA_MCIF_STATUS_0_IDLE_NO _MK_ENUM_CONST(0x0) +#define NVDLA_MCIF_STATUS_0_IDLE_YES _MK_ENUM_CONST(0x1) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CDMA_S_STATUS_0 +#define CDMA_S_STATUS_0 _MK_ADDR_CONST(0x3000) +#define CDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_0_SHIFT) +#define CDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CDMA_S_STATUS_0_STATUS_1_SHIFT) +#define CDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CDMA_S_POINTER_0 +#define CDMA_S_POINTER_0 _MK_ADDR_CONST(0x3004) +#define CDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_PRODUCER_SHIFT) +#define CDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CDMA_S_POINTER_0_CONSUMER_SHIFT) +#define CDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CDMA_S_ARBITER_0 +#define CDMA_S_ARBITER_0 _MK_ADDR_CONST(0x3008) +#define CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_ARBITER_0_ARB_WEIGHT_FIELD _MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WEIGHT_SHIFT) +#define CDMA_S_ARBITER_0_ARB_WMB_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_S_ARBITER_0_ARB_WMB_FIELD _MK_FIELD_CONST(0xf, CDMA_S_ARBITER_0_ARB_WMB_SHIFT) + + +// Register CDMA_S_CBUF_FLUSH_STATUS_0 +#define CDMA_S_CBUF_FLUSH_STATUS_0 _MK_ADDR_CONST(0x300c) +#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_FIELD _MK_FIELD_CONST(0x1, CDMA_S_CBUF_FLUSH_STATUS_0_FLUSH_DONE_SHIFT) + + +// Register CDMA_D_OP_ENABLE_0 +#define CDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0x3010) +#define CDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_MISC_CFG_0 +#define CDMA_D_MISC_CFG_0 _MK_ADDR_CONST(0x3014) +#define CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CDMA_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(8) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_IN_PRECISION_SHIFT) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CDMA_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_DATA_REUSE_SHIFT) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_DATA_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT _MK_SHIFT_CONST(20) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT _MK_SHIFT_CONST(24) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT _MK_SHIFT_CONST(28) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_DATAIN_FORMAT_0 +#define CDMA_D_DATAIN_FORMAT_0 _MK_ADDR_CONST(0x3018) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL _MK_ENUM_CONST(0x1) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT _MK_SHIFT_CONST(8) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8 _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10 _MK_ENUM_CONST(0x1) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R12 _MK_ENUM_CONST(0x2) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16 _MK_ENUM_CONST(0x3) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_I _MK_ENUM_CONST(0x4) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R16_F _MK_ENUM_CONST(0x5) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16 _MK_ENUM_CONST(0x6) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X16B16G16R16 _MK_ENUM_CONST(0x7) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16B16G16R16_F _MK_ENUM_CONST(0x8) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16 _MK_ENUM_CONST(0x9) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V16U16Y16A16 _MK_ENUM_CONST(0xa) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A16Y16U16V16_F _MK_ENUM_CONST(0xb) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8B8G8R8 _MK_ENUM_CONST(0xc) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8R8G8B8 _MK_ENUM_CONST(0xd) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8A8 _MK_ENUM_CONST(0xe) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8A8 _MK_ENUM_CONST(0xf) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8B8G8R8 _MK_ENUM_CONST(0x10) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_X8R8G8B8 _MK_ENUM_CONST(0x11) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B8G8R8X8 _MK_ENUM_CONST(0x12) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R8G8B8X8 _MK_ENUM_CONST(0x13) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2B10G10R10 _MK_ENUM_CONST(0x14) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2R10G10B10 _MK_ENUM_CONST(0x15) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_B10G10R10A2 _MK_ENUM_CONST(0x16) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_R10G10B10A2 _MK_ENUM_CONST(0x17) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A2Y10U10V10 _MK_ENUM_CONST(0x18) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V10U10Y10A2 _MK_ENUM_CONST(0x19) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_A8Y8U8V8 _MK_ENUM_CONST(0x1a) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_V8U8Y8A8 _MK_ENUM_CONST(0x1b) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___U8V8_N444 _MK_ENUM_CONST(0x1c) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y8___V8U8_N444 _MK_ENUM_CONST(0x1d) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___U10V10_N444 _MK_ENUM_CONST(0x1e) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y10___V10U10_N444 _MK_ENUM_CONST(0x1f) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___U12V12_N444 _MK_ENUM_CONST(0x20) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y12___V12U12_N444 _MK_ENUM_CONST(0x21) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___U16V16_N444 _MK_ENUM_CONST(0x22) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_FORMAT_T_Y16___V16U16_N444 _MK_ENUM_CONST(0x23) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_PITCH_LINEAR _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_MAPPING_RESERVED_LINEAR _MK_ENUM_CONST(0x1) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT _MK_SHIFT_CONST(20) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SHIFT) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_UNSIGNED_INT _MK_ENUM_CONST(0x0) +#define CDMA_D_DATAIN_FORMAT_0_PIXEL_SIGN_OVERRIDE_SIGNED_INT _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_DATAIN_SIZE_0_0 +#define CDMA_D_DATAIN_SIZE_0_0 _MK_ADDR_CONST(0x301c) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT) + + +// Register CDMA_D_DATAIN_SIZE_1_0 +#define CDMA_D_DATAIN_SIZE_1_0 _MK_ADDR_CONST(0x3020) +#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT) + + +// Register CDMA_D_DATAIN_SIZE_EXT_0_0 +#define CDMA_D_DATAIN_SIZE_EXT_0_0 _MK_ADDR_CONST(0x3024) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT) + + +// Register CDMA_D_PIXEL_OFFSET_0 +#define CDMA_D_PIXEL_OFFSET_0 _MK_ADDR_CONST(0x3028) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_PIXEL_OFFSET_0_PIXEL_X_OFFSET_SHIFT) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_FIELD _MK_FIELD_CONST(0x7, CDMA_D_PIXEL_OFFSET_0_PIXEL_Y_OFFSET_SHIFT) + + +// Register CDMA_D_DAIN_RAM_TYPE_0 +#define CDMA_D_DAIN_RAM_TYPE_0 _MK_ADDR_CONST(0x302c) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define CDMA_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_DAIN_ADDR_HIGH_0_0 +#define CDMA_D_DAIN_ADDR_HIGH_0_0 _MK_ADDR_CONST(0x3030) +#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_0_0_DATAIN_ADDR_HIGH_0_SHIFT) + + +// Register CDMA_D_DAIN_ADDR_LOW_0_0 +#define CDMA_D_DAIN_ADDR_LOW_0_0 _MK_ADDR_CONST(0x3034) +#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_0_0_DATAIN_ADDR_LOW_0_SHIFT) + + +// Register CDMA_D_DAIN_ADDR_HIGH_1_0 +#define CDMA_D_DAIN_ADDR_HIGH_1_0 _MK_ADDR_CONST(0x3038) +#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_HIGH_1_0_DATAIN_ADDR_HIGH_1_SHIFT) + + +// Register CDMA_D_DAIN_ADDR_LOW_1_0 +#define CDMA_D_DAIN_ADDR_LOW_1_0 _MK_ADDR_CONST(0x303c) +#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_DAIN_ADDR_LOW_1_0_DATAIN_ADDR_LOW_1_SHIFT) + + +// Register CDMA_D_LINE_STRIDE_0 +#define CDMA_D_LINE_STRIDE_0 _MK_ADDR_CONST(0x3040) +#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_LINE_STRIDE_0_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT) + + +// Register CDMA_D_LINE_UV_STRIDE_0 +#define CDMA_D_LINE_UV_STRIDE_0 _MK_ADDR_CONST(0x3044) +#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_LINE_UV_STRIDE_0_UV_LINE_STRIDE_SHIFT) + + +// Register CDMA_D_SURF_STRIDE_0 +#define CDMA_D_SURF_STRIDE_0 _MK_ADDR_CONST(0x3048) +#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_SURF_STRIDE_0_SURF_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT) + + +// Register CDMA_D_DAIN_MAP_0 +#define CDMA_D_DAIN_MAP_0 _MK_ADDR_CONST(0x304c) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_LINE_PACKED_SHIFT) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CDMA_D_DAIN_MAP_0_LINE_PACKED_TRUE _MK_ENUM_CONST(0x1) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FIELD _MK_FIELD_CONST(0x1, CDMA_D_DAIN_MAP_0_SURF_PACKED_SHIFT) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CDMA_D_DAIN_MAP_0_SURF_PACKED_TRUE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_RESERVED_X_CFG_0 +#define CDMA_D_RESERVED_X_CFG_0 _MK_ADDR_CONST(0x3050) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_FIELD _MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_LINE_SHIFT) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_FIELD _MK_FIELD_CONST(0x3ff, CDMA_D_RESERVED_X_CFG_0_RSV_PER_UV_LINE_SHIFT) + + +// Register CDMA_D_RESERVED_Y_CFG_0 +#define CDMA_D_RESERVED_Y_CFG_0 _MK_ADDR_CONST(0x3054) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_FIELD _MK_FIELD_CONST(0x7, CDMA_D_RESERVED_Y_CFG_0_RSV_HEIGHT_SHIFT) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_RESERVED_Y_CFG_0_RSV_Y_INDEX_SHIFT) + + +// Register CDMA_D_BATCH_NUMBER_0 +#define CDMA_D_BATCH_NUMBER_0 _MK_ADDR_CONST(0x3058) +#define CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_BATCH_NUMBER_0_BATCHES_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_BATCH_NUMBER_0_BATCHES_SHIFT) + + +// Register CDMA_D_BATCH_STRIDE_0 +#define CDMA_D_BATCH_STRIDE_0 _MK_ADDR_CONST(0x305c) +#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_BATCH_STRIDE_0_BATCH_STRIDE_SHIFT) + + +// Register CDMA_D_ENTRY_PER_SLICE_0 +#define CDMA_D_ENTRY_PER_SLICE_0 _MK_ADDR_CONST(0x3060) +#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD _MK_FIELD_CONST(0x3fff, CDMA_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT) + + +// Register CDMA_D_FETCH_GRAIN_0 +#define CDMA_D_FETCH_GRAIN_0 _MK_ADDR_CONST(0x3064) +#define CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_FETCH_GRAIN_0_GRAINS_FIELD _MK_FIELD_CONST(0xfff, CDMA_D_FETCH_GRAIN_0_GRAINS_SHIFT) + + +// Register CDMA_D_WEIGHT_FORMAT_0 +#define CDMA_D_WEIGHT_FORMAT_0 _MK_ADDR_CONST(0x3068) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD _MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED _MK_ENUM_CONST(0x0) +#define CDMA_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_WEIGHT_SIZE_0_0 +#define CDMA_D_WEIGHT_SIZE_0_0 _MK_ADDR_CONST(0x306c) +#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_FIELD _MK_FIELD_CONST(0x3ffff, CDMA_D_WEIGHT_SIZE_0_0_BYTE_PER_KERNEL_SHIFT) + + +// Register CDMA_D_WEIGHT_SIZE_1_0 +#define CDMA_D_WEIGHT_SIZE_1_0 _MK_ADDR_CONST(0x3070) +#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_FIELD _MK_FIELD_CONST(0x1fff, CDMA_D_WEIGHT_SIZE_1_0_WEIGHT_KERNEL_SHIFT) + + +// Register CDMA_D_WEIGHT_RAM_TYPE_0 +#define CDMA_D_WEIGHT_RAM_TYPE_0 _MK_ADDR_CONST(0x3074) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_SHIFT) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define CDMA_D_WEIGHT_RAM_TYPE_0_WEIGHT_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_WEIGHT_ADDR_HIGH_0 +#define CDMA_D_WEIGHT_ADDR_HIGH_0 _MK_ADDR_CONST(0x3078) +#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_HIGH_0_WEIGHT_ADDR_HIGH_SHIFT) + + +// Register CDMA_D_WEIGHT_ADDR_LOW_0 +#define CDMA_D_WEIGHT_ADDR_LOW_0 _MK_ADDR_CONST(0x307c) +#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_ADDR_LOW_0_WEIGHT_ADDR_LOW_SHIFT) + + +// Register CDMA_D_WEIGHT_BYTES_0 +#define CDMA_D_WEIGHT_BYTES_0 _MK_ADDR_CONST(0x3080) +#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT) + + +// Register CDMA_D_WGS_ADDR_HIGH_0 +#define CDMA_D_WGS_ADDR_HIGH_0 _MK_ADDR_CONST(0x3084) +#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_HIGH_0_WGS_ADDR_HIGH_SHIFT) + + +// Register CDMA_D_WGS_ADDR_LOW_0 +#define CDMA_D_WGS_ADDR_LOW_0 _MK_ADDR_CONST(0x3088) +#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WGS_ADDR_LOW_0_WGS_ADDR_LOW_SHIFT) + + +// Register CDMA_D_WMB_ADDR_HIGH_0 +#define CDMA_D_WMB_ADDR_HIGH_0 _MK_ADDR_CONST(0x308c) +#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_HIGH_0_WMB_ADDR_HIGH_SHIFT) + + +// Register CDMA_D_WMB_ADDR_LOW_0 +#define CDMA_D_WMB_ADDR_LOW_0 _MK_ADDR_CONST(0x3090) +#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_WMB_ADDR_LOW_0_WMB_ADDR_LOW_SHIFT) + + +// Register CDMA_D_WMB_BYTES_0 +#define CDMA_D_WMB_BYTES_0 _MK_ADDR_CONST(0x3094) +#define CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_WMB_BYTES_0_WMB_BYTES_FIELD _MK_FIELD_CONST(0xfffffff, CDMA_D_WMB_BYTES_0_WMB_BYTES_SHIFT) + + +// Register CDMA_D_MEAN_FORMAT_0 +#define CDMA_D_MEAN_FORMAT_0 _MK_ADDR_CONST(0x3098) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_FIELD _MK_FIELD_CONST(0x1, CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_SHIFT) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_MEAN_FORMAT_0_MEAN_FORMAT_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_MEAN_GLOBAL_0_0 +#define CDMA_D_MEAN_GLOBAL_0_0 _MK_ADDR_CONST(0x309c) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_RY_SHIFT) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_0_0_MEAN_GU_SHIFT) + + +// Register CDMA_D_MEAN_GLOBAL_1_0 +#define CDMA_D_MEAN_GLOBAL_1_0 _MK_ADDR_CONST(0x30a0) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_BV_SHIFT) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_MEAN_GLOBAL_1_0_MEAN_AX_SHIFT) + + +// Register CDMA_D_CVT_CFG_0 +#define CDMA_D_CVT_CFG_0 _MK_ADDR_CONST(0x30a4) +#define CDMA_D_CVT_CFG_0_CVT_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CVT_CFG_0_CVT_EN_FIELD _MK_FIELD_CONST(0x1, CDMA_D_CVT_CFG_0_CVT_EN_SHIFT) +#define CDMA_D_CVT_CFG_0_CVT_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_CVT_CFG_0_CVT_EN_ENABLE _MK_ENUM_CONST(0x1) +#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT _MK_SHIFT_CONST(4) +#define CDMA_D_CVT_CFG_0_CVT_TRUNCATE_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_CVT_CFG_0_CVT_TRUNCATE_SHIFT) + + +// Register CDMA_D_CVT_OFFSET_0 +#define CDMA_D_CVT_OFFSET_0 _MK_ADDR_CONST(0x30a8) +#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CVT_OFFSET_0_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT) + + +// Register CDMA_D_CVT_SCALE_0 +#define CDMA_D_CVT_SCALE_0 _MK_ADDR_CONST(0x30ac) +#define CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CVT_SCALE_0_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_CVT_SCALE_0_CVT_SCALE_SHIFT) + + +// Register CDMA_D_CONV_STRIDE_0 +#define CDMA_D_CONV_STRIDE_0 _MK_ADDR_CONST(0x30b0) +#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_FIELD _MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_X_STRIDE_SHIFT) +#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_FIELD _MK_FIELD_CONST(0x7, CDMA_D_CONV_STRIDE_0_CONV_Y_STRIDE_SHIFT) + + +// Register CDMA_D_ZERO_PADDING_0 +#define CDMA_D_ZERO_PADDING_0 _MK_ADDR_CONST(0x30b4) +#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_ZERO_PADDING_0_PAD_LEFT_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_LEFT_SHIFT) +#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT _MK_SHIFT_CONST(8) +#define CDMA_D_ZERO_PADDING_0_PAD_RIGHT_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_RIGHT_SHIFT) +#define CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_ZERO_PADDING_0_PAD_TOP_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_ZERO_PADDING_0_PAD_TOP_SHIFT) +#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT _MK_SHIFT_CONST(24) +#define CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_FIELD _MK_FIELD_CONST(0x3f, CDMA_D_ZERO_PADDING_0_PAD_BOTTOM_SHIFT) + + +// Register CDMA_D_ZERO_PADDING_VALUE_0 +#define CDMA_D_ZERO_PADDING_VALUE_0 _MK_ADDR_CONST(0x30b8) +#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD _MK_FIELD_CONST(0xffff, CDMA_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT) + + +// Register CDMA_D_BANK_0 +#define CDMA_D_BANK_0 _MK_ADDR_CONST(0x30bc) +#define CDMA_D_BANK_0_DATA_BANK_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_BANK_0_DATA_BANK_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_DATA_BANK_SHIFT) +#define CDMA_D_BANK_0_WEIGHT_BANK_SHIFT _MK_SHIFT_CONST(16) +#define CDMA_D_BANK_0_WEIGHT_BANK_FIELD _MK_FIELD_CONST(0x1f, CDMA_D_BANK_0_WEIGHT_BANK_SHIFT) + + +// Register CDMA_D_NAN_FLUSH_TO_ZERO_0 +#define CDMA_D_NAN_FLUSH_TO_ZERO_0 _MK_ADDR_CONST(0x30c0) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define CDMA_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDMA_D_NAN_INPUT_DATA_NUM_0 +#define CDMA_D_NAN_INPUT_DATA_NUM_0 _MK_ADDR_CONST(0x30c4) +#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_DATA_NUM_0_NAN_DATA_NUM_SHIFT) + + +// Register CDMA_D_NAN_INPUT_WEIGHT_NUM_0 +#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0 _MK_ADDR_CONST(0x30c8) +#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_NAN_INPUT_WEIGHT_NUM_0_NAN_WEIGHT_NUM_SHIFT) + + +// Register CDMA_D_INF_INPUT_DATA_NUM_0 +#define CDMA_D_INF_INPUT_DATA_NUM_0 _MK_ADDR_CONST(0x30cc) +#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_DATA_NUM_0_INF_DATA_NUM_SHIFT) + + +// Register CDMA_D_INF_INPUT_WEIGHT_NUM_0 +#define CDMA_D_INF_INPUT_WEIGHT_NUM_0 _MK_ADDR_CONST(0x30d0) +#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_INF_INPUT_WEIGHT_NUM_0_INF_WEIGHT_NUM_SHIFT) + + +// Register CDMA_D_PERF_ENABLE_0 +#define CDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x30d4) +#define CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, CDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT) + + +// Register CDMA_D_PERF_DAT_READ_STALL_0 +#define CDMA_D_PERF_DAT_READ_STALL_0 _MK_ADDR_CONST(0x30d8) +#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_STALL_0_DAT_RD_STALL_SHIFT) + + +// Register CDMA_D_PERF_WT_READ_STALL_0 +#define CDMA_D_PERF_WT_READ_STALL_0 _MK_ADDR_CONST(0x30dc) +#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_STALL_0_WT_RD_STALL_SHIFT) + + +// Register CDMA_D_PERF_DAT_READ_LATENCY_0 +#define CDMA_D_PERF_DAT_READ_LATENCY_0 _MK_ADDR_CONST(0x30e0) +#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_DAT_READ_LATENCY_0_DAT_RD_LATENCY_SHIFT) + + +// Register CDMA_D_PERF_WT_READ_LATENCY_0 +#define CDMA_D_PERF_WT_READ_LATENCY_0 _MK_ADDR_CONST(0x30e4) +#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_PERF_WT_READ_LATENCY_0_WT_RD_LATENCY_SHIFT) + + +// Register CDMA_D_CYA_0 +#define CDMA_D_CYA_0 _MK_ADDR_CONST(0x30e8) +#define CDMA_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CDMA_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CDMA_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CSC_S_STATUS_0 +#define CSC_S_STATUS_0 _MK_ADDR_CONST(0x4000) +#define CSC_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CSC_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_0_SHIFT) +#define CSC_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CSC_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CSC_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CSC_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CSC_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CSC_S_STATUS_0_STATUS_1_SHIFT) +#define CSC_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CSC_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CSC_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CSC_S_POINTER_0 +#define CSC_S_POINTER_0 _MK_ADDR_CONST(0x4004) +#define CSC_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CSC_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CSC_S_POINTER_0_PRODUCER_SHIFT) +#define CSC_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CSC_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CSC_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CSC_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CSC_S_POINTER_0_CONSUMER_SHIFT) +#define CSC_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CSC_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CSC_D_OP_ENABLE_0 +#define CSC_D_OP_ENABLE_0 _MK_ADDR_CONST(0x4008) +#define CSC_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CSC_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CSC_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CSC_D_MISC_CFG_0 +#define CSC_D_MISC_CFG_0 _MK_ADDR_CONST(0x400c) +#define CSC_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CSC_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(8) +#define CSC_D_MISC_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_IN_PRECISION_SHIFT) +#define CSC_D_MISC_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CSC_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_MISC_CFG_0_DATA_REUSE_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_DATA_REUSE_SHIFT) +#define CSC_D_MISC_CFG_0_DATA_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_DATA_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT _MK_SHIFT_CONST(20) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_WEIGHT_REUSE_SHIFT) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_WEIGHT_REUSE_ENABLE _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT _MK_SHIFT_CONST(24) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_DATA_RLS_SHIFT) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_SKIP_DATA_RLS_ENABLE _MK_ENUM_CONST(0x1) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT _MK_SHIFT_CONST(28) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_FIELD _MK_FIELD_CONST(0x1, CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_SHIFT) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_DISABLE _MK_ENUM_CONST(0x0) +#define CSC_D_MISC_CFG_0_SKIP_WEIGHT_RLS_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CSC_D_DATAIN_FORMAT_0 +#define CSC_D_DATAIN_FORMAT_0 _MK_ADDR_CONST(0x4010) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FIELD _MK_FIELD_CONST(0x1, CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_SHIFT) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_FEATURE _MK_ENUM_CONST(0x0) +#define CSC_D_DATAIN_FORMAT_0_DATAIN_FORMAT_PIXEL _MK_ENUM_CONST(0x1) + + +// Register CSC_D_DATAIN_SIZE_EXT_0_0 +#define CSC_D_DATAIN_SIZE_EXT_0_0 _MK_ADDR_CONST(0x4014) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_WIDTH_EXT_SHIFT) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_0_0_DATAIN_HEIGHT_EXT_SHIFT) + + +// Register CSC_D_DATAIN_SIZE_EXT_1_0 +#define CSC_D_DATAIN_SIZE_EXT_1_0 _MK_ADDR_CONST(0x4018) +#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAIN_SIZE_EXT_1_0_DATAIN_CHANNEL_EXT_SHIFT) + + +// Register CSC_D_BATCH_NUMBER_0 +#define CSC_D_BATCH_NUMBER_0 _MK_ADDR_CONST(0x401c) +#define CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_BATCH_NUMBER_0_BATCHES_FIELD _MK_FIELD_CONST(0x1f, CSC_D_BATCH_NUMBER_0_BATCHES_SHIFT) + + +// Register CSC_D_POST_Y_EXTENSION_0 +#define CSC_D_POST_Y_EXTENSION_0 _MK_ADDR_CONST(0x4020) +#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_FIELD _MK_FIELD_CONST(0x3, CSC_D_POST_Y_EXTENSION_0_Y_EXTENSION_SHIFT) + + +// Register CSC_D_ENTRY_PER_SLICE_0 +#define CSC_D_ENTRY_PER_SLICE_0 _MK_ADDR_CONST(0x4024) +#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ENTRY_PER_SLICE_0_ENTRIES_FIELD _MK_FIELD_CONST(0x3fff, CSC_D_ENTRY_PER_SLICE_0_ENTRIES_SHIFT) + + +// Register CSC_D_WEIGHT_FORMAT_0 +#define CSC_D_WEIGHT_FORMAT_0 _MK_ADDR_CONST(0x4028) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_FIELD _MK_FIELD_CONST(0x1, CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_SHIFT) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_UNCOMPRESSED _MK_ENUM_CONST(0x0) +#define CSC_D_WEIGHT_FORMAT_0_WEIGHT_FORMAT_COMPRESSED _MK_ENUM_CONST(0x1) + + +// Register CSC_D_WEIGHT_SIZE_EXT_0_0 +#define CSC_D_WEIGHT_SIZE_EXT_0_0 _MK_ADDR_CONST(0x402c) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_WIDTH_EXT_SHIFT) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_WEIGHT_SIZE_EXT_0_0_WEIGHT_HEIGHT_EXT_SHIFT) + + +// Register CSC_D_WEIGHT_SIZE_EXT_1_0 +#define CSC_D_WEIGHT_SIZE_EXT_1_0 _MK_ADDR_CONST(0x4030) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_CHANNEL_EXT_SHIFT) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_WEIGHT_SIZE_EXT_1_0_WEIGHT_KERNEL_SHIFT) + + +// Register CSC_D_WEIGHT_BYTES_0 +#define CSC_D_WEIGHT_BYTES_0 _MK_ADDR_CONST(0x4034) +#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_FIELD _MK_FIELD_CONST(0xffffffff, CSC_D_WEIGHT_BYTES_0_WEIGHT_BYTES_SHIFT) + + +// Register CSC_D_WMB_BYTES_0 +#define CSC_D_WMB_BYTES_0 _MK_ADDR_CONST(0x4038) +#define CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_WMB_BYTES_0_WMB_BYTES_FIELD _MK_FIELD_CONST(0xfffffff, CSC_D_WMB_BYTES_0_WMB_BYTES_SHIFT) + + +// Register CSC_D_DATAOUT_SIZE_0_0 +#define CSC_D_DATAOUT_SIZE_0_0 _MK_ADDR_CONST(0x403c) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT) + + +// Register CSC_D_DATAOUT_SIZE_1_0 +#define CSC_D_DATAOUT_SIZE_1_0 _MK_ADDR_CONST(0x4040) +#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CSC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT) + + +// Register CSC_D_ATOMICS_0 +#define CSC_D_ATOMICS_0 _MK_ADDR_CONST(0x4044) +#define CSC_D_ATOMICS_0_ATOMICS_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ATOMICS_0_ATOMICS_FIELD _MK_FIELD_CONST(0x1fffff, CSC_D_ATOMICS_0_ATOMICS_SHIFT) + + +// Register CSC_D_RELEASE_0 +#define CSC_D_RELEASE_0 _MK_ADDR_CONST(0x4048) +#define CSC_D_RELEASE_0_RLS_SLICES_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_RELEASE_0_RLS_SLICES_FIELD _MK_FIELD_CONST(0xfff, CSC_D_RELEASE_0_RLS_SLICES_SHIFT) + + +// Register CSC_D_CONV_STRIDE_EXT_0 +#define CSC_D_CONV_STRIDE_EXT_0 _MK_ADDR_CONST(0x404c) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_FIELD _MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_X_STRIDE_EXT_SHIFT) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_FIELD _MK_FIELD_CONST(0x7, CSC_D_CONV_STRIDE_EXT_0_CONV_Y_STRIDE_EXT_SHIFT) + + +// Register CSC_D_DILATION_EXT_0 +#define CSC_D_DILATION_EXT_0 _MK_ADDR_CONST(0x4050) +#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_DILATION_EXT_0_X_DILATION_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_X_DILATION_EXT_SHIFT) +#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_DILATION_EXT_0_Y_DILATION_EXT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_DILATION_EXT_0_Y_DILATION_EXT_SHIFT) + + +// Register CSC_D_ZERO_PADDING_0 +#define CSC_D_ZERO_PADDING_0 _MK_ADDR_CONST(0x4054) +#define CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ZERO_PADDING_0_PAD_LEFT_FIELD _MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_LEFT_SHIFT) +#define CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_ZERO_PADDING_0_PAD_TOP_FIELD _MK_FIELD_CONST(0x1f, CSC_D_ZERO_PADDING_0_PAD_TOP_SHIFT) + + +// Register CSC_D_ZERO_PADDING_VALUE_0 +#define CSC_D_ZERO_PADDING_VALUE_0 _MK_ADDR_CONST(0x4058) +#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_FIELD _MK_FIELD_CONST(0xffff, CSC_D_ZERO_PADDING_VALUE_0_PAD_VALUE_SHIFT) + + +// Register CSC_D_BANK_0 +#define CSC_D_BANK_0 _MK_ADDR_CONST(0x405c) +#define CSC_D_BANK_0_DATA_BANK_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_BANK_0_DATA_BANK_FIELD _MK_FIELD_CONST(0x1f, CSC_D_BANK_0_DATA_BANK_SHIFT) +#define CSC_D_BANK_0_WEIGHT_BANK_SHIFT _MK_SHIFT_CONST(16) +#define CSC_D_BANK_0_WEIGHT_BANK_FIELD _MK_FIELD_CONST(0x1f, CSC_D_BANK_0_WEIGHT_BANK_SHIFT) + + +// Register CSC_D_PRA_CFG_0 +#define CSC_D_PRA_CFG_0 _MK_ADDR_CONST(0x4060) +#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_PRA_CFG_0_PRA_TRUNCATE_FIELD _MK_FIELD_CONST(0x3, CSC_D_PRA_CFG_0_PRA_TRUNCATE_SHIFT) + + +// Register CSC_D_CYA_0 +#define CSC_D_CYA_0 _MK_ADDR_CONST(0x4064) +#define CSC_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CSC_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CSC_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CMAC_A_S_STATUS_0 +#define CMAC_A_S_STATUS_0 _MK_ADDR_CONST(0x5000) +#define CMAC_A_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_0_SHIFT) +#define CMAC_A_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_A_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_A_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CMAC_A_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_A_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CMAC_A_S_STATUS_0_STATUS_1_SHIFT) +#define CMAC_A_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_A_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_A_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CMAC_A_S_POINTER_0 +#define CMAC_A_S_POINTER_0 _MK_ADDR_CONST(0x5004) +#define CMAC_A_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_PRODUCER_SHIFT) +#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_A_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CMAC_A_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_A_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CMAC_A_S_POINTER_0_CONSUMER_SHIFT) +#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_A_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CMAC_A_D_OP_ENABLE_0 +#define CMAC_A_D_OP_ENABLE_0 _MK_ADDR_CONST(0x5008) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CMAC_A_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CMAC_A_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CMAC_A_D_MISC_CFG_0 +#define CMAC_A_D_MISC_CFG_0 _MK_ADDR_CONST(0x500c) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CMAC_A_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CMAC_A_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CMAC_A_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CMAC_A_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CMAC_B_S_STATUS_0 +#define CMAC_B_S_STATUS_0 _MK_ADDR_CONST(0x6000) +#define CMAC_B_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_0_SHIFT) +#define CMAC_B_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_B_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_B_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CMAC_B_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_B_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CMAC_B_S_STATUS_0_STATUS_1_SHIFT) +#define CMAC_B_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CMAC_B_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CMAC_B_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CMAC_B_S_POINTER_0 +#define CMAC_B_S_POINTER_0 _MK_ADDR_CONST(0x6004) +#define CMAC_B_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_PRODUCER_SHIFT) +#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_B_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CMAC_B_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CMAC_B_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CMAC_B_S_POINTER_0_CONSUMER_SHIFT) +#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CMAC_B_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CMAC_B_D_OP_ENABLE_0 +#define CMAC_B_D_OP_ENABLE_0 _MK_ADDR_CONST(0x6008) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CMAC_B_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CMAC_B_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CMAC_B_D_MISC_CFG_0 +#define CMAC_B_D_MISC_CFG_0 _MK_ADDR_CONST(0x600c) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CMAC_B_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CMAC_B_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CMAC_B_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CMAC_B_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CACC_S_STATUS_0 +#define CACC_S_STATUS_0 _MK_ADDR_CONST(0x7000) +#define CACC_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CACC_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_0_SHIFT) +#define CACC_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CACC_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CACC_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CACC_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CACC_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CACC_S_STATUS_0_STATUS_1_SHIFT) +#define CACC_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CACC_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CACC_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CACC_S_POINTER_0 +#define CACC_S_POINTER_0 _MK_ADDR_CONST(0x7004) +#define CACC_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CACC_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CACC_S_POINTER_0_PRODUCER_SHIFT) +#define CACC_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CACC_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CACC_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CACC_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CACC_S_POINTER_0_CONSUMER_SHIFT) +#define CACC_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CACC_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CACC_D_OP_ENABLE_0 +#define CACC_D_OP_ENABLE_0 _MK_ADDR_CONST(0x7008) +#define CACC_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CACC_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CACC_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CACC_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CACC_D_MISC_CFG_0 +#define CACC_D_MISC_CFG_0 _MK_ADDR_CONST(0x700c) +#define CACC_D_MISC_CFG_0_CONV_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_MISC_CFG_0_CONV_MODE_FIELD _MK_FIELD_CONST(0x1, CACC_D_MISC_CFG_0_CONV_MODE_SHIFT) +#define CACC_D_MISC_CFG_0_CONV_MODE_DIRECT _MK_ENUM_CONST(0x0) +#define CACC_D_MISC_CFG_0_CONV_MODE_WINOGRAD _MK_ENUM_CONST(0x1) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(12) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, CACC_D_MISC_CFG_0_PROC_PRECISION_SHIFT) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define CACC_D_MISC_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + +// Register CACC_D_DATAOUT_SIZE_0_0 +#define CACC_D_DATAOUT_SIZE_0_0 _MK_ADDR_CONST(0x7010) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_WIDTH_SHIFT) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_0_0_DATAOUT_HEIGHT_SHIFT) + + +// Register CACC_D_DATAOUT_SIZE_1_0 +#define CACC_D_DATAOUT_SIZE_1_0 _MK_ADDR_CONST(0x7014) +#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CACC_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT) + + +// Register CACC_D_DATAOUT_ADDR_0 +#define CACC_D_DATAOUT_ADDR_0 _MK_ADDR_CONST(0x7018) +#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_FIELD _MK_FIELD_CONST(0xffffffff, CACC_D_DATAOUT_ADDR_0_DATAOUT_ADDR_SHIFT) + + +// Register CACC_D_BATCH_NUMBER_0 +#define CACC_D_BATCH_NUMBER_0 _MK_ADDR_CONST(0x701c) +#define CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_BATCH_NUMBER_0_BATCHES_FIELD _MK_FIELD_CONST(0x1f, CACC_D_BATCH_NUMBER_0_BATCHES_SHIFT) + + +// Register CACC_D_LINE_STRIDE_0 +#define CACC_D_LINE_STRIDE_0 _MK_ADDR_CONST(0x7020) +#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_LINE_STRIDE_0_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffff, CACC_D_LINE_STRIDE_0_LINE_STRIDE_SHIFT) + + +// Register CACC_D_SURF_STRIDE_0 +#define CACC_D_SURF_STRIDE_0 _MK_ADDR_CONST(0x7024) +#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_SURF_STRIDE_0_SURF_STRIDE_FIELD _MK_FIELD_CONST(0xffffff, CACC_D_SURF_STRIDE_0_SURF_STRIDE_SHIFT) + + +// Register CACC_D_DATAOUT_MAP_0 +#define CACC_D_DATAOUT_MAP_0 _MK_ADDR_CONST(0x7028) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FIELD _MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_LINE_PACKED_SHIFT) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CACC_D_DATAOUT_MAP_0_LINE_PACKED_TRUE _MK_ENUM_CONST(0x1) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT _MK_SHIFT_CONST(16) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FIELD _MK_FIELD_CONST(0x1, CACC_D_DATAOUT_MAP_0_SURF_PACKED_SHIFT) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_FALSE _MK_ENUM_CONST(0x0) +#define CACC_D_DATAOUT_MAP_0_SURF_PACKED_TRUE _MK_ENUM_CONST(0x1) + + +// Register CACC_D_CLIP_CFG_0 +#define CACC_D_CLIP_CFG_0 _MK_ADDR_CONST(0x702c) +#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_FIELD _MK_FIELD_CONST(0x1f, CACC_D_CLIP_CFG_0_CLIP_TRUNCATE_SHIFT) + + +// Register CACC_D_OUT_SATURATION_0 +#define CACC_D_OUT_SATURATION_0 _MK_ADDR_CONST(0x7030) +#define CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_OUT_SATURATION_0_SAT_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, CACC_D_OUT_SATURATION_0_SAT_COUNT_SHIFT) + + +// Register CACC_D_CYA_0 +#define CACC_D_CYA_0 _MK_ADDR_CONST(0x7034) +#define CACC_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CACC_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CACC_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register SDP_RDMA_S_STATUS_0 +#define SDP_RDMA_S_STATUS_0 _MK_ADDR_CONST(0x8000) +#define SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_0_SHIFT) +#define SDP_RDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_RDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define SDP_RDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_S_STATUS_0_STATUS_1_SHIFT) +#define SDP_RDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_RDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register SDP_RDMA_S_POINTER_0 +#define SDP_RDMA_S_POINTER_0 _MK_ADDR_CONST(0x8004) +#define SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_PRODUCER_SHIFT) +#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define SDP_RDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_S_POINTER_0_CONSUMER_SHIFT) +#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_OP_ENABLE_0 +#define SDP_RDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0x8008) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_DATA_CUBE_WIDTH_0 +#define SDP_RDMA_D_DATA_CUBE_WIDTH_0 _MK_ADDR_CONST(0x800c) +#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT) + + +// Register SDP_RDMA_D_DATA_CUBE_HEIGHT_0 +#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0 _MK_ADDR_CONST(0x8010) +#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT) + + +// Register SDP_RDMA_D_DATA_CUBE_CHANNEL_0 +#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0 _MK_ADDR_CONST(0x8014) +#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, SDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT) + + +// Register SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x8018) +#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x801c) +#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_SRC_LINE_STRIDE_0 +#define SDP_RDMA_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0x8020) +#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_SRC_SURFACE_STRIDE_0 +#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8024) +#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BRDMA_CFG_0 +#define SDP_RDMA_D_BRDMA_CFG_0 _MK_ADDR_CONST(0x8028) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DISABLE_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_MUL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_ALU _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_USE_BOTH _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT _MK_SHIFT_CONST(3) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_ONE_BYTE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_SIZE_TWO_BYTE _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_KERNEL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_DATA_MODE_PER_ELEMENT _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_BRDMA_CFG_0_BRDMA_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_BS_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x802c) +#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_LOW_0_BS_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x8030) +#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BASE_ADDR_HIGH_0_BS_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_BS_LINE_STRIDE_0 +#define SDP_RDMA_D_BS_LINE_STRIDE_0 _MK_ADDR_CONST(0x8034) +#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_LINE_STRIDE_0_BS_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BS_SURFACE_STRIDE_0 +#define SDP_RDMA_D_BS_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8038) +#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_SURFACE_STRIDE_0_BS_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BS_BATCH_STRIDE_0 +#define SDP_RDMA_D_BS_BATCH_STRIDE_0 _MK_ADDR_CONST(0x803c) +#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BS_BATCH_STRIDE_0_BS_BATCH_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_NRDMA_CFG_0 +#define SDP_RDMA_D_NRDMA_CFG_0 _MK_ADDR_CONST(0x8040) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DISABLE_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_MUL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_ALU _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_USE_BOTH _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT _MK_SHIFT_CONST(3) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_ONE_BYTE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_SIZE_TWO_BYTE _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_KERNEL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_DATA_MODE_PER_ELEMENT _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_NRDMA_CFG_0_NRDMA_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_BN_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x8044) +#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_LOW_0_BN_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x8048) +#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BASE_ADDR_HIGH_0_BN_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_BN_LINE_STRIDE_0 +#define SDP_RDMA_D_BN_LINE_STRIDE_0 _MK_ADDR_CONST(0x804c) +#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_LINE_STRIDE_0_BN_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BN_SURFACE_STRIDE_0 +#define SDP_RDMA_D_BN_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8050) +#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_SURFACE_STRIDE_0_BN_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_BN_BATCH_STRIDE_0 +#define SDP_RDMA_D_BN_BATCH_STRIDE_0 _MK_ADDR_CONST(0x8054) +#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_BN_BATCH_STRIDE_0_BN_BATCH_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_ERDMA_CFG_0 +#define SDP_RDMA_D_ERDMA_CFG_0 _MK_ADDR_CONST(0x8058) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DISABLE_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_MUL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_ALU _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_USE_BOTH _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT _MK_SHIFT_CONST(3) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_ONE_BYTE _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_SIZE_TWO_BYTE _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_KERNEL _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_DATA_MODE_PER_ELEMENT _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_ERDMA_CFG_0_ERDMA_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_EW_BASE_ADDR_LOW_0 +#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x805c) +#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_LOW_0_EW_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 +#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x8060) +#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BASE_ADDR_HIGH_0_EW_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_RDMA_D_EW_LINE_STRIDE_0 +#define SDP_RDMA_D_EW_LINE_STRIDE_0 _MK_ADDR_CONST(0x8064) +#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_LINE_STRIDE_0_EW_LINE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_EW_SURFACE_STRIDE_0 +#define SDP_RDMA_D_EW_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x8068) +#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_SURFACE_STRIDE_0_EW_SURFACE_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_EW_BATCH_STRIDE_0 +#define SDP_RDMA_D_EW_BATCH_STRIDE_0 _MK_ADDR_CONST(0x806c) +#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_EW_BATCH_STRIDE_0_EW_BATCH_STRIDE_SHIFT) + + +// Register SDP_RDMA_D_FEATURE_MODE_CFG_0 +#define SDP_RDMA_D_FEATURE_MODE_CFG_0 _MK_ADDR_CONST(0x8070) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_WINOGRAD_ON _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(4) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT _MK_SHIFT_CONST(6) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_SHIFT) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_OUT_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT _MK_SHIFT_CONST(8) +#define SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD _MK_FIELD_CONST(0x1f, SDP_RDMA_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT) + + +// Register SDP_RDMA_D_SRC_DMA_CFG_0 +#define SDP_RDMA_D_SRC_DMA_CFG_0 _MK_ADDR_CONST(0x8074) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0 +#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0x8078) +#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT) + + +// Register SDP_RDMA_D_STATUS_INF_INPUT_NUM_0 +#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0 _MK_ADDR_CONST(0x807c) +#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT) + + +// Register SDP_RDMA_D_PERF_ENABLE_0 +#define SDP_RDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x8080) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_DMA_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT _MK_SHIFT_CONST(1) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_RDMA_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_RDMA_D_PERF_MRDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0 _MK_ADDR_CONST(0x8084) +#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_MRDMA_READ_STALL_0_MRDMA_STALL_SHIFT) + + +// Register SDP_RDMA_D_PERF_BRDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0 _MK_ADDR_CONST(0x8088) +#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_BRDMA_READ_STALL_0_BRDMA_STALL_SHIFT) + + +// Register SDP_RDMA_D_PERF_NRDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0 _MK_ADDR_CONST(0x808c) +#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_NRDMA_READ_STALL_0_NRDMA_STALL_SHIFT) + + +// Register SDP_RDMA_D_PERF_ERDMA_READ_STALL_0 +#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0 _MK_ADDR_CONST(0x8090) +#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_RDMA_D_PERF_ERDMA_READ_STALL_0_ERDMA_STALL_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register SDP_S_STATUS_0 +#define SDP_S_STATUS_0 _MK_ADDR_CONST(0x9000) +#define SDP_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_0_SHIFT) +#define SDP_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define SDP_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define SDP_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, SDP_S_STATUS_0_STATUS_1_SHIFT) +#define SDP_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define SDP_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define SDP_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register SDP_S_POINTER_0 +#define SDP_S_POINTER_0 _MK_ADDR_CONST(0x9004) +#define SDP_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, SDP_S_POINTER_0_PRODUCER_SHIFT) +#define SDP_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define SDP_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, SDP_S_POINTER_0_CONSUMER_SHIFT) +#define SDP_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define SDP_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register SDP_S_LUT_ACCESS_CFG_0 +#define SDP_S_LUT_ACCESS_CFG_0 _MK_ADDR_CONST(0x9008) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD _MK_FIELD_CONST(0x3ff, SDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(17) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE _MK_ENUM_CONST(0x1) + + +// Register SDP_S_LUT_ACCESS_DATA_0 +#define SDP_S_LUT_ACCESS_DATA_0 _MK_ADDR_CONST(0x900c) +#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT) + + +// Register SDP_S_LUT_CFG_0 +#define SDP_S_LUT_CFG_0 _MK_ADDR_CONST(0x9010) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(4) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(5) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT _MK_SHIFT_CONST(6) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD _MK_FIELD_CONST(0x1, SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define SDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO _MK_ENUM_CONST(0x1) + + +// Register SDP_S_LUT_INFO_0 +#define SDP_S_LUT_INFO_0 _MK_ADDR_CONST(0x9014) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT) +#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, SDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT) + + +// Register SDP_S_LUT_LE_START_0 +#define SDP_S_LUT_LE_START_0 _MK_ADDR_CONST(0x9018) +#define SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_START_0_LUT_LE_START_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_START_0_LUT_LE_START_SHIFT) + + +// Register SDP_S_LUT_LE_END_0 +#define SDP_S_LUT_LE_END_0 _MK_ADDR_CONST(0x901c) +#define SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_END_0_LUT_LE_END_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LE_END_0_LUT_LE_END_SHIFT) + + +// Register SDP_S_LUT_LO_START_0 +#define SDP_S_LUT_LO_START_0 _MK_ADDR_CONST(0x9020) +#define SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_START_0_LUT_LO_START_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_START_0_LUT_LO_START_SHIFT) + + +// Register SDP_S_LUT_LO_END_0 +#define SDP_S_LUT_LO_END_0 _MK_ADDR_CONST(0x9024) +#define SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_END_0_LUT_LO_END_FIELD _MK_FIELD_CONST(0xffffffff, SDP_S_LUT_LO_END_0_LUT_LO_END_SHIFT) + + +// Register SDP_S_LUT_LE_SLOPE_SCALE_0 +#define SDP_S_LUT_LE_SLOPE_SCALE_0 _MK_ADDR_CONST(0x9028) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register SDP_S_LUT_LE_SLOPE_SHIFT_0 +#define SDP_S_LUT_LE_SLOPE_SHIFT_0 _MK_ADDR_CONST(0x902c) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register SDP_S_LUT_LO_SLOPE_SCALE_0 +#define SDP_S_LUT_LO_SLOPE_SCALE_0 _MK_ADDR_CONST(0x9030) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register SDP_S_LUT_LO_SLOPE_SHIFT_0 +#define SDP_S_LUT_LO_SLOPE_SHIFT_0 _MK_ADDR_CONST(0x9034) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, SDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register SDP_D_OP_ENABLE_0 +#define SDP_D_OP_ENABLE_0 _MK_ADDR_CONST(0x9038) +#define SDP_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_OP_ENABLE_0_OP_EN_SHIFT) +#define SDP_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define SDP_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DATA_CUBE_WIDTH_0 +#define SDP_D_DATA_CUBE_WIDTH_0 _MK_ADDR_CONST(0x903c) +#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT) + + +// Register SDP_D_DATA_CUBE_HEIGHT_0 +#define SDP_D_DATA_CUBE_HEIGHT_0 _MK_ADDR_CONST(0x9040) +#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT) + + +// Register SDP_D_DATA_CUBE_CHANNEL_0 +#define SDP_D_DATA_CUBE_CHANNEL_0 _MK_ADDR_CONST(0x9044) +#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, SDP_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT) + + +// Register SDP_D_DST_BASE_ADDR_LOW_0 +#define SDP_D_DST_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0x9048) +#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT) + + +// Register SDP_D_DST_BASE_ADDR_HIGH_0 +#define SDP_D_DST_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0x904c) +#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT) + + +// Register SDP_D_DST_LINE_STRIDE_0 +#define SDP_D_DST_LINE_STRIDE_0 _MK_ADDR_CONST(0x9050) +#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT) + + +// Register SDP_D_DST_SURFACE_STRIDE_0 +#define SDP_D_DST_SURFACE_STRIDE_0 _MK_ADDR_CONST(0x9054) +#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT) + + +// Register SDP_D_DP_BS_CFG_0 +#define SDP_D_DP_BS_CFG_0 _MK_ADDR_CONST(0x9058) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_ALU_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_FIELD _MK_FIELD_CONST(0x3, SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MAX _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_MIN _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_ALU_ALGO_SUM _MK_ENUM_CONST(0x2) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(4) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_MUL_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT _MK_SHIFT_CONST(5) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_MUL_PRELU_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT _MK_SHIFT_CONST(6) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_SHIFT) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_CFG_0_BS_RELU_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_BS_ALU_CFG_0 +#define SDP_D_DP_BS_ALU_CFG_0 _MK_ADDR_CONST(0x905c) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_SHIFT) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_BS_ALU_CFG_0_BS_ALU_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BS_ALU_SRC_VALUE_0 +#define SDP_D_DP_BS_ALU_SRC_VALUE_0 _MK_ADDR_CONST(0x9060) +#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BS_ALU_SRC_VALUE_0_BS_ALU_OPERAND_SHIFT) + + +// Register SDP_D_DP_BS_MUL_CFG_0 +#define SDP_D_DP_BS_MUL_CFG_0 _MK_ADDR_CONST(0x9064) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_SHIFT) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0xff, SDP_D_DP_BS_MUL_CFG_0_BS_MUL_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BS_MUL_SRC_VALUE_0 +#define SDP_D_DP_BS_MUL_SRC_VALUE_0 _MK_ADDR_CONST(0x9068) +#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BS_MUL_SRC_VALUE_0_BS_MUL_OPERAND_SHIFT) + + +// Register SDP_D_DP_BN_CFG_0 +#define SDP_D_DP_BN_CFG_0 _MK_ADDR_CONST(0x906c) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_ALU_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_FIELD _MK_FIELD_CONST(0x3, SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MAX _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_MIN _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_ALU_ALGO_SUM _MK_ENUM_CONST(0x2) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(4) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_MUL_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT _MK_SHIFT_CONST(5) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_MUL_PRELU_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT _MK_SHIFT_CONST(6) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_SHIFT) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_CFG_0_BN_RELU_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_BN_ALU_CFG_0 +#define SDP_D_DP_BN_ALU_CFG_0 _MK_ADDR_CONST(0x9070) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_SHIFT) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_BN_ALU_CFG_0_BN_ALU_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BN_ALU_SRC_VALUE_0 +#define SDP_D_DP_BN_ALU_SRC_VALUE_0 _MK_ADDR_CONST(0x9074) +#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BN_ALU_SRC_VALUE_0_BN_ALU_OPERAND_SHIFT) + + +// Register SDP_D_DP_BN_MUL_CFG_0 +#define SDP_D_DP_BN_MUL_CFG_0 _MK_ADDR_CONST(0x9078) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_SHIFT) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_FIELD _MK_FIELD_CONST(0xff, SDP_D_DP_BN_MUL_CFG_0_BN_MUL_SHIFT_VALUE_SHIFT) + + +// Register SDP_D_DP_BN_MUL_SRC_VALUE_0 +#define SDP_D_DP_BN_MUL_SRC_VALUE_0 _MK_ADDR_CONST(0x907c) +#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_BN_MUL_SRC_VALUE_0_BN_MUL_OPERAND_SHIFT) + + +// Register SDP_D_DP_EW_CFG_0 +#define SDP_D_DP_EW_CFG_0 _MK_ADDR_CONST(0x9080) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_ALU_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_FIELD _MK_FIELD_CONST(0x3, SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MAX _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_MIN _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_SUM _MK_ENUM_CONST(0x2) +#define SDP_D_DP_EW_CFG_0_EW_ALU_ALGO_EQL _MK_ENUM_CONST(0x3) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(4) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_MUL_BYPASS_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT _MK_SHIFT_CONST(5) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_MUL_PRELU_YES _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT _MK_SHIFT_CONST(6) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_SHIFT) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_CFG_0_EW_LUT_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_EW_ALU_CFG_0 +#define SDP_D_DP_EW_ALU_CFG_0 _MK_ADDR_CONST(0x9084) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_SHIFT) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_SHIFT) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_ALU_CFG_0_EW_ALU_CVT_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_EW_ALU_SRC_VALUE_0 +#define SDP_D_DP_EW_ALU_SRC_VALUE_0 _MK_ADDR_CONST(0x9088) +#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_SRC_VALUE_0_EW_ALU_OPERAND_SHIFT) + + +// Register SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 +#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0 _MK_ADDR_CONST(0x908c) +#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_ALU_CVT_OFFSET_VALUE_0_EW_ALU_CVT_OFFSET_SHIFT) + + +// Register SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 +#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0 _MK_ADDR_CONST(0x9090) +#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_EW_ALU_CVT_SCALE_VALUE_0_EW_ALU_CVT_SCALE_SHIFT) + + +// Register SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 +#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0 _MK_ADDR_CONST(0x9094) +#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_EW_ALU_CVT_TRUNCATE_VALUE_0_EW_ALU_CVT_TRUNCATE_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CFG_0 +#define SDP_D_DP_EW_MUL_CFG_0 _MK_ADDR_CONST(0x9098) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_SHIFT) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_REG _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_SRC_MEM _MK_ENUM_CONST(0x1) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_FIELD _MK_FIELD_CONST(0x1, SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_SHIFT) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_NO _MK_ENUM_CONST(0x0) +#define SDP_D_DP_EW_MUL_CFG_0_EW_MUL_CVT_BYPASS_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DP_EW_MUL_SRC_VALUE_0 +#define SDP_D_DP_EW_MUL_SRC_VALUE_0 _MK_ADDR_CONST(0x909c) +#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_SRC_VALUE_0_EW_MUL_OPERAND_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 +#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0 _MK_ADDR_CONST(0x90a0) +#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DP_EW_MUL_CVT_OFFSET_VALUE_0_EW_MUL_CVT_OFFSET_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 +#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0 _MK_ADDR_CONST(0x90a4) +#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_D_DP_EW_MUL_CVT_SCALE_VALUE_0_EW_MUL_CVT_SCALE_SHIFT) + + +// Register SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 +#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0 _MK_ADDR_CONST(0x90a8) +#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_FIELD _MK_FIELD_CONST(0x3f, SDP_D_DP_EW_MUL_CVT_TRUNCATE_VALUE_0_EW_MUL_CVT_TRUNCATE_SHIFT) + + +// Register SDP_D_DP_EW_TRUNCATE_VALUE_0 +#define SDP_D_DP_EW_TRUNCATE_VALUE_0 _MK_ADDR_CONST(0x90ac) +#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_FIELD _MK_FIELD_CONST(0x3ff, SDP_D_DP_EW_TRUNCATE_VALUE_0_EW_TRUNCATE_SHIFT) + + +// Register SDP_D_FEATURE_MODE_CFG_0 +#define SDP_D_FEATURE_MODE_CFG_0 _MK_ADDR_CONST(0x90b0) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_OFF _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_FLYING_MODE_ON _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_MEM _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_OUTPUT_DST_PDP _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_OFF _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_WINOGRAD_ON _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(3) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_SHIFT) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define SDP_D_FEATURE_MODE_CFG_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) +#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT _MK_SHIFT_CONST(8) +#define SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_FIELD _MK_FIELD_CONST(0x1f, SDP_D_FEATURE_MODE_CFG_0_BATCH_NUMBER_SHIFT) + + +// Register SDP_D_DST_DMA_CFG_0 +#define SDP_D_DST_DMA_CFG_0 _MK_ADDR_CONST(0x90b4) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define SDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register SDP_D_DST_BATCH_STRIDE_0 +#define SDP_D_DST_BATCH_STRIDE_0 _MK_ADDR_CONST(0x90b8) +#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_DST_BATCH_STRIDE_0_DST_BATCH_STRIDE_SHIFT) + + +// Register SDP_D_DATA_FORMAT_0 +#define SDP_D_DATA_FORMAT_0 _MK_ADDR_CONST(0x90bc) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_PROC_PRECISION_SHIFT) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_D_DATA_FORMAT_0_PROC_PRECISION_FP16 _MK_ENUM_CONST(0x2) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FIELD _MK_FIELD_CONST(0x3, SDP_D_DATA_FORMAT_0_OUT_PRECISION_SHIFT) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define SDP_D_DATA_FORMAT_0_OUT_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + +// Register SDP_D_CVT_OFFSET_0 +#define SDP_D_CVT_OFFSET_0 _MK_ADDR_CONST(0x90c0) +#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_CVT_OFFSET_0_CVT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_CVT_OFFSET_0_CVT_OFFSET_SHIFT) + + +// Register SDP_D_CVT_SCALE_0 +#define SDP_D_CVT_SCALE_0 _MK_ADDR_CONST(0x90c4) +#define SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_CVT_SCALE_0_CVT_SCALE_FIELD _MK_FIELD_CONST(0xffff, SDP_D_CVT_SCALE_0_CVT_SCALE_SHIFT) + + +// Register SDP_D_CVT_SHIFT_0 +#define SDP_D_CVT_SHIFT_0 _MK_ADDR_CONST(0x90c8) +#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_CVT_SHIFT_0_CVT_SHIFT_FIELD _MK_FIELD_CONST(0x3f, SDP_D_CVT_SHIFT_0_CVT_SHIFT_SHIFT) + + +// Register SDP_D_STATUS_0 +#define SDP_D_STATUS_0 _MK_ADDR_CONST(0x90cc) +#define SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_0_STATUS_UNEQUAL_FIELD _MK_FIELD_CONST(0x1, SDP_D_STATUS_0_STATUS_UNEQUAL_SHIFT) + + +// Register SDP_D_STATUS_NAN_INPUT_NUM_0 +#define SDP_D_STATUS_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0x90d0) +#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_INPUT_NUM_0_STATUS_NAN_INPUT_NUM_SHIFT) + + +// Register SDP_D_STATUS_INF_INPUT_NUM_0 +#define SDP_D_STATUS_INF_INPUT_NUM_0 _MK_ADDR_CONST(0x90d4) +#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_INF_INPUT_NUM_0_STATUS_INF_INPUT_NUM_SHIFT) + + +// Register SDP_D_STATUS_NAN_OUTPUT_NUM_0 +#define SDP_D_STATUS_NAN_OUTPUT_NUM_0 _MK_ADDR_CONST(0x90d8) +#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_STATUS_NAN_OUTPUT_NUM_0_STATUS_NAN_OUTPUT_NUM_SHIFT) + + +// Register SDP_D_PERF_ENABLE_0 +#define SDP_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x90dc) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_DMA_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_DMA_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT _MK_SHIFT_CONST(1) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_LUT_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_LUT_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT _MK_SHIFT_CONST(2) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_SAT_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_SAT_EN_YES _MK_ENUM_CONST(0x1) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT _MK_SHIFT_CONST(3) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_FIELD _MK_FIELD_CONST(0x1, SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_SHIFT) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_NO _MK_ENUM_CONST(0x0) +#define SDP_D_PERF_ENABLE_0_PERF_NAN_INF_COUNT_EN_YES _MK_ENUM_CONST(0x1) + + +// Register SDP_D_PERF_WDMA_WRITE_STALL_0 +#define SDP_D_PERF_WDMA_WRITE_STALL_0 _MK_ADDR_CONST(0x90e0) +#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_WDMA_WRITE_STALL_0_WDMA_STALL_SHIFT) + + +// Register SDP_D_PERF_LUT_UFLOW_0 +#define SDP_D_PERF_LUT_UFLOW_0 _MK_ADDR_CONST(0x90e4) +#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_UFLOW_0_LUT_UFLOW_SHIFT) + + +// Register SDP_D_PERF_LUT_OFLOW_0 +#define SDP_D_PERF_LUT_OFLOW_0 _MK_ADDR_CONST(0x90e8) +#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_OFLOW_0_LUT_OFLOW_SHIFT) + + +// Register SDP_D_PERF_OUT_SATURATION_0 +#define SDP_D_PERF_OUT_SATURATION_0 _MK_ADDR_CONST(0x90ec) +#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_OUT_SATURATION_0_OUT_SATURATION_SHIFT) + + +// Register SDP_D_PERF_LUT_HYBRID_0 +#define SDP_D_PERF_LUT_HYBRID_0 _MK_ADDR_CONST(0x90f0) +#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_HYBRID_0_LUT_HYBRID_SHIFT) + + +// Register SDP_D_PERF_LUT_LE_HIT_0 +#define SDP_D_PERF_LUT_LE_HIT_0 _MK_ADDR_CONST(0x90f4) +#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LE_HIT_0_LUT_LE_HIT_SHIFT) + + +// Register SDP_D_PERF_LUT_LO_HIT_0 +#define SDP_D_PERF_LUT_LO_HIT_0 _MK_ADDR_CONST(0x90f8) +#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT _MK_SHIFT_CONST(0) +#define SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_FIELD _MK_FIELD_CONST(0xffffffff, SDP_D_PERF_LUT_LO_HIT_0_LUT_LO_HIT_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register PDP_RDMA_S_STATUS_0 +#define PDP_RDMA_S_STATUS_0 _MK_ADDR_CONST(0xa000) +#define PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_0_SHIFT) +#define PDP_RDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_RDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define PDP_RDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, PDP_RDMA_S_STATUS_0_STATUS_1_SHIFT) +#define PDP_RDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_RDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register PDP_RDMA_S_POINTER_0 +#define PDP_RDMA_S_POINTER_0 _MK_ADDR_CONST(0xa004) +#define PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_PRODUCER_SHIFT) +#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define PDP_RDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_S_POINTER_0_CONSUMER_SHIFT) +#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_OP_ENABLE_0 +#define PDP_RDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0xa008) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 +#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0 _MK_ADDR_CONST(0xa00c) +#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT) + + +// Register PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 +#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0 _MK_ADDR_CONST(0xa010) +#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT) + + +// Register PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 +#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0 _MK_ADDR_CONST(0xa014) +#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, PDP_RDMA_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT) + + +// Register PDP_RDMA_D_FLYING_MODE_0 +#define PDP_RDMA_D_FLYING_MODE_0 _MK_ADDR_CONST(0xa018) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_SHIFT) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_ON_FLYING _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_FLYING_MODE_0_FLYING_MODE_OFF_FLYING _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 +#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xa01c) +#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 +#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xa020) +#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register PDP_RDMA_D_SRC_LINE_STRIDE_0 +#define PDP_RDMA_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0xa024) +#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register PDP_RDMA_D_SRC_SURFACE_STRIDE_0 +#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xa028) +#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register PDP_RDMA_D_SRC_RAM_CFG_0 +#define PDP_RDMA_D_SRC_RAM_CFG_0 _MK_ADDR_CONST(0xa02c) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_SHIFT) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_SRC_RAM_CFG_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_DATA_FORMAT_0 +#define PDP_RDMA_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xa030) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x3, PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16 _MK_ENUM_CONST(0x1) +#define PDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16 _MK_ENUM_CONST(0x2) + + +// Register PDP_RDMA_D_OPERATION_MODE_CFG_0 +#define PDP_RDMA_D_OPERATION_MODE_CFG_0 _MK_ADDR_CONST(0xa034) +#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD _MK_FIELD_CONST(0xff, PDP_RDMA_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT) + + +// Register PDP_RDMA_D_POOLING_KERNEL_CFG_0 +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0 _MK_ADDR_CONST(0xa038) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 _MK_ENUM_CONST(0x1) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 _MK_ENUM_CONST(0x2) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 _MK_ENUM_CONST(0x3) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 _MK_ENUM_CONST(0x4) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 _MK_ENUM_CONST(0x5) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 _MK_ENUM_CONST(0x6) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 _MK_ENUM_CONST(0x7) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT _MK_SHIFT_CONST(4) +#define PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT) + + +// Register PDP_RDMA_D_POOLING_PADDING_CFG_0 +#define PDP_RDMA_D_POOLING_PADDING_CFG_0 _MK_ADDR_CONST(0xa03c) +#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_RDMA_D_POOLING_PADDING_CFG_0_PAD_WIDTH_SHIFT) + + +// Register PDP_RDMA_D_PARTIAL_WIDTH_IN_0 +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0 _MK_ADDR_CONST(0xa040) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT _MK_SHIFT_CONST(10) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT _MK_SHIFT_CONST(20) +#define PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD _MK_FIELD_CONST(0x3ff, PDP_RDMA_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT) + + +// Register PDP_RDMA_D_PERF_ENABLE_0 +#define PDP_RDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xa044) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_RDMA_D_PERF_READ_STALL_0 +#define PDP_RDMA_D_PERF_READ_STALL_0 _MK_ADDR_CONST(0xa048) +#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT) + + +// Register PDP_RDMA_D_CYA_0 +#define PDP_RDMA_D_CYA_0 _MK_ADDR_CONST(0xa04c) +#define PDP_RDMA_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_RDMA_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, PDP_RDMA_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register PDP_S_STATUS_0 +#define PDP_S_STATUS_0 _MK_ADDR_CONST(0xb000) +#define PDP_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define PDP_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_0_SHIFT) +#define PDP_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define PDP_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define PDP_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define PDP_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, PDP_S_STATUS_0_STATUS_1_SHIFT) +#define PDP_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define PDP_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define PDP_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register PDP_S_POINTER_0 +#define PDP_S_POINTER_0 _MK_ADDR_CONST(0xb004) +#define PDP_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define PDP_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, PDP_S_POINTER_0_PRODUCER_SHIFT) +#define PDP_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define PDP_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define PDP_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, PDP_S_POINTER_0_CONSUMER_SHIFT) +#define PDP_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define PDP_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register PDP_D_OP_ENABLE_0 +#define PDP_D_OP_ENABLE_0 _MK_ADDR_CONST(0xb008) +#define PDP_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, PDP_D_OP_ENABLE_0_OP_EN_SHIFT) +#define PDP_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_D_DATA_CUBE_IN_WIDTH_0 +#define PDP_D_DATA_CUBE_IN_WIDTH_0 _MK_ADDR_CONST(0xb00c) +#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_WIDTH_0_CUBE_IN_WIDTH_SHIFT) + + +// Register PDP_D_DATA_CUBE_IN_HEIGHT_0 +#define PDP_D_DATA_CUBE_IN_HEIGHT_0 _MK_ADDR_CONST(0xb010) +#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_HEIGHT_0_CUBE_IN_HEIGHT_SHIFT) + + +// Register PDP_D_DATA_CUBE_IN_CHANNEL_0 +#define PDP_D_DATA_CUBE_IN_CHANNEL_0 _MK_ADDR_CONST(0xb014) +#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_IN_CHANNEL_0_CUBE_IN_CHANNEL_SHIFT) + + +// Register PDP_D_DATA_CUBE_OUT_WIDTH_0 +#define PDP_D_DATA_CUBE_OUT_WIDTH_0 _MK_ADDR_CONST(0xb018) +#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_WIDTH_0_CUBE_OUT_WIDTH_SHIFT) + + +// Register PDP_D_DATA_CUBE_OUT_HEIGHT_0 +#define PDP_D_DATA_CUBE_OUT_HEIGHT_0 _MK_ADDR_CONST(0xb01c) +#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_HEIGHT_0_CUBE_OUT_HEIGHT_SHIFT) + + +// Register PDP_D_DATA_CUBE_OUT_CHANNEL_0 +#define PDP_D_DATA_CUBE_OUT_CHANNEL_0 _MK_ADDR_CONST(0xb020) +#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, PDP_D_DATA_CUBE_OUT_CHANNEL_0_CUBE_OUT_CHANNEL_SHIFT) + + +// Register PDP_D_OPERATION_MODE_CFG_0 +#define PDP_D_OPERATION_MODE_CFG_0 _MK_ADDR_CONST(0xb024) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_FIELD _MK_FIELD_CONST(0x3, PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_SHIFT) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_AVERAGE _MK_ENUM_CONST(0x0) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MAX _MK_ENUM_CONST(0x1) +#define PDP_D_OPERATION_MODE_CFG_0_POOLING_METHOD_POOLING_METHOD_MIN _MK_ENUM_CONST(0x2) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT _MK_SHIFT_CONST(4) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_FIELD _MK_FIELD_CONST(0x1, PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_SHIFT) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_ON_FLYING _MK_ENUM_CONST(0x0) +#define PDP_D_OPERATION_MODE_CFG_0_FLYING_MODE_OFF_FLYING _MK_ENUM_CONST(0x1) +#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT _MK_SHIFT_CONST(8) +#define PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_FIELD _MK_FIELD_CONST(0xff, PDP_D_OPERATION_MODE_CFG_0_SPLIT_NUM_SHIFT) + + +// Register PDP_D_NAN_FLUSH_TO_ZERO_0 +#define PDP_D_NAN_FLUSH_TO_ZERO_0 _MK_ADDR_CONST(0xb028) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_D_PARTIAL_WIDTH_IN_0 +#define PDP_D_PARTIAL_WIDTH_IN_0 _MK_ADDR_CONST(0xb02c) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_FIRST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT _MK_SHIFT_CONST(10) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_LAST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT _MK_SHIFT_CONST(20) +#define PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_IN_0_PARTIAL_WIDTH_IN_MID_SHIFT) + + +// Register PDP_D_PARTIAL_WIDTH_OUT_0 +#define PDP_D_PARTIAL_WIDTH_OUT_0 _MK_ADDR_CONST(0xb030) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_FIRST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT _MK_SHIFT_CONST(10) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_LAST_SHIFT) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT _MK_SHIFT_CONST(20) +#define PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_FIELD _MK_FIELD_CONST(0x3ff, PDP_D_PARTIAL_WIDTH_OUT_0_PARTIAL_WIDTH_OUT_MID_SHIFT) + + +// Register PDP_D_POOLING_KERNEL_CFG_0 +#define PDP_D_POOLING_KERNEL_CFG_0 _MK_ADDR_CONST(0xb034) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_SHIFT) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_1 _MK_ENUM_CONST(0x0) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_2 _MK_ENUM_CONST(0x1) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_3 _MK_ENUM_CONST(0x2) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_4 _MK_ENUM_CONST(0x3) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_5 _MK_ENUM_CONST(0x4) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_6 _MK_ENUM_CONST(0x5) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_7 _MK_ENUM_CONST(0x6) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_WIDTH_KERNEL_WIDTH_8 _MK_ENUM_CONST(0x7) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT _MK_SHIFT_CONST(8) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_SHIFT) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_1 _MK_ENUM_CONST(0x0) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_2 _MK_ENUM_CONST(0x1) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_3 _MK_ENUM_CONST(0x2) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_4 _MK_ENUM_CONST(0x3) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_5 _MK_ENUM_CONST(0x4) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_6 _MK_ENUM_CONST(0x5) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_7 _MK_ENUM_CONST(0x6) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_HEIGHT_KERNEL_HEIGHT_8 _MK_ENUM_CONST(0x7) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT _MK_SHIFT_CONST(16) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_WIDTH_SHIFT) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT _MK_SHIFT_CONST(20) +#define PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_FIELD _MK_FIELD_CONST(0xf, PDP_D_POOLING_KERNEL_CFG_0_KERNEL_STRIDE_HEIGHT_SHIFT) + + +// Register PDP_D_RECIP_KERNEL_WIDTH_0 +#define PDP_D_RECIP_KERNEL_WIDTH_0 _MK_ADDR_CONST(0xb038) +#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_FIELD _MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_WIDTH_0_RECIP_KERNEL_WIDTH_SHIFT) + + +// Register PDP_D_RECIP_KERNEL_HEIGHT_0 +#define PDP_D_RECIP_KERNEL_HEIGHT_0 _MK_ADDR_CONST(0xb03c) +#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_FIELD _MK_FIELD_CONST(0x1ffff, PDP_D_RECIP_KERNEL_HEIGHT_0_RECIP_KERNEL_HEIGHT_SHIFT) + + +// Register PDP_D_POOLING_PADDING_CFG_0 +#define PDP_D_POOLING_PADDING_CFG_0 _MK_ADDR_CONST(0xb040) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_LEFT_SHIFT) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT _MK_SHIFT_CONST(4) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_TOP_SHIFT) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT _MK_SHIFT_CONST(8) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_RIGHT_SHIFT) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT _MK_SHIFT_CONST(12) +#define PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_FIELD _MK_FIELD_CONST(0x7, PDP_D_POOLING_PADDING_CFG_0_PAD_BOTTOM_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_1_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0 _MK_ADDR_CONST(0xb044) +#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_1_CFG_0_PAD_VALUE_1X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_2_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0 _MK_ADDR_CONST(0xb048) +#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_2_CFG_0_PAD_VALUE_2X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_3_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0 _MK_ADDR_CONST(0xb04c) +#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_3_CFG_0_PAD_VALUE_3X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_4_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0 _MK_ADDR_CONST(0xb050) +#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_4_CFG_0_PAD_VALUE_4X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_5_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0 _MK_ADDR_CONST(0xb054) +#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_5_CFG_0_PAD_VALUE_5X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_6_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0 _MK_ADDR_CONST(0xb058) +#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_6_CFG_0_PAD_VALUE_6X_SHIFT) + + +// Register PDP_D_POOLING_PADDING_VALUE_7_CFG_0 +#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0 _MK_ADDR_CONST(0xb05c) +#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_FIELD _MK_FIELD_CONST(0x7ffff, PDP_D_POOLING_PADDING_VALUE_7_CFG_0_PAD_VALUE_7X_SHIFT) + + +// Register PDP_D_SRC_BASE_ADDR_LOW_0 +#define PDP_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xb060) +#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register PDP_D_SRC_BASE_ADDR_HIGH_0 +#define PDP_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xb064) +#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register PDP_D_SRC_LINE_STRIDE_0 +#define PDP_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0xb068) +#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register PDP_D_SRC_SURFACE_STRIDE_0 +#define PDP_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xb06c) +#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register PDP_D_DST_BASE_ADDR_LOW_0 +#define PDP_D_DST_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xb070) +#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT) + + +// Register PDP_D_DST_BASE_ADDR_HIGH_0 +#define PDP_D_DST_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xb074) +#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT) + + +// Register PDP_D_DST_LINE_STRIDE_0 +#define PDP_D_DST_LINE_STRIDE_0 _MK_ADDR_CONST(0xb078) +#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT) + + +// Register PDP_D_DST_SURFACE_STRIDE_0 +#define PDP_D_DST_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xb07c) +#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT) + + +// Register PDP_D_DST_RAM_CFG_0 +#define PDP_D_DST_RAM_CFG_0 _MK_ADDR_CONST(0xb080) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_SHIFT) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define PDP_D_DST_RAM_CFG_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register PDP_D_DATA_FORMAT_0 +#define PDP_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xb084) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x3, PDP_D_DATA_FORMAT_0_INPUT_DATA_SHIFT) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT8 _MK_ENUM_CONST(0x0) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_INT16 _MK_ENUM_CONST(0x1) +#define PDP_D_DATA_FORMAT_0_INPUT_DATA_FP16 _MK_ENUM_CONST(0x2) + + +// Register PDP_D_INF_INPUT_NUM_0 +#define PDP_D_INF_INPUT_NUM_0 _MK_ADDR_CONST(0xb088) +#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT) + + +// Register PDP_D_NAN_INPUT_NUM_0 +#define PDP_D_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0xb08c) +#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT) + + +// Register PDP_D_NAN_OUTPUT_NUM_0 +#define PDP_D_NAN_OUTPUT_NUM_0 _MK_ADDR_CONST(0xb090) +#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT) + + +// Register PDP_D_PERF_ENABLE_0 +#define PDP_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xb094) +#define PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, PDP_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define PDP_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define PDP_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register PDP_D_PERF_WRITE_STALL_0 +#define PDP_D_PERF_WRITE_STALL_0 _MK_ADDR_CONST(0xb098) +#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT) + + +// Register PDP_D_CYA_0 +#define PDP_D_CYA_0 _MK_ADDR_CONST(0xb09c) +#define PDP_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define PDP_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, PDP_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CDP_RDMA_S_STATUS_0 +#define CDP_RDMA_S_STATUS_0 _MK_ADDR_CONST(0xc000) +#define CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_0_SHIFT) +#define CDP_RDMA_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_RDMA_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CDP_RDMA_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_S_STATUS_0_STATUS_1_SHIFT) +#define CDP_RDMA_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_RDMA_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CDP_RDMA_S_POINTER_0 +#define CDP_RDMA_S_POINTER_0 _MK_ADDR_CONST(0xc004) +#define CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_PRODUCER_SHIFT) +#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CDP_RDMA_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_S_POINTER_0_CONSUMER_SHIFT) +#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_RDMA_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_OP_ENABLE_0 +#define CDP_RDMA_D_OP_ENABLE_0 _MK_ADDR_CONST(0xc008) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_DATA_CUBE_WIDTH_0 +#define CDP_RDMA_D_DATA_CUBE_WIDTH_0 _MK_ADDR_CONST(0xc00c) +#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_WIDTH_0_WIDTH_SHIFT) + + +// Register CDP_RDMA_D_DATA_CUBE_HEIGHT_0 +#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0 _MK_ADDR_CONST(0xc010) +#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_HEIGHT_0_HEIGHT_SHIFT) + + +// Register CDP_RDMA_D_DATA_CUBE_CHANNEL_0 +#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0 _MK_ADDR_CONST(0xc014) +#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, CDP_RDMA_D_DATA_CUBE_CHANNEL_0_CHANNEL_SHIFT) + + +// Register CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 +#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xc018) +#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_LOW_0_SRC_BASE_ADDR_LOW_SHIFT) + + +// Register CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 +#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xc01c) +#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_BASE_ADDR_HIGH_0_SRC_BASE_ADDR_HIGH_SHIFT) + + +// Register CDP_RDMA_D_SRC_LINE_STRIDE_0 +#define CDP_RDMA_D_SRC_LINE_STRIDE_0 _MK_ADDR_CONST(0xc020) +#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_LINE_STRIDE_0_SRC_LINE_STRIDE_SHIFT) + + +// Register CDP_RDMA_D_SRC_SURFACE_STRIDE_0 +#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xc024) +#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_SRC_SURFACE_STRIDE_0_SRC_SURFACE_STRIDE_SHIFT) + + +// Register CDP_RDMA_D_SRC_DMA_CFG_0 +#define CDP_RDMA_D_SRC_DMA_CFG_0 _MK_ADDR_CONST(0xc028) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_SHIFT) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_SRC_DMA_CFG_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_SRC_COMPRESSION_EN_0 +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0 _MK_ADDR_CONST(0xc02c) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_SHIFT) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_SRC_COMPRESSION_EN_0_SRC_COMPRESSION_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_OPERATION_MODE_0 +#define CDP_RDMA_D_OPERATION_MODE_0 _MK_ADDR_CONST(0xc030) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_SHIFT) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_READPHILE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_WRITEPHILE _MK_ENUM_CONST(0x1) +#define CDP_RDMA_D_OPERATION_MODE_0_OPERATION_MODE_ORDINARY _MK_ENUM_CONST(0x2) + + +// Register CDP_RDMA_D_DATA_FORMAT_0 +#define CDP_RDMA_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xc034) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x3, CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_SHIFT) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT8 _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_INT16 _MK_ENUM_CONST(0x1) +#define CDP_RDMA_D_DATA_FORMAT_0_INPUT_DATA_FP16 _MK_ENUM_CONST(0x2) + + +// Register CDP_RDMA_D_PERF_ENABLE_0 +#define CDP_RDMA_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xc038) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_RDMA_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_RDMA_D_PERF_READ_STALL_0 +#define CDP_RDMA_D_PERF_READ_STALL_0 _MK_ADDR_CONST(0xc03c) +#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_PERF_READ_STALL_0_PERF_READ_STALL_SHIFT) + + +// Register CDP_RDMA_D_CYA_0 +#define CDP_RDMA_D_CYA_0 _MK_ADDR_CONST(0xc040) +#define CDP_RDMA_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_RDMA_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CDP_RDMA_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register CDP_S_STATUS_0 +#define CDP_S_STATUS_0 _MK_ADDR_CONST(0xd000) +#define CDP_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_0_SHIFT) +#define CDP_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define CDP_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define CDP_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, CDP_S_STATUS_0_STATUS_1_SHIFT) +#define CDP_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define CDP_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define CDP_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register CDP_S_POINTER_0 +#define CDP_S_POINTER_0 _MK_ADDR_CONST(0xd004) +#define CDP_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, CDP_S_POINTER_0_PRODUCER_SHIFT) +#define CDP_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define CDP_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, CDP_S_POINTER_0_CONSUMER_SHIFT) +#define CDP_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define CDP_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register CDP_S_LUT_ACCESS_CFG_0 +#define CDP_S_LUT_ACCESS_CFG_0 _MK_ADDR_CONST(0xd008) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_FIELD _MK_FIELD_CONST(0x3ff, CDP_S_LUT_ACCESS_CFG_0_LUT_ADDR_SHIFT) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_SHIFT) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_TABLE_ID_LO _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT _MK_SHIFT_CONST(17) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_SHIFT) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_READ _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_ACCESS_CFG_0_LUT_ACCESS_TYPE_WRITE _MK_ENUM_CONST(0x1) + + +// Register CDP_S_LUT_ACCESS_DATA_0 +#define CDP_S_LUT_ACCESS_DATA_0 _MK_ADDR_CONST(0xd00c) +#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_ACCESS_DATA_0_LUT_DATA_SHIFT) + + +// Register CDP_S_LUT_CFG_0 +#define CDP_S_LUT_CFG_0 _MK_ADDR_CONST(0xd010) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_EXPONENT _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_LE_FUNCTION_LINEAR _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(4) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_UFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT _MK_SHIFT_CONST(5) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_OFLOW_PRIORITY_LO _MK_ENUM_CONST(0x1) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT _MK_SHIFT_CONST(6) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_FIELD _MK_FIELD_CONST(0x1, CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_SHIFT) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LE _MK_ENUM_CONST(0x0) +#define CDP_S_LUT_CFG_0_LUT_HYBRID_PRIORITY_LO _MK_ENUM_CONST(0x1) + + +// Register CDP_S_LUT_INFO_0 +#define CDP_S_LUT_INFO_0 _MK_ADDR_CONST(0xd014) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_FIELD _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_OFFSET_SHIFT) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LE_INDEX_SELECT_SHIFT) +#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_FIELD _MK_FIELD_CONST(0xff, CDP_S_LUT_INFO_0_LUT_LO_INDEX_SELECT_SHIFT) + + +// Register CDP_S_LUT_LE_START_LOW_0 +#define CDP_S_LUT_LE_START_LOW_0 _MK_ADDR_CONST(0xd018) +#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_START_LOW_0_LUT_LE_START_LOW_SHIFT) + + +// Register CDP_S_LUT_LE_START_HIGH_0 +#define CDP_S_LUT_LE_START_HIGH_0 _MK_ADDR_CONST(0xd01c) +#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_START_HIGH_0_LUT_LE_START_HIGH_SHIFT) + + +// Register CDP_S_LUT_LE_END_LOW_0 +#define CDP_S_LUT_LE_END_LOW_0 _MK_ADDR_CONST(0xd020) +#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LE_END_LOW_0_LUT_LE_END_LOW_SHIFT) + + +// Register CDP_S_LUT_LE_END_HIGH_0 +#define CDP_S_LUT_LE_END_HIGH_0 _MK_ADDR_CONST(0xd024) +#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LE_END_HIGH_0_LUT_LE_END_HIGH_SHIFT) + + +// Register CDP_S_LUT_LO_START_LOW_0 +#define CDP_S_LUT_LO_START_LOW_0 _MK_ADDR_CONST(0xd028) +#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_START_LOW_0_LUT_LO_START_LOW_SHIFT) + + +// Register CDP_S_LUT_LO_START_HIGH_0 +#define CDP_S_LUT_LO_START_HIGH_0 _MK_ADDR_CONST(0xd02c) +#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_START_HIGH_0_LUT_LO_START_HIGH_SHIFT) + + +// Register CDP_S_LUT_LO_END_LOW_0 +#define CDP_S_LUT_LO_END_LOW_0 _MK_ADDR_CONST(0xd030) +#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_S_LUT_LO_END_LOW_0_LUT_LO_END_LOW_SHIFT) + + +// Register CDP_S_LUT_LO_END_HIGH_0 +#define CDP_S_LUT_LO_END_HIGH_0 _MK_ADDR_CONST(0xd034) +#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_FIELD _MK_FIELD_CONST(0x3f, CDP_S_LUT_LO_END_HIGH_0_LUT_LO_END_HIGH_SHIFT) + + +// Register CDP_S_LUT_LE_SLOPE_SCALE_0 +#define CDP_S_LUT_LE_SLOPE_SCALE_0 _MK_ADDR_CONST(0xd038) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_UFLOW_SCALE_SHIFT) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LE_SLOPE_SCALE_0_LUT_LE_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register CDP_S_LUT_LE_SLOPE_SHIFT_0 +#define CDP_S_LUT_LE_SLOPE_SHIFT_0 _MK_ADDR_CONST(0xd03c) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_UFLOW_SHIFT_SHIFT) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LE_SLOPE_SHIFT_0_LUT_LE_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register CDP_S_LUT_LO_SLOPE_SCALE_0 +#define CDP_S_LUT_LO_SLOPE_SCALE_0 _MK_ADDR_CONST(0xd040) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_UFLOW_SCALE_SHIFT) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT _MK_SHIFT_CONST(16) +#define CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_S_LUT_LO_SLOPE_SCALE_0_LUT_LO_SLOPE_OFLOW_SCALE_SHIFT) + + +// Register CDP_S_LUT_LO_SLOPE_SHIFT_0 +#define CDP_S_LUT_LO_SLOPE_SHIFT_0 _MK_ADDR_CONST(0xd044) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_UFLOW_SHIFT_SHIFT) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT _MK_SHIFT_CONST(5) +#define CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_FIELD _MK_FIELD_CONST(0x1f, CDP_S_LUT_LO_SLOPE_SHIFT_0_LUT_LO_SLOPE_OFLOW_SHIFT_SHIFT) + + +// Register CDP_D_OP_ENABLE_0 +#define CDP_D_OP_ENABLE_0 _MK_ADDR_CONST(0xd048) +#define CDP_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_OP_ENABLE_0_OP_EN_SHIFT) +#define CDP_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_FUNC_BYPASS_0 +#define CDP_D_FUNC_BYPASS_0 _MK_ADDR_CONST(0xd04c) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_FIELD _MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_SHIFT) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_FUNC_BYPASS_0_SQSUM_BYPASS_ENABLE _MK_ENUM_CONST(0x1) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT _MK_SHIFT_CONST(1) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_FIELD _MK_FIELD_CONST(0x1, CDP_D_FUNC_BYPASS_0_MUL_BYPASS_SHIFT) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_FUNC_BYPASS_0_MUL_BYPASS_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_DST_BASE_ADDR_LOW_0 +#define CDP_D_DST_BASE_ADDR_LOW_0 _MK_ADDR_CONST(0xd050) +#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_LOW_0_DST_BASE_ADDR_LOW_SHIFT) + + +// Register CDP_D_DST_BASE_ADDR_HIGH_0 +#define CDP_D_DST_BASE_ADDR_HIGH_0 _MK_ADDR_CONST(0xd054) +#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_BASE_ADDR_HIGH_0_DST_BASE_ADDR_HIGH_SHIFT) + + +// Register CDP_D_DST_LINE_STRIDE_0 +#define CDP_D_DST_LINE_STRIDE_0 _MK_ADDR_CONST(0xd058) +#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_LINE_STRIDE_0_DST_LINE_STRIDE_SHIFT) + + +// Register CDP_D_DST_SURFACE_STRIDE_0 +#define CDP_D_DST_SURFACE_STRIDE_0 _MK_ADDR_CONST(0xd05c) +#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DST_SURFACE_STRIDE_0_DST_SURFACE_STRIDE_SHIFT) + + +// Register CDP_D_DST_DMA_CFG_0 +#define CDP_D_DST_DMA_CFG_0 _MK_ADDR_CONST(0xd060) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_SHIFT) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_CV _MK_ENUM_CONST(0x0) +#define CDP_D_DST_DMA_CFG_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register CDP_D_DST_COMPRESSION_EN_0 +#define CDP_D_DST_COMPRESSION_EN_0 _MK_ADDR_CONST(0xd064) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_SHIFT) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_DST_COMPRESSION_EN_0_DST_COMPRESSION_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_DATA_FORMAT_0 +#define CDP_D_DATA_FORMAT_0 _MK_ADDR_CONST(0xd068) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FIELD _MK_FIELD_CONST(0x3, CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_SHIFT) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT8 _MK_ENUM_CONST(0x0) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_INT16 _MK_ENUM_CONST(0x1) +#define CDP_D_DATA_FORMAT_0_INPUT_DATA_TYPE_FP16 _MK_ENUM_CONST(0x2) + + +// Register CDP_D_NAN_FLUSH_TO_ZERO_0 +#define CDP_D_NAN_FLUSH_TO_ZERO_0 _MK_ADDR_CONST(0xd06c) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_FIELD _MK_FIELD_CONST(0x1, CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_SHIFT) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_NAN_FLUSH_TO_ZERO_0_NAN_TO_ZERO_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_LRN_CFG_0 +#define CDP_D_LRN_CFG_0 _MK_ADDR_CONST(0xd070) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_FIELD _MK_FIELD_CONST(0x3, CDP_D_LRN_CFG_0_NORMALZ_LEN_SHIFT) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN3 _MK_ENUM_CONST(0x0) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN5 _MK_ENUM_CONST(0x1) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN7 _MK_ENUM_CONST(0x2) +#define CDP_D_LRN_CFG_0_NORMALZ_LEN_LEN9 _MK_ENUM_CONST(0x3) + + +// Register CDP_D_DATIN_OFFSET_0 +#define CDP_D_DATIN_OFFSET_0 _MK_ADDR_CONST(0xd074) +#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_FIELD _MK_FIELD_CONST(0xffff, CDP_D_DATIN_OFFSET_0_DATIN_OFFSET_SHIFT) + + +// Register CDP_D_DATIN_SCALE_0 +#define CDP_D_DATIN_SCALE_0 _MK_ADDR_CONST(0xd078) +#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATIN_SCALE_0_DATIN_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_D_DATIN_SCALE_0_DATIN_SCALE_SHIFT) + + +// Register CDP_D_DATIN_SHIFTER_0 +#define CDP_D_DATIN_SHIFTER_0 _MK_ADDR_CONST(0xd07c) +#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_FIELD _MK_FIELD_CONST(0x1f, CDP_D_DATIN_SHIFTER_0_DATIN_SHIFTER_SHIFT) + + +// Register CDP_D_DATOUT_OFFSET_0 +#define CDP_D_DATOUT_OFFSET_0 _MK_ADDR_CONST(0xd080) +#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_DATOUT_OFFSET_0_DATOUT_OFFSET_SHIFT) + + +// Register CDP_D_DATOUT_SCALE_0 +#define CDP_D_DATOUT_SCALE_0 _MK_ADDR_CONST(0xd084) +#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_FIELD _MK_FIELD_CONST(0xffff, CDP_D_DATOUT_SCALE_0_DATOUT_SCALE_SHIFT) + + +// Register CDP_D_DATOUT_SHIFTER_0 +#define CDP_D_DATOUT_SHIFTER_0 _MK_ADDR_CONST(0xd088) +#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_FIELD _MK_FIELD_CONST(0x3f, CDP_D_DATOUT_SHIFTER_0_DATOUT_SHIFTER_SHIFT) + + +// Register CDP_D_NAN_INPUT_NUM_0 +#define CDP_D_NAN_INPUT_NUM_0 _MK_ADDR_CONST(0xd08c) +#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_NAN_INPUT_NUM_0_NAN_INPUT_NUM_SHIFT) + + +// Register CDP_D_INF_INPUT_NUM_0 +#define CDP_D_INF_INPUT_NUM_0 _MK_ADDR_CONST(0xd090) +#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_INF_INPUT_NUM_0_INF_INPUT_NUM_SHIFT) + + +// Register CDP_D_NAN_OUTPUT_NUM_0 +#define CDP_D_NAN_OUTPUT_NUM_0 _MK_ADDR_CONST(0xd094) +#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_NAN_OUTPUT_NUM_0_NAN_OUTPUT_NUM_SHIFT) + + +// Register CDP_D_OUT_SATURATION_0 +#define CDP_D_OUT_SATURATION_0 _MK_ADDR_CONST(0xd098) +#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_OUT_SATURATION_0_OUT_SATURATION_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_OUT_SATURATION_0_OUT_SATURATION_SHIFT) + + +// Register CDP_D_PERF_ENABLE_0 +#define CDP_D_PERF_ENABLE_0 _MK_ADDR_CONST(0xd09c) +#define CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_ENABLE_0_DMA_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_DMA_EN_SHIFT) +#define CDP_D_PERF_ENABLE_0_DMA_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_PERF_ENABLE_0_DMA_EN_ENABLE _MK_ENUM_CONST(0x1) +#define CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT _MK_SHIFT_CONST(1) +#define CDP_D_PERF_ENABLE_0_LUT_EN_FIELD _MK_FIELD_CONST(0x1, CDP_D_PERF_ENABLE_0_LUT_EN_SHIFT) +#define CDP_D_PERF_ENABLE_0_LUT_EN_DISABLE _MK_ENUM_CONST(0x0) +#define CDP_D_PERF_ENABLE_0_LUT_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register CDP_D_PERF_WRITE_STALL_0 +#define CDP_D_PERF_WRITE_STALL_0 _MK_ADDR_CONST(0xd0a0) +#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_WRITE_STALL_0_PERF_WRITE_STALL_SHIFT) + + +// Register CDP_D_PERF_LUT_UFLOW_0 +#define CDP_D_PERF_LUT_UFLOW_0 _MK_ADDR_CONST(0xd0a4) +#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_UFLOW_0_PERF_LUT_UFLOW_SHIFT) + + +// Register CDP_D_PERF_LUT_OFLOW_0 +#define CDP_D_PERF_LUT_OFLOW_0 _MK_ADDR_CONST(0xd0a8) +#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_OFLOW_0_PERF_LUT_OFLOW_SHIFT) + + +// Register CDP_D_PERF_LUT_HYBRID_0 +#define CDP_D_PERF_LUT_HYBRID_0 _MK_ADDR_CONST(0xd0ac) +#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_HYBRID_0_PERF_LUT_HYBRID_SHIFT) + + +// Register CDP_D_PERF_LUT_LE_HIT_0 +#define CDP_D_PERF_LUT_LE_HIT_0 _MK_ADDR_CONST(0xd0b0) +#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LE_HIT_0_PERF_LUT_LE_HIT_SHIFT) + + +// Register CDP_D_PERF_LUT_LO_HIT_0 +#define CDP_D_PERF_LUT_LO_HIT_0 _MK_ADDR_CONST(0xd0b4) +#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_PERF_LUT_LO_HIT_0_PERF_LUT_LO_HIT_SHIFT) + + +// Register CDP_D_CYA_0 +#define CDP_D_CYA_0 _MK_ADDR_CONST(0xd0b8) +#define CDP_D_CYA_0_CYA_SHIFT _MK_SHIFT_CONST(0) +#define CDP_D_CYA_0_CYA_FIELD _MK_FIELD_CONST(0xffffffff, CDP_D_CYA_0_CYA_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register NVDLA_GEC_FEATURE_0 +#define NVDLA_GEC_FEATURE_0 _MK_ADDR_CONST(0xe000) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_FIELD _MK_FIELD_CONST(0x3f, NVDLA_GEC_FEATURE_0_NUM_ERR_SLICES_SHIFT) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_FEATURE_0_NUM_ERR_FIELD _MK_FIELD_CONST(0xffff, NVDLA_GEC_FEATURE_0_NUM_ERR_SHIFT) + + +// Register NVDLA_GEC_SWRESET_0 +#define NVDLA_GEC_SWRESET_0 _MK_ADDR_CONST(0xe004) +#define NVDLA_GEC_SWRESET_0_SWRST_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_SWRESET_0_SWRST_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_SWRESET_0_SWRST_SHIFT) + + +// Register NVDLA_GEC_MISSIONERR_TYPE_0 +#define NVDLA_GEC_MISSIONERR_TYPE_0 _MK_ADDR_CONST(0xe008) +#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_MISSIONERR_TYPE_0_CODE_FIELD _MK_FIELD_CONST(0x3f, NVDLA_GEC_MISSIONERR_TYPE_0_CODE_SHIFT) + + +// Register NVDLA_GEC_CURRENT_COUNTER_VALUE_0 +#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0 _MK_ADDR_CONST(0xe00c) +#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_FIELD _MK_FIELD_CONST(0x1ff, NVDLA_GEC_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT) + + +// Register NVDLA_GEC_MISSIONERR_INDEX_0 +#define NVDLA_GEC_MISSIONERR_INDEX_0 _MK_ADDR_CONST(0xe014) +#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_MISSIONERR_INDEX_0_IDX_FIELD _MK_FIELD_CONST(0x7f, NVDLA_GEC_MISSIONERR_INDEX_0_IDX_SHIFT) + + +// Register NVDLA_GEC_CORRECTABLE_THRESHOLD_0 +#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0 _MK_ADDR_CONST(0xe018) +#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_GEC_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT) + + +// Register NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0 +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0 _MK_ADDR_CONST(0xe01c) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD _MK_FIELD_CONST(0xff, NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK _MK_ENUM_CONST(0xe1) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0 _MK_ADDR_CONST(0xe030) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR13_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR14_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR15_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR16_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR17_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR18_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR19_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR20_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR21_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR22_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR23_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR24_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR25_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR26_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR27_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR28_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR29_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR30_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_ENABLE_0_ERR31_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0 _MK_ADDR_CONST(0xe034) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR13_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR14_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR15_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR16_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR17_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR18_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR19_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR20_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR21_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR22_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR23_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR24_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR25_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR26_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR27_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR28_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR29_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR30_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_FORCE_0_ERR31_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0 _MK_ADDR_CONST(0xe038) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_STATUS_0_ERR31_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0 +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0 _MK_ADDR_CONST(0xe03c) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR15_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR16_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR17_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR18_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR19_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR20_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR21_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR22_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR23_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR24_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR25_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR26_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR27_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR28_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR29_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR30_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_MISSIONERR_INJECT_0_ERR31_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0 _MK_ADDR_CONST(0xe040) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR13_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR14_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR15_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR16_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR17_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR18_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR19_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR20_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR21_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR22_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR23_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR24_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR25_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR26_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR27_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR28_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR29_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR30_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_ENABLE_0_ERR31_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0 _MK_ADDR_CONST(0xe044) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR13_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR14_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR15_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR16_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR17_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR18_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR19_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR20_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR21_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR22_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR23_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR24_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR25_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR26_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR27_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR28_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR29_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR30_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_FORCE_0_ERR31_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0 _MK_ADDR_CONST(0xe048) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_LATENTERR_STATUS_0_ERR31_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0 +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0 _MK_ADDR_CONST(0xe050) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR13_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR14_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR15_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR16_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR17_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR18_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR19_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR20_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR21_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR22_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR23_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR24_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR25_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR26_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR27_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR28_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR29_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR30_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_SHIFT) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE0_COUNTER_RELOAD_0_ERR31_RELOAD _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0 _MK_ADDR_CONST(0xe060) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR32_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR33_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR34_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR35_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR36_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR37_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR38_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR39_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR40_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR41_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR42_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR43_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR44_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR45_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR46_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR47_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR48_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR49_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR50_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR51_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR52_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR53_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR54_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR55_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR56_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR57_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR58_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR59_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR60_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR61_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR62_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ENABLE_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0 _MK_ADDR_CONST(0xe064) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR32_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR33_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR34_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR35_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR36_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR37_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR38_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR39_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR40_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR41_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR42_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR43_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR44_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR45_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR46_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR47_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR48_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR49_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR50_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR51_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR52_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR53_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR54_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR55_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR56_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR57_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR58_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR59_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR60_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR61_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR62_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_FORCE_0_ERR63_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0 _MK_ADDR_CONST(0xe068) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_STATUS_0_ERR63_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0 _MK_ADDR_CONST(0xe06c) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR32_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR33_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR34_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR35_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR36_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR37_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR38_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR39_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR40_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR41_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR42_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR43_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR44_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR45_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR46_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR47_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR48_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR49_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR50_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR51_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR52_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR53_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR54_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR55_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR56_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR57_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR58_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR59_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR60_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR61_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR62_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_INJECT_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0 _MK_ADDR_CONST(0xe070) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR32_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR33_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR34_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR35_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR36_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR37_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR38_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR39_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR40_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR41_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR42_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR43_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR44_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR45_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR46_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR47_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR48_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR49_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR50_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR51_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR52_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR53_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR54_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR55_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR56_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR57_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR58_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR59_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR60_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR61_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR62_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_ENABLE_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0 _MK_ADDR_CONST(0xe074) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR32_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR33_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR34_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR35_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR36_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR37_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR38_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR39_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR40_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR41_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR42_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR43_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR44_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR45_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR46_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR47_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR48_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR49_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR50_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR51_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR52_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR53_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR54_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR55_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR56_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR57_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR58_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR59_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR60_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR61_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR62_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_FORCE_0_ERR63_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0 _MK_ADDR_CONST(0xe078) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_LATENTERR_STATUS_0_ERR63_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0 +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0 _MK_ADDR_CONST(0xe080) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR32_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR33_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR34_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR35_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT _MK_SHIFT_CONST(4) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR36_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT _MK_SHIFT_CONST(5) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR37_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT _MK_SHIFT_CONST(6) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR38_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT _MK_SHIFT_CONST(7) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR39_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR40_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT _MK_SHIFT_CONST(9) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR41_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT _MK_SHIFT_CONST(10) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR42_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT _MK_SHIFT_CONST(11) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR43_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT _MK_SHIFT_CONST(12) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR44_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT _MK_SHIFT_CONST(13) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR45_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT _MK_SHIFT_CONST(14) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR46_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT _MK_SHIFT_CONST(15) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR47_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR48_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT _MK_SHIFT_CONST(17) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR49_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT _MK_SHIFT_CONST(18) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR50_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT _MK_SHIFT_CONST(19) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR51_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT _MK_SHIFT_CONST(20) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR52_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT _MK_SHIFT_CONST(21) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR53_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT _MK_SHIFT_CONST(22) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR54_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT _MK_SHIFT_CONST(23) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR55_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR56_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT _MK_SHIFT_CONST(25) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR57_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT _MK_SHIFT_CONST(26) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR58_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT _MK_SHIFT_CONST(27) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR59_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT _MK_SHIFT_CONST(28) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR60_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT _MK_SHIFT_CONST(29) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR61_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT _MK_SHIFT_CONST(30) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR62_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_COUNTER_RELOAD_0_ERR63_RELOAD _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0 +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0 _MK_ADDR_CONST(0xe084) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT _MK_SHIFT_CONST(31) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_SHIFT) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE1_MISSIONERR_ECC_CORRECTION_DIS_0_ERR63_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0 _MK_ADDR_CONST(0xe090) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR64_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR65_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR66_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_ENABLE_0_ERR67_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0 _MK_ADDR_CONST(0xe094) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR64_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR65_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR66_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_FORCE_0_ERR67_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0 _MK_ADDR_CONST(0xe098) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_STATUS_0_ERR67_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0 +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0 _MK_ADDR_CONST(0xe09c) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR64_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_MISSIONERR_INJECT_0_ERR65_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0 +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0 _MK_ADDR_CONST(0xe0a0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR64_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR65_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR66_ENABLE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_DISABLE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_ENABLE_0_ERR67_ENABLE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0 +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0 _MK_ADDR_CONST(0xe0a4) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR64_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR65_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR66_FORCE _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_NOFORCE _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_FORCE_0_ERR67_FORCE _MK_ENUM_CONST(0x1) + + +// Register NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0 +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0 _MK_ADDR_CONST(0xe0a8) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_LATENTERR_STATUS_0_ERR67_SHIFT) + + +// Register NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0 +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0 _MK_ADDR_CONST(0xe0b0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR64_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT _MK_SHIFT_CONST(1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR65_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT _MK_SHIFT_CONST(2) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR66_RELOAD _MK_ENUM_CONST(0x1) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT _MK_SHIFT_CONST(3) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_FIELD _MK_FIELD_CONST(0x1, NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_SHIFT) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_NORELOAD _MK_ENUM_CONST(0x0) +#define NVDLA_GEC_ERRSLICE2_COUNTER_RELOAD_0_ERR67_RELOAD _MK_ENUM_CONST(0x1) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register NVDLA_CVIF_CFG_RD_WEIGHT_0_0 +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0 _MK_ADDR_CONST(0xf000) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_BDMA_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_SDP_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_PDP_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_0_0_RD_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_CVIF_CFG_RD_WEIGHT_1_0 +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0 _MK_ADDR_CONST(0xf004) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_B_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_N_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_SDP_E_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_1_0_RD_WEIGHT_CDMA_DAT_SHIFT) + + +// Register NVDLA_CVIF_CFG_RD_WEIGHT_2_0 +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0 _MK_ADDR_CONST(0xf008) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_CDMA_WT_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RBK_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_1_SHIFT) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_RD_WEIGHT_2_0_RD_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_CVIF_CFG_WR_WEIGHT_0_0 +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0 _MK_ADDR_CONST(0xf00c) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_BDMA_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_SDP_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_PDP_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_0_0_WR_WEIGHT_CDP_SHIFT) + + +// Register NVDLA_CVIF_CFG_WR_WEIGHT_1_0 +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0 _MK_ADDR_CONST(0xf010) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RBK_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_2_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT _MK_SHIFT_CONST(16) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_1_SHIFT) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT _MK_SHIFT_CONST(24) +#define NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_WR_WEIGHT_1_0_WR_WEIGHT_RSV_0_SHIFT) + + +// Register NVDLA_CVIF_CFG_OUTSTANDING_CNT_0 +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0 _MK_ADDR_CONST(0xf014) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT _MK_SHIFT_CONST(0) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_RD_OS_CNT_SHIFT) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_FIELD _MK_FIELD_CONST(0xff, NVDLA_CVIF_CFG_OUTSTANDING_CNT_0_WR_OS_CNT_SHIFT) + + +// Register NVDLA_CVIF_STATUS_0 +#define NVDLA_CVIF_STATUS_0 _MK_ADDR_CONST(0xf018) +#define NVDLA_CVIF_STATUS_0_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define NVDLA_CVIF_STATUS_0_IDLE_FIELD _MK_FIELD_CONST(0x1, NVDLA_CVIF_STATUS_0_IDLE_SHIFT) +#define NVDLA_CVIF_STATUS_0_IDLE_NO _MK_ENUM_CONST(0x0) +#define NVDLA_CVIF_STATUS_0_IDLE_YES _MK_ENUM_CONST(0x1) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register BDMA_CFG_SRC_ADDR_LOW_0 +#define BDMA_CFG_SRC_ADDR_LOW_0 _MK_ADDR_CONST(0x10000) +#define BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_SRC_ADDR_LOW_0_V32_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_ADDR_LOW_0_V32_SHIFT) + + +// Register BDMA_CFG_SRC_ADDR_HIGH_0 +#define BDMA_CFG_SRC_ADDR_HIGH_0 _MK_ADDR_CONST(0x10004) +#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_SRC_ADDR_HIGH_0_V8_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_CFG_SRC_ADDR_HIGH_0_V8_SHIFT) + + +// Register BDMA_CFG_DST_ADDR_LOW_0 +#define BDMA_CFG_DST_ADDR_LOW_0 _MK_ADDR_CONST(0x10008) +#define BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_DST_ADDR_LOW_0_V32_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_ADDR_LOW_0_V32_SHIFT) + + +// Register BDMA_CFG_DST_ADDR_HIGH_0 +#define BDMA_CFG_DST_ADDR_HIGH_0 _MK_ADDR_CONST(0x1000c) +#define BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_DST_ADDR_HIGH_0_V8_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_CFG_DST_ADDR_HIGH_0_V8_SHIFT) + + +// Register BDMA_CFG_LINE_0 +#define BDMA_CFG_LINE_0 _MK_ADDR_CONST(0x10010) +#define BDMA_CFG_LINE_0_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LINE_0_SIZE_FIELD _MK_FIELD_CONST(0x1fff, BDMA_CFG_LINE_0_SIZE_SHIFT) + + +// Register BDMA_CFG_CMD_0 +#define BDMA_CFG_CMD_0 _MK_ADDR_CONST(0x10014) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_SRC_RAM_TYPE_SHIFT) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_CVSRAM _MK_ENUM_CONST(0x0) +#define BDMA_CFG_CMD_0_SRC_RAM_TYPE_MC _MK_ENUM_CONST(0x1) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT _MK_SHIFT_CONST(1) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_CMD_0_DST_RAM_TYPE_SHIFT) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_CVSRAM _MK_ENUM_CONST(0x0) +#define BDMA_CFG_CMD_0_DST_RAM_TYPE_MC _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_LINE_REPEAT_0 +#define BDMA_CFG_LINE_REPEAT_0 _MK_ADDR_CONST(0x10018) +#define BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LINE_REPEAT_0_NUMBER_FIELD _MK_FIELD_CONST(0xffffff, BDMA_CFG_LINE_REPEAT_0_NUMBER_SHIFT) + + +// Register BDMA_CFG_SRC_LINE_0 +#define BDMA_CFG_SRC_LINE_0 _MK_ADDR_CONST(0x1001c) +#define BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_SRC_LINE_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_LINE_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_DST_LINE_0 +#define BDMA_CFG_DST_LINE_0 _MK_ADDR_CONST(0x10020) +#define BDMA_CFG_DST_LINE_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_DST_LINE_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_LINE_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_SURF_REPEAT_0 +#define BDMA_CFG_SURF_REPEAT_0 _MK_ADDR_CONST(0x10024) +#define BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_SURF_REPEAT_0_NUMBER_FIELD _MK_FIELD_CONST(0xffffff, BDMA_CFG_SURF_REPEAT_0_NUMBER_SHIFT) + + +// Register BDMA_CFG_SRC_SURF_0 +#define BDMA_CFG_SRC_SURF_0 _MK_ADDR_CONST(0x10028) +#define BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_SRC_SURF_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_SRC_SURF_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_DST_SURF_0 +#define BDMA_CFG_DST_SURF_0 _MK_ADDR_CONST(0x1002c) +#define BDMA_CFG_DST_SURF_0_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define BDMA_CFG_DST_SURF_0_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, BDMA_CFG_DST_SURF_0_STRIDE_SHIFT) + + +// Register BDMA_CFG_OP_0 +#define BDMA_CFG_OP_0 _MK_ADDR_CONST(0x10030) +#define BDMA_CFG_OP_0_EN_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_OP_0_EN_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_OP_0_EN_SHIFT) +#define BDMA_CFG_OP_0_EN_DISABLE _MK_ENUM_CONST(0x0) +#define BDMA_CFG_OP_0_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_LAUNCH0_0 +#define BDMA_CFG_LAUNCH0_0 _MK_ADDR_CONST(0x10034) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_SHIFT) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_NO _MK_ENUM_CONST(0x0) +#define BDMA_CFG_LAUNCH0_0_GRP0_LAUNCH_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_LAUNCH1_0 +#define BDMA_CFG_LAUNCH1_0 _MK_ADDR_CONST(0x10038) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_SHIFT) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_NO _MK_ENUM_CONST(0x0) +#define BDMA_CFG_LAUNCH1_0_GRP1_LAUNCH_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_CFG_STATUS_0 +#define BDMA_CFG_STATUS_0 _MK_ADDR_CONST(0x1003c) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_FIELD _MK_FIELD_CONST(0x1, BDMA_CFG_STATUS_0_STALL_COUNT_EN_SHIFT) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_NO _MK_ENUM_CONST(0x0) +#define BDMA_CFG_STATUS_0_STALL_COUNT_EN_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_STATUS_0 +#define BDMA_STATUS_0 _MK_ADDR_CONST(0x10040) +#define BDMA_STATUS_0_FREE_SLOT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_0_FREE_SLOT_FIELD _MK_FIELD_CONST(0xff, BDMA_STATUS_0_FREE_SLOT_SHIFT) +#define BDMA_STATUS_0_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define BDMA_STATUS_0_IDLE_FIELD _MK_FIELD_CONST(0x1, BDMA_STATUS_0_IDLE_SHIFT) +#define BDMA_STATUS_0_IDLE_NO _MK_ENUM_CONST(0x0) +#define BDMA_STATUS_0_IDLE_YES _MK_ENUM_CONST(0x1) +#define BDMA_STATUS_0_GRP0_BUSY_SHIFT _MK_SHIFT_CONST(9) +#define BDMA_STATUS_0_GRP0_BUSY_FIELD _MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP0_BUSY_SHIFT) +#define BDMA_STATUS_0_GRP0_BUSY_NO _MK_ENUM_CONST(0x0) +#define BDMA_STATUS_0_GRP0_BUSY_YES _MK_ENUM_CONST(0x1) +#define BDMA_STATUS_0_GRP1_BUSY_SHIFT _MK_SHIFT_CONST(10) +#define BDMA_STATUS_0_GRP1_BUSY_FIELD _MK_FIELD_CONST(0x1, BDMA_STATUS_0_GRP1_BUSY_SHIFT) +#define BDMA_STATUS_0_GRP1_BUSY_NO _MK_ENUM_CONST(0x0) +#define BDMA_STATUS_0_GRP1_BUSY_YES _MK_ENUM_CONST(0x1) + + +// Register BDMA_STATUS_GRP0_READ_STALL_0 +#define BDMA_STATUS_GRP0_READ_STALL_0 _MK_ADDR_CONST(0x10044) +#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP0_READ_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_READ_STALL_0_COUNT_SHIFT) + + +// Register BDMA_STATUS_GRP0_WRITE_STALL_0 +#define BDMA_STATUS_GRP0_WRITE_STALL_0 _MK_ADDR_CONST(0x10048) +#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP0_WRITE_STALL_0_COUNT_SHIFT) + + +// Register BDMA_STATUS_GRP1_READ_STALL_0 +#define BDMA_STATUS_GRP1_READ_STALL_0 _MK_ADDR_CONST(0x1004c) +#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP1_READ_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_READ_STALL_0_COUNT_SHIFT) + + +// Register BDMA_STATUS_GRP1_WRITE_STALL_0 +#define BDMA_STATUS_GRP1_WRITE_STALL_0 _MK_ADDR_CONST(0x10050) +#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_FIELD _MK_FIELD_CONST(0xffffffff, BDMA_STATUS_GRP1_WRITE_STALL_0_COUNT_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + +// Register RBK_S_STATUS_0 +#define RBK_S_STATUS_0 _MK_ADDR_CONST(0x11000) +#define RBK_S_STATUS_0_STATUS_0_SHIFT _MK_SHIFT_CONST(0) +#define RBK_S_STATUS_0_STATUS_0_FIELD _MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_0_SHIFT) +#define RBK_S_STATUS_0_STATUS_0_IDLE _MK_ENUM_CONST(0x0) +#define RBK_S_STATUS_0_STATUS_0_RUNNING _MK_ENUM_CONST(0x1) +#define RBK_S_STATUS_0_STATUS_0_PENDING _MK_ENUM_CONST(0x2) +#define RBK_S_STATUS_0_STATUS_1_SHIFT _MK_SHIFT_CONST(16) +#define RBK_S_STATUS_0_STATUS_1_FIELD _MK_FIELD_CONST(0x3, RBK_S_STATUS_0_STATUS_1_SHIFT) +#define RBK_S_STATUS_0_STATUS_1_IDLE _MK_ENUM_CONST(0x0) +#define RBK_S_STATUS_0_STATUS_1_RUNNING _MK_ENUM_CONST(0x1) +#define RBK_S_STATUS_0_STATUS_1_PENDING _MK_ENUM_CONST(0x2) + + +// Register RBK_S_POINTER_0 +#define RBK_S_POINTER_0 _MK_ADDR_CONST(0x11004) +#define RBK_S_POINTER_0_PRODUCER_SHIFT _MK_SHIFT_CONST(0) +#define RBK_S_POINTER_0_PRODUCER_FIELD _MK_FIELD_CONST(0x1, RBK_S_POINTER_0_PRODUCER_SHIFT) +#define RBK_S_POINTER_0_PRODUCER_GROUP_0 _MK_ENUM_CONST(0x0) +#define RBK_S_POINTER_0_PRODUCER_GROUP_1 _MK_ENUM_CONST(0x1) +#define RBK_S_POINTER_0_CONSUMER_SHIFT _MK_SHIFT_CONST(16) +#define RBK_S_POINTER_0_CONSUMER_FIELD _MK_FIELD_CONST(0x1, RBK_S_POINTER_0_CONSUMER_SHIFT) +#define RBK_S_POINTER_0_CONSUMER_GROUP_0 _MK_ENUM_CONST(0x0) +#define RBK_S_POINTER_0_CONSUMER_GROUP_1 _MK_ENUM_CONST(0x1) + + +// Register RBK_D_OP_ENABLE_0 +#define RBK_D_OP_ENABLE_0 _MK_ADDR_CONST(0x11008) +#define RBK_D_OP_ENABLE_0_OP_EN_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_OP_ENABLE_0_OP_EN_FIELD _MK_FIELD_CONST(0x1, RBK_D_OP_ENABLE_0_OP_EN_SHIFT) +#define RBK_D_OP_ENABLE_0_OP_EN_DISABLE _MK_ENUM_CONST(0x0) +#define RBK_D_OP_ENABLE_0_OP_EN_ENABLE _MK_ENUM_CONST(0x1) + + +// Register RBK_D_MISC_CFG_0 +#define RBK_D_MISC_CFG_0 _MK_ADDR_CONST(0x1100c) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_FIELD _MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_RUBIK_MODE_SHIFT) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_CONTRACT _MK_ENUM_CONST(0x0) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_SPLIT _MK_ENUM_CONST(0x1) +#define RBK_D_MISC_CFG_0_RUBIK_MODE_MERGE _MK_ENUM_CONST(0x2) +#define RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT _MK_SHIFT_CONST(8) +#define RBK_D_MISC_CFG_0_IN_PRECISION_FIELD _MK_FIELD_CONST(0x3, RBK_D_MISC_CFG_0_IN_PRECISION_SHIFT) +#define RBK_D_MISC_CFG_0_IN_PRECISION_INT8 _MK_ENUM_CONST(0x0) +#define RBK_D_MISC_CFG_0_IN_PRECISION_INT16 _MK_ENUM_CONST(0x1) +#define RBK_D_MISC_CFG_0_IN_PRECISION_FP16 _MK_ENUM_CONST(0x2) + + +// Register RBK_D_DAIN_RAM_TYPE_0 +#define RBK_D_DAIN_RAM_TYPE_0 _MK_ADDR_CONST(0x11010) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_SHIFT) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define RBK_D_DAIN_RAM_TYPE_0_DATAIN_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register RBK_D_DATAIN_SIZE_0_0 +#define RBK_D_DATAIN_SIZE_0_0 _MK_ADDR_CONST(0x11014) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_WIDTH_SHIFT) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT _MK_SHIFT_CONST(16) +#define RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_0_0_DATAIN_HEIGHT_SHIFT) + + +// Register RBK_D_DATAIN_SIZE_1_0 +#define RBK_D_DATAIN_SIZE_1_0 _MK_ADDR_CONST(0x11018) +#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAIN_SIZE_1_0_DATAIN_CHANNEL_SHIFT) + + +// Register RBK_D_DAIN_ADDR_HIGH_0 +#define RBK_D_DAIN_ADDR_HIGH_0 _MK_ADDR_CONST(0x1101c) +#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_DAIN_ADDR_HIGH_0_DAIN_ADDR_HIGH_SHIFT) + + +// Register RBK_D_DAIN_ADDR_LOW_0 +#define RBK_D_DAIN_ADDR_LOW_0 _MK_ADDR_CONST(0x11020) +#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_ADDR_LOW_0_DAIN_ADDR_LOW_SHIFT) + + +// Register RBK_D_DAIN_LINE_STRIDE_0 +#define RBK_D_DAIN_LINE_STRIDE_0 _MK_ADDR_CONST(0x11024) +#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_LINE_STRIDE_0_DAIN_LINE_STRIDE_SHIFT) + + +// Register RBK_D_DAIN_SURF_STRIDE_0 +#define RBK_D_DAIN_SURF_STRIDE_0 _MK_ADDR_CONST(0x11028) +#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_SURF_STRIDE_0_DAIN_SURF_STRIDE_SHIFT) + + +// Register RBK_D_DAIN_PLANAR_STRIDE_0 +#define RBK_D_DAIN_PLANAR_STRIDE_0 _MK_ADDR_CONST(0x1102c) +#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAIN_PLANAR_STRIDE_0_DAIN_PLANAR_STRIDE_SHIFT) + + +// Register RBK_D_DAOUT_RAM_TYPE_0 +#define RBK_D_DAOUT_RAM_TYPE_0 _MK_ADDR_CONST(0x11030) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_FIELD _MK_FIELD_CONST(0x1, RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_SHIFT) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_CVIF _MK_ENUM_CONST(0x0) +#define RBK_D_DAOUT_RAM_TYPE_0_DATAOUT_RAM_TYPE_MCIF _MK_ENUM_CONST(0x1) + + +// Register RBK_D_DATAOUT_SIZE_1_0 +#define RBK_D_DATAOUT_SIZE_1_0 _MK_ADDR_CONST(0x11034) +#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_FIELD _MK_FIELD_CONST(0x1fff, RBK_D_DATAOUT_SIZE_1_0_DATAOUT_CHANNEL_SHIFT) + + +// Register RBK_D_DAOUT_ADDR_HIGH_0 +#define RBK_D_DAOUT_ADDR_HIGH_0 _MK_ADDR_CONST(0x11038) +#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_DAOUT_ADDR_HIGH_0_DAOUT_ADDR_HIGH_SHIFT) + + +// Register RBK_D_DAOUT_ADDR_LOW_0 +#define RBK_D_DAOUT_ADDR_LOW_0 _MK_ADDR_CONST(0x1103c) +#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_ADDR_LOW_0_DAOUT_ADDR_LOW_SHIFT) + + +// Register RBK_D_DAOUT_LINE_STRIDE_0 +#define RBK_D_DAOUT_LINE_STRIDE_0 _MK_ADDR_CONST(0x11040) +#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_LINE_STRIDE_0_DAOUT_LINE_STRIDE_SHIFT) + + +// Register RBK_D_CONTRACT_STRIDE_0_0 +#define RBK_D_CONTRACT_STRIDE_0_0 _MK_ADDR_CONST(0x11044) +#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_0_0_CONTRACT_STRIDE_0_SHIFT) + + +// Register RBK_D_CONTRACT_STRIDE_1_0 +#define RBK_D_CONTRACT_STRIDE_1_0 _MK_ADDR_CONST(0x11048) +#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_CONTRACT_STRIDE_1_0_CONTRACT_STRIDE_1_SHIFT) + + +// Register RBK_D_DAOUT_SURF_STRIDE_0 +#define RBK_D_DAOUT_SURF_STRIDE_0 _MK_ADDR_CONST(0x1104c) +#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_SURF_STRIDE_0_DAOUT_SURF_STRIDE_SHIFT) + + +// Register RBK_D_DAOUT_PLANAR_STRIDE_0 +#define RBK_D_DAOUT_PLANAR_STRIDE_0 _MK_ADDR_CONST(0x11050) +#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT _MK_SHIFT_CONST(5) +#define RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_FIELD _MK_FIELD_CONST(0x7ffffff, RBK_D_DAOUT_PLANAR_STRIDE_0_DAOUT_PLANAR_STRIDE_SHIFT) + + +// Register RBK_D_DECONV_STRIDE_0 +#define RBK_D_DECONV_STRIDE_0 _MK_ADDR_CONST(0x11054) +#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_FIELD _MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_X_STRIDE_SHIFT) +#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT _MK_SHIFT_CONST(16) +#define RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_FIELD _MK_FIELD_CONST(0x1f, RBK_D_DECONV_STRIDE_0_DECONV_Y_STRIDE_SHIFT) + + +// Register RBK_D_PERF_ENABLE_0 +#define RBK_D_PERF_ENABLE_0 _MK_ADDR_CONST(0x11058) +#define RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_PERF_ENABLE_0_PERF_EN_FIELD _MK_FIELD_CONST(0x1, RBK_D_PERF_ENABLE_0_PERF_EN_SHIFT) + + +// Register RBK_D_PERF_READ_STALL_0 +#define RBK_D_PERF_READ_STALL_0 _MK_ADDR_CONST(0x1105c) +#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_PERF_READ_STALL_0_RD_STALL_CNT_SHIFT) + + +// Register RBK_D_PERF_WRITE_STALL_0 +#define RBK_D_PERF_WRITE_STALL_0 _MK_ADDR_CONST(0x11060) +#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT _MK_SHIFT_CONST(0) +#define RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_FIELD _MK_FIELD_CONST(0xffffffff, RBK_D_PERF_WRITE_STALL_0_WR_STALL_CNT_SHIFT) + + + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_NVDLA_CFGROM 0x0 +#define BASE_ADDRESS_NVDLA_GLB 0x1000 +#define BASE_ADDRESS_NVDLA_MCIF 0x2000 +#define BASE_ADDRESS_NVDLA_CDMA 0x3000 +#define BASE_ADDRESS_NVDLA_CSC 0x4000 +#define BASE_ADDRESS_NVDLA_CMAC_A 0x5000 +#define BASE_ADDRESS_NVDLA_CMAC_B 0x6000 +#define BASE_ADDRESS_NVDLA_CACC 0x7000 +#define BASE_ADDRESS_NVDLA_SDP_RDMA 0x8000 +#define BASE_ADDRESS_NVDLA_SDP 0x9000 +#define BASE_ADDRESS_NVDLA_PDP_RDMA 0xa000 +#define BASE_ADDRESS_NVDLA_PDP 0xb000 +#define BASE_ADDRESS_NVDLA_CDP_RDMA 0xc000 +#define BASE_ADDRESS_NVDLA_CDP 0xd000 +#define BASE_ADDRESS_NVDLA_GEC 0xe000 +#define BASE_ADDRESS_NVDLA_CVIF 0xf000 +#define BASE_ADDRESS_NVDLA_BDMA 0x10000 +#define BASE_ADDRESS_NVDLA_RBK 0x11000 + +#endif From 33e83e06448517ed80b72ace90b993d871f0b86c Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 13:08:57 -0700 Subject: [PATCH 121/139] [dromajo] separate documentation | move header file gen to tcip --- docs/Advanced-Concepts/Debugging-BOOM.rst | 30 +++++++++++++++++++ docs/Advanced-Concepts/Debugging-RTL.rst | 23 -------------- docs/Advanced-Concepts/index.rst | 1 + docs/Chipyard-Basics/Chipyard-Components.rst | 2 +- generators/boom | 2 +- .../chipyard/src/main/scala/Subsystem.scala | 27 +++-------------- generators/testchipip | 2 +- 7 files changed, 38 insertions(+), 49 deletions(-) create mode 100644 docs/Advanced-Concepts/Debugging-BOOM.rst diff --git a/docs/Advanced-Concepts/Debugging-BOOM.rst b/docs/Advanced-Concepts/Debugging-BOOM.rst new file mode 100644 index 00000000..1e61804c --- /dev/null +++ b/docs/Advanced-Concepts/Debugging-BOOM.rst @@ -0,0 +1,30 @@ +Debugging BOOM +====================== + +In addition to the default debugging techniques specified in :ref:`Debugging RTL`, +single-core BOOM designs can utilize the Dromajo co-simulator (see :ref:`Dromajo`) +to verify functionality. + +.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. + +.. warning:: Dromajo currently only works in VCS simulation and FireSim. + +Setting up Dromajo Co-simulation +-------------------------------------- + +Dromajo co-simulation is setup to work when two config fragments are added to a BOOM config. +First, a ``chipyard.config.WithTraceIO`` config fragment must be added so that BOOM's traceport is enabled. +Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config fragment must be added to +connect the Dromajo co-simulator to the traceport. +Once both config fragments are added Dromajo should be enabled. + +To build/run Dromajo with a BOOM design, run your configuration the following make commands: + +.. code-block:: shell + + # build the default Dromajo BOOM config without waveform dumps + # replace "DromajoBoomConfig" with your particular config + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 + + # run a simulation with Dromajo + make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary diff --git a/docs/Advanced-Concepts/Debugging-RTL.rst b/docs/Advanced-Concepts/Debugging-RTL.rst index 86e5ced3..6831cc4a 100644 --- a/docs/Advanced-Concepts/Debugging-RTL.rst +++ b/docs/Advanced-Concepts/Debugging-RTL.rst @@ -86,29 +86,6 @@ identical program behavior. The torture utility can also be configured to run continuously for stress-testing. The torture utility exists within the ``utilities`` directory. -Dromajo Co-simulation for BOOM designs --------------------------------------- -Dromajo co-simulation is setup to work when two config. fragments are added to a BOOM config. -First, a ``chipyard.config.WithTraceIO`` config. fragment must be added so that BOOM's traceport is enabled. -Second, a ``chipyard.iobinders.WithSimDromajoBridge`` config. fragment must be added to -connect the Dromajo co-simulator to the traceport. -Once both config. fragments are added Dromajo should be enabled. - -To build/run Dromajo with a BOOM design, run your configuration the following make commands: - -.. code-block:: shell - - # build the default Dromajo BOOM config. without waveform dumps - # replace "DromajoBoomConfig" with your particular config - make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 - - # run a simulation with Dromajo - make CONFIG=DromajoBoomConfig ENABLE_DROMAJO=1 BINARY= run-binary - -.. warning:: Dromajo currently only works in single-core BOOM systems without accelerators. - -.. warning:: Dromajo currently only works in VCS simulation and FireSim. - Firesim Debugging --------------------------- Chisel printfs, asserts, Dromajo co-simulation, and waveform generation are also available in FireSim diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index c13e569b..12b12716 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -11,6 +11,7 @@ They expect you to know about Chisel, Parameters, configs, etc. Top-Testharness Chip-Communication Debugging-RTL + Debugging-BOOM Resources CDEs diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index 7a89e93a..c24f81ed 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -80,7 +80,7 @@ Tools A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC). **Dromajo** - A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technology. + A RV64GC emulator primarily used for co-simulation and was originally developed by Esperanto Technologies. See :ref:`Dromajo` for more information. Toolchains diff --git a/generators/boom b/generators/boom index 8c4ac6fd..2668248c 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 8c4ac6fd40b455387cec369080b9b47d6fd1466e +Subproject commit 2668248c5c673037f5cb7a8bc2a90c5fb0c019d9 diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala index 4dfa7d73..99c31472 100644 --- a/generators/chipyard/src/main/scala/Subsystem.scala +++ b/generators/chipyard/src/main/scala/Subsystem.scala @@ -24,6 +24,8 @@ import freechips.rocketchip.amba.axi4._ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams} +import testchipip.{DromajoHelper} + trait HasChipyardTiles extends HasTiles with CanHavePeripheryPLIC with CanHavePeripheryCLINT @@ -106,27 +108,6 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) // Generate C header with relevant information for Dromajo - // THIS IS INCLUDED IN THE `dromajo_params.h` header file - var dromajoParams: String = "" - dromajoParams += "#ifndef DROMAJO_PARAMS_H" - dromajoParams += "\n#define DROMAJO_PARAMS_H" - dromajoParams += "\n\n" + "#define DROMAJO_RESET_VECTOR " + "\"" + "0x" + f"${p(BootROMParams).hang}%X" + "\"" - dromajoParams += "\n" + "#define DROMAJO_MMIO_START " + "\"" + "0x" + f"${p(BootROMParams).address + p(BootROMParams).size}%X" + "\"" - p(ExtMem) map { eP => - dromajoParams += "\n" + "#define DROMAJO_MMIO_END " + "\"" + "0x" + f"${eP.master.base}%X" + "\"" - // dromajo memory is in MiB chunks - dromajoParams += "\n" + "#define DROMAJO_MEM_SIZE " + "\"" + "0x" + f"${eP.master.size >> 20}%X" + "\"" - } - p(PLICKey) map { pP => - dromajoParams += "\n" + "#define DROMAJO_PLIC_BASE " + "\"" + "0x" + f"${pP.baseAddress}%X" + "\"" - dromajoParams += "\n" + "#define DROMAJO_PLIC_SIZE " + "\"" + "0x" + f"${PLICConsts.size(pP.maxHarts)}%X" + "\"" - } - p(CLINTKey) map { cP => - dromajoParams += "\n" + "#define DROMAJO_CLINT_BASE " + "\"" + "0x" + f"${cP.baseAddress}%X" + "\"" - dromajoParams += "\n" + "#define DROMAJO_CLINT_SIZE " + "\"" + "0x" + f"${CLINTConsts.size}%X" + "\"" - } - dromajoParams += "\n\n#endif" - - ElaborationArtefacts.add("""dromajo_params.h""", dromajoParams) - + // This is included in the `dromajo_params.h` header file + DromajoHelper.addArtefacts } diff --git a/generators/testchipip b/generators/testchipip index e43e818f..8ce64295 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit e43e818f443764cb1a1bdaa243b5adc795083217 +Subproject commit 8ce64295f2c1f6b927145527538988809a03a057 From ca3c557fe29c45dc9be9589bae8bd84f4c853378 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 13:43:14 -0700 Subject: [PATCH 122/139] [dromajo] change dromajo url | small cleanup --- .gitmodules | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index cae791dd..aab9a8f7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -127,4 +127,4 @@ url = https://github.com/ucb-bar/nvdla-workload.git [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src - url = https://github.com/abejgonzalez/dromajo.git + url = https://github.com/riscv-boom/dromajo.git diff --git a/generators/testchipip b/generators/testchipip index 8ce64295..342d1d70 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 8ce64295f2c1f6b927145527538988809a03a057 +Subproject commit 342d1d70985797381985ea0a47e668961ceb0c3d From 9dda27f20cc1afbcb4b0d3f088e95963e923bced Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 14:47:15 -0700 Subject: [PATCH 123/139] [traceio] wdata: use option instead of 1.B wire --- generators/boom | 2 +- generators/testchipip | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/boom b/generators/boom index 2668248c..f0caca8d 160000 --- a/generators/boom +++ b/generators/boom @@ -1 +1 @@ -Subproject commit 2668248c5c673037f5cb7a8bc2a90c5fb0c019d9 +Subproject commit f0caca8d6bc98f3ccc7d8b9391b7f7c8efb2f879 diff --git a/generators/testchipip b/generators/testchipip index 342d1d70..72cafd8c 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 342d1d70985797381985ea0a47e668961ceb0c3d +Subproject commit 72cafd8c867f3a1a6decac62e6e77b9b6de02be7 From d88627e913a97ee10c3cded3f33bdef9f6d54c3a Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 14:51:27 -0700 Subject: [PATCH 124/139] [traceio] bump firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4e94c1a0..724a66b0 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a +Subproject commit 724a66b0f4430b02d7d5e83b419916250978ee01 From 73f8ec5017c2f19e76a8c03aea364a77de826274 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 16 May 2020 22:46:39 +0000 Subject: [PATCH 125/139] [stage] Make config concatenation actually work --- .../src/main/scala/stage/ChipyardAnnotations.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala index dfee1596..d75c11a1 100644 --- a/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala +++ b/generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala @@ -11,7 +11,12 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio override val options = Seq( new ShellOption[String]( longOption = "legacy-configs", - toAnnotationSeq = a => Seq(new ConfigsAnnotation(a.split("_"))), + toAnnotationSeq = a => { + val split = a.split('.') + val packageName = split.init.mkString(".") + val configs = split.last.split("_") + Seq(new ConfigsAnnotation(configs map { config => s"${packageName}.${config}" } )) + }, helpText = "A string of underscore-delimited configs (configs have decreasing precendence from left to right).", shortOption = Some("LC") ) From 8d5927913f0411ada620fe6084fa7f9060c6aa52 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 16 May 2020 22:48:42 +0000 Subject: [PATCH 126/139] [stage] Support using Chipyard's stage for non-processor designs --- .../src/main/scala/stage/phases/AddDefaultTests.scala | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala index fce5d432..27ff2b25 100644 --- a/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala +++ b/generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala @@ -16,6 +16,7 @@ import freechips.rocketchip.stage.RocketChipOptions import freechips.rocketchip.stage.phases.{RocketTestSuiteAnnotation} import freechips.rocketchip.system.{RocketTestSuite, TestGeneration} import freechips.rocketchip.util.HasRocketChipStageUtils +import freechips.rocketchip.tile.XLen import chipyard.TestSuiteHelper @@ -30,9 +31,13 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS private def addTestSuiteAnnotations(implicit p: Parameters): Seq[Annotation] = { val annotations = mutable.ArrayBuffer[Annotation]() val suiteHelper = new TestSuiteHelper - suiteHelper.addRocketTestSuites - suiteHelper.addBoomTestSuites - suiteHelper.addArianeTestSuites + // Use Xlen as a proxy for detecting if we are a processor-like target + // The underlying test suites expect this field to be defined + if (p.lift(XLen).nonEmpty) { + suiteHelper.addRocketTestSuites + suiteHelper.addBoomTestSuites + suiteHelper.addArianeTestSuites + } // if hwacha parameter exists then generate its tests // TODO: find a more elegant way to do this. either through From e913ddbbbe407272b60527f683322ff996200b2e Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 16 May 2020 16:45:50 -0700 Subject: [PATCH 127/139] [traceio] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index 72cafd8c..cf536b68 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit 72cafd8c867f3a1a6decac62e6e77b9b6de02be7 +Subproject commit cf536b685dba3063b623ccffeaf68517e234966b From 99846c1ccbf48709d266680b94c8cdc3d1832398 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:17 +0000 Subject: [PATCH 128/139] [firechip] Use the standard Chipyard generator --- .../firechip/src/main/scala/Generator.scala | 73 ------------------- .../src/test/scala/ScalaTestSuite.scala | 39 +++------- sims/firesim | 2 +- 3 files changed, 13 insertions(+), 101 deletions(-) delete mode 100644 generators/firechip/src/main/scala/Generator.scala diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala deleted file mode 100644 index 01747bb3..00000000 --- a/generators/firechip/src/main/scala/Generator.scala +++ /dev/null @@ -1,73 +0,0 @@ -//See LICENSE for license details. - -package firesim.firesim - -import java.io.{File, FileWriter} - -import chisel3.RawModule -import chisel3.internal.firrtl.{Circuit, Port} - -import freechips.rocketchip.diplomacy.{ValName, AutoBundle} -import freechips.rocketchip.devices.debug.DebugIO -import freechips.rocketchip.util.{ElaborationArtefacts} -import freechips.rocketchip.system.DefaultTestSuites._ -import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite} -import freechips.rocketchip.config.Parameters -import freechips.rocketchip.subsystem.RocketTilesKey -import freechips.rocketchip.tile.XLen - -import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities} - -import scala.util.Try - -import chipyard.TestSuiteHelper - -trait HasTestSuites { - def addTestSuites(targetName: String, params: Parameters) { - val suiteHelper = new TestSuiteHelper - suiteHelper.addRocketTestSuites(params) - suiteHelper.addBoomTestSuites(params) - suiteHelper.addArianeTestSuites(params) - TestGeneration.addSuites(suiteHelper.suites.values.toSeq) - TestGeneration.addSuite(FastBlockdevTests) - TestGeneration.addSuite(SlowBlockdevTests) - if (!targetName.contains("NoNIC")) - TestGeneration.addSuite(NICLoopbackTests) - - import hwacha.HwachaTestSuites._ - if (Try(params(hwacha.HwachaNLanes)).getOrElse(0) > 0) { - TestGeneration.addSuites(rv64uv.map(_("p"))) - TestGeneration.addSuites(rv64uv.map(_("vp"))) - TestGeneration.addSuite(rv64sv("p")) - TestGeneration.addSuite(hwachaBmarks) - } - } -} - -// Mixed into an App or into a TestSuite -trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSuites { - /** Output software test Makefrags, which provide targets for integration testing. */ - def generateTestSuiteMakefrags { - addTestSuites(names.topModuleClass, targetParams) - writeOutputFile(s"$longName.d", TestGeneration.generateMakeFrag) // Subsystem-specific test suites - } - - // Output miscellaneous files produced as a side-effect of elaboration - def generateArtefacts { - // generate RC's artefacts - ElaborationArtefacts.files.foreach { case (extension, contents) => - writeOutputFile(s"${longName}.${extension}", contents ()) - } - } -} - -object FireSimGenerator extends App with IsFireSimGeneratorLike { - override lazy val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs - lazy val generatorArgs = GeneratorArgs(args) - lazy val genDir = new File(names.targetDir) - // The only reason this is not generateFirrtl; generateAnno is that we need to use a different - // JsonProtocol to properly write out the annotations. Fix once the generated are unified - elaborate - generateTestSuiteMakefrags - generateArtefacts -} diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 3ab4162c..1e83271c 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -12,38 +12,27 @@ import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} import freechips.rocketchip.system.TestGeneration._ import freechips.rocketchip.system.DefaultTestSuites._ -import firesim.util.GeneratorArgs - abstract class FireSimTestSuite( topModuleClass: String, targetConfigs: String, platformConfigs: String, N: Int = 8 - ) extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { + ) extends firesim.TestSuiteCommon { import scala.concurrent.duration._ import ExecutionContext.Implicits.global - val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + val topModuleProject = "firesim.firesim" - lazy val generatorArgs = GeneratorArgs( - midasFlowKind = "midas", - targetDir = "generated-src", - topModuleProject = "firesim.firesim", - topModuleClass = topModuleClass, - targetConfigProject = "firesim.firesim", - targetConfigs = targetConfigs ++ "_WithScalaTestFeatures", - platformConfigProject = "firesim.firesim", - platformConfigs = platformConfigs) - - // From HasFireSimGeneratorUtilities - // For the firesim utilities to use the same directory as the test suite - override lazy val testDir = genDir + val chipyardLongName = topModuleProject + "." + topModuleClass + "." + targetConfigs // From TestSuiteCommon - val targetTuple = generatorArgs.tupleName - val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", - s"TARGET_CONFIG=${generatorArgs.targetConfigs}", - s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") + val targetTuple = s"$topModuleClass-$targetConfigs-$platformConfigs" + val commonMakeArgs = Seq(s"DESIGN=${topModuleClass}", + s"TARGET_CONFIG=${targetConfigs}", + s"PLATFORM_CONFIG=${platformConfigs}") + + override lazy val genDir = new File(firesimDir, s"generated-src/${chipyardLongName}") + def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), @@ -127,20 +116,16 @@ abstract class FireSimTestSuite( } clean - mkdirs - elaborate - generateTestSuiteMakefrags - generateArtefacts runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) - runSuite("verilator")(FastBlockdevTests) + //runSuite("verilator")(FastBlockdevTests) } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { - runSuite("verilator")(NICLoopbackTests) + //runSuite("verilator")(NICLoopbackTests) } //class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { // runSuite("verilator")(NICLoopbackTests) diff --git a/sims/firesim b/sims/firesim index 4e94c1a0..11cce04c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4e94c1a0131dc673f894c62f9a110637844a806a +Subproject commit 11cce04c538cd805d8d23d15f0b6231846bec1ce From 96e838c773c8a32de55f0636ee46bc5d7e73e556 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 17 May 2020 00:18:54 +0000 Subject: [PATCH 129/139] [firechip] Set the cover property library in FireSim Harnesses --- generators/firechip/src/main/scala/FireSim.scala | 1 + generators/firechip/src/main/scala/FireSimMulticlockPOC.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala index 50f6f658..a4cea5ec 100644 --- a/generators/firechip/src/main/scala/FireSim.scala +++ b/generators/firechip/src/main/scala/FireSim.scala @@ -29,6 +29,7 @@ object NodeIdx { } class FireSim(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge) val clock = clockBridge.io.clocks.head val reset = WireInit(false.B) diff --git a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala index 758cb055..1f1ae06a 100644 --- a/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala +++ b/generators/firechip/src/main/scala/FireSimMulticlockPOC.scala @@ -84,6 +84,7 @@ class FiresimMulticlockTopModule[+L <: DigitalTop](l: L) extends chipyard.Digita // Harness Definition class FireSimMulticlockPOC(implicit val p: Parameters) extends RawModule { + freechips.rocketchip.util.property.cover.setPropLib(new midas.passes.FireSimPropertyLibrary()) val clockBridge = Module(new RationalClockBridge(p(FireSimClockKey).additionalClocks:_*)) val refClock = clockBridge.io.clocks.head val reset = WireInit(false.B) From 465e96a5ca3b5198434bb983fab9bb7af8d6f2d2 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Mon, 18 May 2020 12:21:17 -0700 Subject: [PATCH 130/139] bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index cf536b68..b02bd8ea 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit cf536b685dba3063b623ccffeaf68517e234966b +Subproject commit b02bd8eacaffe425811bd3fd8ef7d30772ae3cb7 From db65105163b3728fe89121d4feb73e091936c140 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 18 May 2020 19:23:16 +0000 Subject: [PATCH 131/139] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 11cce04c..3f36872c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 11cce04c538cd805d8d23d15f0b6231846bec1ce +Subproject commit 3f36872cdd5aec2ac28c7e3879e0a2e41eb00f57 From fa2d620fb2367712ef2aa4c5ac43b3e32f2f052f Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 19 May 2020 00:50:14 +0000 Subject: [PATCH 132/139] Remove commented code in ScalaTests --- .../src/test/scala/ScalaTestSuite.scala | 77 +++---------------- 1 file changed, 10 insertions(+), 67 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 1e83271c..f92a7960 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -6,6 +6,7 @@ import java.io.File import scala.concurrent.{Future, Await, ExecutionContext} import scala.sys.process.{stringSeqToProcess, ProcessLogger} import scala.io.Source +import org.scalatest.Suites import freechips.rocketchip.diplomacy._ import freechips.rocketchip.system.{RocketTestSuite, BenchmarkTestSuite} @@ -50,12 +51,6 @@ abstract class FireSimTestSuite( } } - //def runReplay(backend: String, replayBackend: String, name: String) = { - // val dir = (new File(outDir, backend)).getAbsolutePath - // (Seq("make", s"replay-$replayBackend", - // s"SAMPLE=${dir}/${name}.sample", s"output_dir=$dir") ++ makeArgs).! - //} - def runSuite(backend: String, debug: Boolean = false)(suite: RocketTestSuite) { // compile emulators behavior of s"${suite.makeTargetName} running on $backend" @@ -72,20 +67,6 @@ abstract class FireSimTestSuite( results.flatten foreach { case (name, exitcode) => it should s"pass $name" in { assert(exitcode == 0) } } - //replayBackends foreach { replayBackend => - // if (platformParams(midas.EnableSnapshot) && isCmdAvailable("vcs")) { - // assert((Seq("make", s"vcs-$replayBackend") ++ makeArgs).! == 0) // compile vcs - // suite.names foreach { name => - // it should s"replay $name in $replayBackend" in { - // assert(runReplay(backend, replayBackend, s"$name$postfix") == 0) - // } - // } - // } else { - // suite.names foreach { name => - // ignore should s"replay $name in $backend" - // } - // } - //} } else { ignore should s"pass $backend" } @@ -117,61 +98,23 @@ abstract class FireSimTestSuite( clean runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0""")) - //diffTracelog("rv64ui-p-simple.out") runSuite("verilator")(benchmarks) - //runSuite("verilator")(FastBlockdevTests) } class RocketF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimQuadRocketConfig", "WithSynthAsserts_BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimLargeBoomConfig", "BaseF1Config") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") { - //runSuite("verilator")(NICLoopbackTests) -} -//class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") { -// runSuite("verilator")(NICLoopbackTests) -//} -// Disabled until RAM optimizations re-enabled in multiclock -//class RamModelRocketF1Tests extends FireSimTestSuite("FireSim", "FireSimDualRocketConfig", "BaseF1Config_MCRams") -//class RamModelBoomF1Tests extends FireSimTestSuite("FireSim", "FireSimBoomConfig", "BaseF1Config_MCRams") - +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimRocketConfig", "BaseF1Config") // Multiclock tests class RocketMulticlockF1Tests extends FireSimTestSuite( "FireSimMulticlockPOC", "FireSimQuadRocketMulticlockConfig", "WithSynthAsserts_BaseF1Config") -// Jerry broke these -- damn it Jerry. -//abstract class FireSimTraceGenTest(targetConfig: String, platformConfig: String) -// extends firesim.TestSuiteCommon with IsFireSimGeneratorLike { -// val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs -// -// lazy val generatorArgs = GeneratorArgs( -// midasFlowKind = "midas", -// targetDir = "generated-src", -// topModuleProject = "firesim.firesim", -// topModuleClass = "FireSimTraceGen", -// targetConfigProject = "firesim.firesim", -// targetConfigs = targetConfig ++ "_WithScalaTestFeatures", -// platformConfigProject = "firesim.firesim", -// platformConfigs = platformConfig) -// -// // From HasFireSimGeneratorUtilities -// // For the firesim utilities to use the same directory as the test suite -// override lazy val testDir = genDir -// -// // From TestSuiteCommon -// val targetTuple = generatorArgs.tupleName -// val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", -// s"TARGET_CONFIG=${generatorArgs.targetConfigs}", -// s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") -// -// it should "pass" in { -// assert(make("fsim-tracegen") == 0) -// } -//} -// -//class FireSimLLCTraceGenTest extends FireSimTraceGenTest( -// "DDR3FRFCFSLLC4MB_FireSimTraceGenConfig", "BaseF1Config") -// -//class FireSimL2TraceGenTest extends FireSimTraceGenTest( -// "DDR3FRFCFS_FireSimTraceGenL2Config", "BaseF1Config") +class ArianeF1Tests extends FireSimTestSuite("FireSim", "WithNIC_DDR3FRFCFSLLC4MB_FireSimArianeConfig", "BaseF1Config") + +// This test suite only mirrors what is run in CI. CI invokes each test individually, using a testOnly call. +class CITests extends Suites( + new RocketF1Tests, + new BoomF1Tests, + new RocketNICF1Tests, + new RocketMulticlockF1Tests) From 7f3ae32e33b2e782da4dc4f8948b8927f4b3cc54 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 19 May 2020 01:00:25 +0000 Subject: [PATCH 133/139] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 3f36872c..a6911eca 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 3f36872cdd5aec2ac28c7e3879e0a2e41eb00f57 +Subproject commit a6911eca084608965c00d79931d208188e70d8cb From 0fc5a5409636646cd607a9e85cd46f198d629881 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 12:10:11 -0700 Subject: [PATCH 134/139] small cleanup to issues [ci skip] --- .github/ISSUE_TEMPLATE/bug-report.md | 12 +++++------- .github/ISSUE_TEMPLATE/question.md | 5 +++++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 4da4667e..959b6306 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -8,16 +8,14 @@ labels: bug **Impact**: rtl | software | unknown | other +**Tell us about your environment:** +*Chipyard Version:* +*OS:* +*Other:* + **What is the current behavior?** **What is the expected behavior?** -**Please tell us about your environment:** - - **Other information** diff --git a/.github/ISSUE_TEMPLATE/question.md b/.github/ISSUE_TEMPLATE/question.md index b8c3f482..f1b4e218 100644 --- a/.github/ISSUE_TEMPLATE/question.md +++ b/.github/ISSUE_TEMPLATE/question.md @@ -5,6 +5,11 @@ labels: question --- + + From dfc6c9ae5d475117bde6b8e0b582aa573c5f1cb7 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 16:20:48 -0700 Subject: [PATCH 135/139] bump nvdla workload for one less submodule [ci skip] --- software/nvdla-workload | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/software/nvdla-workload b/software/nvdla-workload index 02faf596..88b09e01 160000 --- a/software/nvdla-workload +++ b/software/nvdla-workload @@ -1 +1 @@ -Subproject commit 02faf59692f88b66f8720d4eefa85aae385288a0 +Subproject commit 88b09e0171bdf6b3a77f711c2c8015dc727e460b From 9c73037e93be4dbea93ee9738ef9fb530287a226 Mon Sep 17 00:00:00 2001 From: alonamid Date: Tue, 19 May 2020 19:09:53 -0700 Subject: [PATCH 136/139] Version Upgrade Docs Notes (#545) * version upgrade notes * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez * [skip ci] Update docs/Chipyard-Basics/Initial-Repo-Setup.rst Co-authored-by: Abraham Gonzalez Co-authored-by: Abraham Gonzalez --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 08930f50..88c8b21e 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -86,3 +86,28 @@ This depends on what you are planning to do with Chipyard. * If you intend to run a tutorial VLSI flow using one of the Chipyard examples, go to :ref:`tutorial` and follow the instructions. * If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions. + +Upgrading Chipyard Release Versions +------------------------------------------- + +In order to upgrade between Chipyard versions, we recommend using a fresh clone of the repository (or your fork, with the new release merged into it). + + +Chipyard is a complex framework that depends on a mix of build systems and scripts. Specifically, it relies on git submodules, on sbt build files, and on custom written bash scripts and generated files. +For this reason, upgrading between Chipyard versions is **not** as trivial as just running ``git submodule update -recursive``. This will result in recursive cloning of large submodules that are not necessarily used within your specific Chipyard environments. Furthermore, it will not resolve the status of stale state generated files which may not be compatible between release versions. + + +If you are an advanced git user, an alternative approach to a fresh repository clone may be to run ``git clean -dfx``, and then run the standard Chipyard setup sequence. This approach is dangerous, and **not-recommended** for users who are not deeply familiar with git, since it "blows up" the repository state and removes all untracked and modified files without warning. Hence, if you were working on custom un-committed changes, you would lose them. + +If you would still like to try to perform an in-place manual version upgrade (**not-recommended**), we recommend at least trying to resolve stale state in the following areas: + +* Delete stale ``target`` directories generated by sbt. + +* Delete jar collateral generated by FIRRTL (``lib/firrtl.jar``) + +* Re-generate generated scripts and source files (for example, ``env.sh``) + +* Re-generating/deleting target software state (Linux kernel binaries, Linux images) within FireMarshal + + +This is by no means a comprehensive list of potential stale state within Chipyard. Hence, as mentioned earlier, the recommended method for a Chipyard version upgrade is a fresh clone (or a merge, and then a fresh clone). From 0d087b6d3257da270c7d6ae08944c325f6afe310 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 18:54:37 -0700 Subject: [PATCH 137/139] add auto-gen comments | git init dromajo dir --- scripts/build-toolchains.sh | 3 +++ scripts/init-submodules-no-riscv-tools-nolog.sh | 1 + 2 files changed, 4 insertions(+) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index cbe15161..fa24214c 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -131,12 +131,14 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu # make Dromajo +git submodule --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src cd "$RDIR" # create specific env.sh { + echo "# auto-generated by build-toolchains.sh" echo "export CHIPYARD_TOOLCHAIN_SOURCED=1" echo "export RISCV=$(printf '%q' "$RISCV")" echo "export PATH=\${RISCV}/bin:\${PATH}" @@ -144,5 +146,6 @@ cd "$RDIR" } > env-$TOOLCHAIN.sh # create general env.sh +echo "# line auto-generated by build-toolchains.sh" >> env.sh echo "source \$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/env-$TOOLCHAIN.sh" >> env.sh echo "Toolchain Build Complete!" diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 888feb0e..f8ff84ee 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -73,4 +73,5 @@ git submodule update --init software/firemarshal if [ ! -f $RDIR/software/firemarshal/marshal-config.yaml ]; then echo "firesim-dir: '../../sims/firesim/'" > $RDIR/software/firemarshal/marshal-config.yaml fi +echo "# line auto-generated by init-submodules-no-riscv-tools.sh" >> $RDIR/env.sh echo "PATH=\$( realpath \$(dirname "\${BASH_SOURCE[0]:-\${\(%\):-%x}}") )/software/firemarshal:\$PATH" >> $RDIR/env.sh From d2060947b6cf3da18e8abae90b076c78acc10708 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Tue, 19 May 2020 19:44:35 -0700 Subject: [PATCH 138/139] bump toolchain version | fix git submodule update --- .circleci/config.yml | 2 +- scripts/build-toolchains.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 5361a944..03943fa8 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -6,7 +6,7 @@ version: 2.1 parameters: tools-cache-version: type: string - default: "v4" + default: "v5" # default execution env.s executors: diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index fa24214c..62a2f74b 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -131,7 +131,7 @@ SRCDIR="$(pwd)/toolchains" module_all libgloss --prefix="${RISCV}/riscv64-unknow SRCDIR="$(pwd)/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu # make Dromajo -git submodule --init $CHIPYARD_DIR/tools/dromajo/dromajo-src +git submodule update --init $CHIPYARD_DIR/tools/dromajo/dromajo-src make -C $CHIPYARD_DIR/tools/dromajo/dromajo-src/src cd "$RDIR" From 7208ab0b68afa1af2140bfb721a3aaea13be000d Mon Sep 17 00:00:00 2001 From: Albert Magyar Date: Fri, 15 May 2020 10:26:37 -0700 Subject: [PATCH 139/139] Don't try to init nonexistent midas submodule --- scripts/init-submodules-no-riscv-tools-nolog.sh | 5 ----- 1 file changed, 5 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index f8ff84ee..70b504b4 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -59,11 +59,6 @@ git submodule update --init generators/sha3 git config --unset submodule.sims/firesim.update # Minimal non-recursive clone to initialize sbt dependencies git submodule update --init sims/firesim -( - cd sims/firesim - # Initialize dependencies for MIDAS-level RTL simulation - git submodule update --init sim/midas -) git config submodule.sims/firesim.update none # Only shallow clone needed for basic SW tests