From 4156bd85131c23d0cd377a1e4b0b63012a948b52 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sun, 10 Jan 2021 23:39:16 -0800 Subject: [PATCH] Bump testchipip and sodor | increase sodor SerialTL width for faster binary loading --- .../chipyard/src/main/scala/config/SodorConfigs.scala | 6 ++++++ generators/riscv-sodor | 2 +- generators/testchipip | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 998ccff9..3679ed07 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -16,6 +17,7 @@ class Sodor1StageConfig extends Config( class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -25,6 +27,7 @@ class Sodor2StageConfig extends Config( class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -34,6 +37,7 @@ class Sodor3StageConfig extends Config( class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -43,6 +47,7 @@ class Sodor3StageSinglePortConfig extends Config( class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory @@ -52,6 +57,7 @@ class Sodor5StageConfig extends Config( class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new testchipip.WithSerialTLWidth(32) ++ new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 8fc51640..449354c2 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 8fc516409fde12e447ad78f9d13962b5451c4485 +Subproject commit 449354c27bf07ccc865dc6c005df1d08eaf5b01c diff --git a/generators/testchipip b/generators/testchipip index ca67a843..a62ef167 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ca67a843bd8f568e205981380c11d321d1bad677 +Subproject commit a62ef167bcd48e6d9f9f6aabc4db63ac701ad522