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Bump firesim | fix testchipip segfaults

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This commit is contained in:
Jerry Zhao
2024-01-01 15:44:23 -08:00
parent 5f2b2181c2
commit 41651edbdc
4 changed files with 5 additions and 5 deletions
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4
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -107,7 +107,7 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
// Maps the UART device to the on-board USB-UART // Maps the UART device to the on-board USB-UART
class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTPort) => { case (th: HasHarnessInstantiators, port: UARTPort, chipId: Int) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart") val harnessIO = IO(chiselTypeOf(port.io)).suggestName("uart")
harnessIO <> port.io harnessIO <> port.io
@@ -126,7 +126,7 @@ class WithArty100TUART(rxdPin: String = "A9", txdPin: String = "D10") extends Ha
class WithArty100TPMODUART extends WithArty100TUART("G2", "F3") class WithArty100TPMODUART extends WithArty100TUART("G2", "F3")
class WithArty100TJTAG extends HarnessBinder({ class WithArty100TJTAG extends HarnessBinder({
case (th: HasHarnessInstantiators, port: JTAGPort) => { case (th: HasHarnessInstantiators, port: JTAGPort, chipId: Int) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness] val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag") val harnessIO = IO(chiselTypeOf(port.io)).suggestName("jtag")
harnessIO <> port.io harnessIO <> port.io

2
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
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@@ -100,7 +100,7 @@ class WithSimAXIMem extends HarnessBinder({
case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => { case (th: HasHarnessInstantiators, port: AXI4MemPort, chipId: Int) => {
val mem = LazyModule(new SimAXIMem(port.edge, size=port.params.master.size)(Parameters.empty)) val mem = LazyModule(new SimAXIMem(port.edge, size=port.params.master.size)(Parameters.empty))
withClock(port.io.clock) { Module(mem.module) } withClock(port.io.clock) { Module(mem.module) }
mem.io_axi4.head <> port.io mem.io_axi4.head <> port.io.bits
} }
}) })

2
generators/testchipip

Submodule generators/testchipip updated: b3b7443538...263980a9f5

2
sims/firesim

Submodule sims/firesim updated: e975893595...c113e2d600