From 439a72f21bb60fcccd32a67fd73250e5ee8d1462 Mon Sep 17 00:00:00 2001 From: Vamber Yang Date: Tue, 16 May 2023 20:24:52 -0700 Subject: [PATCH] Add new config for using PriorityXBar for coalescer --- .../src/main/scala/config/GPUConfig.scala | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/GPUConfig.scala b/generators/chipyard/src/main/scala/config/GPUConfig.scala index 5282100c..edd49369 100644 --- a/generators/chipyard/src/main/scala/config/GPUConfig.scala +++ b/generators/chipyard/src/main/scala/config/GPUConfig.scala @@ -54,4 +54,22 @@ class MemtraceCore256SbusConfig extends Config( // Small Rocket core that does nothing new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ new chipyard.config.AbstractConfig -) \ No newline at end of file +) + +class MemtraceCorePoXarConfig extends Config( + // Memtrace + new freechips.rocketchip.subsystem.WithMemtraceCore("vecadd.core1.thread4.trace", + traceHasSource = false) ++ + // new freechips.rocketchip.subsystem.WithMemtraceCore("nvbit.vecadd.n100000.filter_sm0.trace", + // traceHasSource = false) ++ + new freechips.rocketchip.subsystem.WithCoalescer ++ + new freechips.rocketchip.subsystem.WithPriorityCoalXbar++ + new freechips.rocketchip.subsystem.WithNLanes(4) ++ + // L2 + new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++ + new freechips.rocketchip.subsystem.WithNBanks(4) ++ + new chipyard.config.WithSystemBusWidth(64) ++ + // Small Rocket core that does nothing + new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++ + new chipyard.config.AbstractConfig + ) \ No newline at end of file