From 439ba9731e3b1db274bb4d112ac1c9397807b594 Mon Sep 17 00:00:00 2001 From: michael-etzkorn Date: Sun, 14 Aug 2022 12:21:45 -0500 Subject: [PATCH] Update SiFive submodules to CHIPS fork --- .gitmodules | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.gitmodules b/.gitmodules index 11ca0d5a..cb7319f3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -15,7 +15,7 @@ url = https://github.com/riscv-boom/riscv-boom.git [submodule "generators/sifive-blocks"] path = generators/sifive-blocks - url = https://github.com/sifive/sifive-blocks.git + url = https://github.com/chipsalliance/rocket-chip-blocks.git [submodule "generators/hwacha"] path = generators/hwacha url = https://github.com/ucb-bar/hwacha.git @@ -27,7 +27,7 @@ url = https://github.com/firesim/icenet.git [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache - url = https://github.com/sifive/block-inclusivecache-sifive.git + url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git [submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] path = toolchains/riscv-tools/riscv-gnu-toolchain url = https://github.com/riscv/riscv-gnu-toolchain.git @@ -121,7 +121,7 @@ url = https://github.com/ucb-bar/riscv-sodor.git [submodule "fpga/fpga-shells"] path = fpga/fpga-shells - url = https://github.com/sifive/fpga-shells.git + url = https://github.com/chipsalliance/rocket-chip-fpga-shells.git [submodule "tools/api-config-chipsalliance"] path = tools/api-config-chipsalliance url = https://github.com/chipsalliance/api-config-chipsalliance.git