Merge pull request #879 from ucb-bar/remove-gen-sim-files

Remove GenerateSimFiles and use make instead
2021-05-13 16:41:17 -05:00
parent 1f28d373ff 16cdc88c52
commit 45f63a1409
12 changed files with 90 additions and 163 deletions
--- a/build.sbt
+++ b/build.sbt
@@ -183,7 +183,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO

 lazy val chipyard = (project in file("generators/chipyard"))
  .sourceDependency(testchipip, testchipipLib)
-  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
+  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
    sha3, // On separate line to allow for cleaner tutorial-setup patches
    dsptools, `rocket-dsptools`,
    gemmini, icenet, tracegen, cva6, nvdla, sodor)
@@ -192,14 +192,10 @@ lazy val chipyard = (project in file("generators/chipyard"))

 lazy val tracegen = (project in file("generators/tracegen"))
  .sourceDependency(testchipip, testchipipLib)
-  .dependsOn(rocketchip, sifive_cache, boom, utilities)
+  .dependsOn(rocketchip, sifive_cache, boom)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val utilities = (project in file("generators/utilities"))
-  .sourceDependency(testchipip, testchipipLib)
-  .settings(commonSettings)
-
 lazy val icenet = (project in file("generators/icenet"))
  .sourceDependency(testchipip, testchipipLib)
  .dependsOn(rocketchip)
--- a/common.mk
+++ b/common.mk
@@ -20,7 +20,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_REQS         = additional make requirements to build the simulator" \
 "   ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best with sbtn or sbt script)"

-EXTRA_GENERATOR_REQS ?=
+EXTRA_GENERATOR_REQS ?= $(BOOTROM_TARGETS)
 EXTRA_SIM_CXXFLAGS   ?=
 EXTRA_SIM_LDFLAGS    ?=
 EXTRA_SIM_SOURCES    ?=
@@ -85,10 +85,13 @@ else
 endif

 #########################################################################################
-# create list of simulation file inputs
+# copy over bootrom files
 #########################################################################################
-$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS)
-	$(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name))
+$(build_dir):
+	mkdir -p $@
+
+$(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
+	cp -f $< $@

 #########################################################################################
 # create firrtl file rule and variables
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -73,6 +73,21 @@ default: $(mcs)
 fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND)
 fpga_common_script_dir := $(fpga_dir)/common/tcl

+#########################################################################################
+# setup misc. sim files
+#########################################################################################
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
+
+# copy files but ignore *.h files in *.f (match vcs)
+$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
+	cp -f $^ $(build_dir)
+	$(foreach file,\
+		$^,\
+		$(if $(filter %.h,$(file)),\
+			,\
+			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+
 #########################################################################################
 # import other necessary rules and variables
 #########################################################################################
--- a/generators/utilities/src/main/resources/csrc/emulator.cc
+++ b/generators/utilities/src/main/resources/csrc/emulator.cc
--- a/generators/chipyard/src/main/scala/ConfigFragments.scala
+++ b/generators/chipyard/src/main/scala/ConfigFragments.scala
@@ -15,6 +15,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 import freechips.rocketchip.tilelink.{HasTLBusParams}
 import freechips.rocketchip.util.{AsyncResetReg, Symmetric}
 import freechips.rocketchip.prci._
+import freechips.rocketchip.stage.phases.TargetDirKey

 import testchipip._
 import tracegen.{TraceGenSystem}
@@ -36,7 +37,7 @@ import chipyard._
 // -----------------------

 class WithBootROM extends Config((site, here, up) => {
-  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"./bootrom/bootrom.rv${site(XLen)}.img"))
+  case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = s"${site(TargetDirKey)}/bootrom.rv${site(XLen)}.img"))
 })

 // DOC include start: gpio config fragment
--- a/generators/utilities/src/main/resources/bootrom
+++ b/generators/utilities/src/main/resources/bootrom
@@ -1 +0,0 @@
-../../../../rocket-chip/bootrom
--- a/generators/utilities/src/main/scala/Simulator.scala
+++ b/generators/utilities/src/main/scala/Simulator.scala
@@ -1,143 +0,0 @@
-package utilities
-
-import java.io.File
-
-case class GenerateSimConfig(
-  targetDir: String = ".",
-  dotFName: String = "sim_files.f",
-  simulator: Option[Simulator] = Some(VerilatorSimulator)
-)
-
-sealed trait Simulator
-object VerilatorSimulator extends Simulator
-object VCSSimulator extends Simulator
-
-trait HasGenerateSimConfig {
-  val parser = new scopt.OptionParser[GenerateSimConfig]("GenerateSimFiles") {
-    head("GenerateSimFiles", "0.1")
-
-    opt[String]("simulator")
-      .abbr("sim")
-      .valueName("<simulator-name>")
-      .action((x, c) => x match {
-        case "verilator" => c.copy(simulator = Some(VerilatorSimulator))
-        case "vcs" => c.copy(simulator = Some(VCSSimulator))
-        case "none" => c.copy(simulator = None)
-        case _ => throw new Exception(s"Unrecognized simulator $x")
-      })
-      .text("Name of simulator to generate files for (verilator, vcs, none)")
-
-    opt[String]("target-dir")
-      .abbr("td")
-      .valueName("<target-directory>")
-      .action((x, c) => c.copy(targetDir = x))
-      .text("Target directory to put files")
-
-    opt[String]("dotFName")
-      .abbr("df")
-      .valueName("<dot-f filename>")
-      .action((x, c) => c.copy(dotFName = x))
-      .text("Name of generated dot-f file")
-  }
-}
-
-object GenerateSimFiles extends App with HasGenerateSimConfig {
-  def addOption(file: File, cfg: GenerateSimConfig): String = {
-    val fname = file.getCanonicalPath
-    // deal with header files
-    if (fname.takeRight(2) == ".h") {
-      cfg.simulator match {
-        // verilator needs to explicitly include verilator.h, so use the -FI option
-        case Some(VerilatorSimulator) => s"-FI ${fname}"
-        // vcs pulls headers in with +incdir, doesn't have anything like verilator.h
-        case Some(VCSSimulator) => ""
-        case None => ""
-      }
-    } else { // do nothing otherwise
-      fname
-    }
-  }
-  def writeDotF(lines: Seq[String], cfg: GenerateSimConfig): Unit = {
-    writeTextToFile(lines.mkString("\n"), new File(cfg.targetDir, cfg.dotFName))
-  }
-  // From FIRRTL
-  def safeFile[A](fileName: String)(code: => A) = try { code } catch {
-    case e@ (_: java.io.FileNotFoundException | _: NullPointerException) => throw new Exception(fileName, e)
-    case t: Throwable                                            => throw t
-  }
-  // From FIRRTL
-  def writeResource(name: String, targetDir: String): File = {
-    val in = getClass.getResourceAsStream(name)
-    val p = java.nio.file.Paths.get(name)
-    val fname = p.getFileName().toString();
-
-    val f = new File(targetDir, fname)
-    val out = new java.io.FileOutputStream(f)
-    safeFile(name)(Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write))
-    out.close()
-    f
-  }
-  // From FIRRTL
-  def writeTextToFile(text: String, file: File) {
-    val out = new java.io.PrintWriter(file)
-    out.write(text)
-    out.close()
-  }
-  def resources(sim: Option[Simulator]): Seq[String] = Seq(
-    "/testchipip/csrc/SimSerial.cc",
-    "/testchipip/csrc/testchip_tsi.cc",
-    "/testchipip/csrc/testchip_tsi.h",
-    "/testchipip/csrc/SimDRAM.cc",
-    "/testchipip/csrc/mm.h",
-    "/testchipip/csrc/mm.cc",
-    "/testchipip/csrc/mm_dramsim2.h",
-    "/testchipip/csrc/mm_dramsim2.cc",
-    "/csrc/SimDTM.cc",
-    "/csrc/SimJTAG.cc",
-    "/csrc/remote_bitbang.h",
-    "/csrc/remote_bitbang.cc",
-    "/vsrc/EICG_wrapper.v",
-    ) ++ (sim match {
-      case None => Seq()
-      case _ => Seq(
-        "/testchipip/csrc/SimSerial.cc",
-        "/testchipip/csrc/SimDRAM.cc",
-        "/testchipip/csrc/mm.h",
-        "/testchipip/csrc/mm.cc",
-        "/testchipip/csrc/mm_dramsim2.h",
-        "/testchipip/csrc/mm_dramsim2.cc",
-        "/csrc/SimDTM.cc",
-        "/csrc/SimJTAG.cc",
-        "/csrc/remote_bitbang.h",
-        "/csrc/remote_bitbang.cc",
-      )
-    }) ++ (sim match { // simulator specific files to include
-      case Some(VerilatorSimulator) => Seq(
-        "/csrc/emulator.cc",
-        "/csrc/verilator.h",
-      )
-      case Some(VCSSimulator) => Seq(
-        "/vsrc/TestDriver.v",
-      )
-      case None => Seq()
-    })
-
-  def writeBootrom(): Unit = {
-    firrtl.FileUtils.makeDirectory("./bootrom/")
-    writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
-    writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
-    writeResource("/bootrom/bootrom.img", "./bootrom/")
-  }
-
-  def writeFiles(cfg: GenerateSimConfig): Unit = {
-    writeBootrom()
-    firrtl.FileUtils.makeDirectory(cfg.targetDir)
-    val files = resources(cfg.simulator).map { writeResource(_, cfg.targetDir) }
-    writeDotF(files.map(addOption(_, cfg)), cfg)
-  }
-
-  parser.parse(args, GenerateSimConfig()) match {
-    case Some(cfg) => writeFiles(cfg)
-    case _ => // error message already shown
-  }
-}
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,17 +1,17 @@
 diff --git a/build.sbt b/build.sbt
-index e80b2a5..b1989d9 100644
+index 3123c4b8..487fc428 100644
 --- a/build.sbt
 +++ b/build.sbt
@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO
 lazy val chipyard = (project in file("generators/chipyard"))
   .sourceDependency(testchipip, testchipipLib)
-   .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
+   .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsptools`,
     gemmini, icenet, tracegen, cva6, nvdla, sodor)
   .settings(libraryDependencies ++= rocketLibDeps.value)
-@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
+@@ -223,11 +223,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
--- a/sims/common-sim-flags.mk
+++ b/sims/common-sim-flags.mk
@@ -21,3 +21,6 @@ SIM_LDFLAGS = \
 	-lfesvr \
 	-ldramsim \
 	$(EXTRA_SIM_LDFLAGS)
+
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -31,6 +31,21 @@ include $(base_dir)/vcs.mk
 default: $(sim)
 debug: $(sim_debug)

+#########################################################################################
+# simulaton requirements
+#########################################################################################
+SIM_FILE_REQS += \
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
+
+# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
+$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
+	cp -f $^ $(build_dir)
+	$(foreach file,\
+		$^,\
+		$(if $(filter %.h,$(file)),\
+			,\
+			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+
 #########################################################################################
 # import other necessary rules and variables
 #########################################################################################
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -30,6 +30,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug

 WAVEFORM_FLAG=-v$(sim_out_name).vcd

+include $(base_dir)/sims/common-sim-flags.mk
+
 # If verilator seed unspecified, verilator uses srand as random seed
 ifdef RANDOM_SEED
 SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
@@ -41,6 +43,37 @@ endif
 default: $(sim)
 debug: $(sim_debug)

+#########################################################################################
+# simulaton requirements
+#########################################################################################
+SIM_FILE_REQS += \
+	$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
+	$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
+
+# the following files are needed for emulator.cc to compile
+SIM_FILE_REQS += \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
+	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
+	$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
+	$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
+	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
+	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
+
+# copy files and add -FI for *.h files in *.f
+$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
+	cp -f $^ $(build_dir)
+	$(foreach file,\
+		$^,\
+		$(if $(filter %.h,$(file)),\
+			echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\
+			echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
+
 #########################################################################################
 # import other necessary rules and variables
 #########################################################################################
@@ -141,8 +174,6 @@ VERILATOR_NONCC_OPTS = \
 #----------------------------------------------------------------------------------------
 # gcc configuration/optimization
 #----------------------------------------------------------------------------------------
-include $(base_dir)/sims/common-sim-flags.mk
-
 VERILATOR_CXXFLAGS = \
 	$(SIM_CXXFLAGS) \
 	$(RUNTIME_PROFILING_CFLAGS) \
--- a/variables.mk
+++ b/variables.mk
@@ -107,8 +107,11 @@ endif
 # path to rocket-chip and testchipip
 #########################################################################################
 ROCKETCHIP_DIR       = $(base_dir)/generators/rocket-chip
+ROCKETCHIP_RSRCS_DIR = $(ROCKETCHIP_DIR)/src/main/resources
 TESTCHIP_DIR         = $(base_dir)/generators/testchipip
+TESTCHIP_RSRCS_DIR   = $(TESTCHIP_DIR)/src/main/resources
 CHIPYARD_FIRRTL_DIR  = $(base_dir)/tools/firrtl
+CHIPYARD_RSRCS_DIR   = $(base_dir)/generators/chipyard/src/main/resources

 #########################################################################################
 # names of various files needed to compile and run things
@@ -135,7 +138,11 @@ HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
 HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
 HARNESS_SMEMS_FIR  ?= $(build_dir)/$(long_name).harness.mems.fir

+BOOTROM_FILES   ?= bootrom.rv64.img bootrom.rv32.img
+BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
+
 # files that contain lists of files needed for VCS or Verilator simulation
+SIM_FILE_REQS =
 sim_files              ?= $(build_dir)/sim_files.f
 sim_top_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.top.f
 sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f