From 40c84faa557b05a8800fc4d89bd2a9b4b3f19db6 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 1 Jan 2024 17:14:30 -0800 Subject: [PATCH 01/17] ADD: organize abstract config into sections --- .../main/scala/config/AbstractConfig.scala | 100 ++++++++++++------ 1 file changed, 68 insertions(+), 32 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index cef46e04..9534ed23 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -11,6 +11,9 @@ import org.chipsalliance.cde.config.{Config} // -------------- class AbstractConfig extends Config( + // ================================== + // Set up TestHarness + // ================================== // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled @@ -28,6 +31,9 @@ class AbstractConfig extends Config( new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz + // ================================== + // Set up I/O harness + // ================================== // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs new chipyard.iobinders.WithSerialTLIOCells ++ @@ -51,38 +57,68 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ - // By default, punch out IOs to the Harness - new chipyard.clocking.WithPassthroughClockGenerator ++ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ - new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus - new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus - new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus - new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus - new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus - new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus - - new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address - new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address - new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface + // ================================== + // Set up Memory Devices + // ================================== + // External memory section + new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( - client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits - width = 32 // serial-tilelink interface with 32 lanes + client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */ + width = 32 /** serial-tilelink interface with 32 lanes */ ) )) ++ - new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs - new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks - new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels - new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model - new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 - new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + + // Peripheral section + new chipyard.config.WithUART ++ /** add a UART */ + + // Core section + new chipyard.config.WithBootROM ++ /** use default bootrom */ + new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ + new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ + + // ================================== + // Set up tiles + // ================================== + // Debug settings + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ + // TODO: add these fragments + // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ + // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ + + // Cache settings + new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ + + // Memory settings + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ + + // Core Settings + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ + + // ================================== + // Set up reset and clocking + // ================================== + new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */ + new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ + + new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */ + new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */ + new chipyard.config.WithControlBusFrequency(500.0) ++ /** Default 500 MHz cbus */ + new chipyard.config.WithSystemBusFrequency(500.0) ++ /** Default 500 MHz sbus */ + new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */ + new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */ + new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */ + + new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */ + new chipyard.clocking.WithPassthroughClockGenerator ++ + + // ================================== + // Base Settings + // ================================== + new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS */ + new freechips.rocketchip.system.BaseConfig) /** "base" rocketchip system */ From 502149d95fd4c734e4531335c029525721617081 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 1 Jan 2024 17:50:14 -0800 Subject: [PATCH 02/17] Update AbstractConfig.scala --- .../chipyard/src/main/scala/config/AbstractConfig.scala | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 9534ed23..7fe20bb7 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -76,16 +76,15 @@ class AbstractConfig extends Config( new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ - // ================================== - // Set up tiles - // ================================== - // Debug settings + // Debug section new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ - // TODO: add these fragments // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ + // ================================== + // Set up tiles + // ================================== // Cache settings new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ From 28ac74d11b2fb18cb03b2205f5068c407210b59b Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Mon, 1 Jan 2024 20:07:37 -0800 Subject: [PATCH 03/17] REFACTOR: adjust sections according to new mapping --- .../main/scala/config/AbstractConfig.scala | 67 ++++++++++++------- 1 file changed, 43 insertions(+), 24 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 7fe20bb7..24527687 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -11,9 +11,9 @@ import org.chipsalliance.cde.config.{Config} // -------------- class AbstractConfig extends Config( - // ================================== + // ================================================ // Set up TestHarness - // ================================== + // ================================================ // The HarnessBinders control generation of hardware in the TestHarness new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled @@ -31,9 +31,9 @@ class AbstractConfig extends Config( new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz - // ================================== + // ================================================ // Set up I/O harness - // ================================== + // ================================================ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs new chipyard.iobinders.WithSerialTLIOCells ++ @@ -57,9 +57,9 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ - // ================================== - // Set up Memory Devices - // ================================== + // ================================================ + // Set up External Memory and IO Devices + // ================================================ // External memory section new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( @@ -68,39 +68,54 @@ class AbstractConfig extends Config( ) )) ++ - // Peripheral section + // MMIO device section new chipyard.config.WithUART ++ /** add a UART */ - // Core section - new chipyard.config.WithBootROM ++ /** use default bootrom */ - new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ - new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ - - // Debug section + // ================================================ + // Set up Debugging + // ================================================ + // JTAG new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ + + // Boot Select Pins + new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ + new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ + + // ================================================ + // Set up Interrupts + // ================================================ + // CLINT and PLIC related settings goes here + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ + + // ================================================ + // Set up Tiles + // ================================================ + // core settings goes here + + + // ================================================ + // Set up Memory system + // ================================================ + // On-chip memory section + new chipyard.config.WithBootROM ++ /** use default bootrom */ - // ================================== - // Set up tiles - // ================================== // Cache settings new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ - // Memory settings + // Memory Bus settings new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */ new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ - // Core Settings - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ - - // ================================== - // Set up reset and clocking - // ================================== + // ================================================ + // Set up power, reset and clocking + // ================================================ + // clocking new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */ new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ @@ -116,6 +131,10 @@ class AbstractConfig extends Config( new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */ new chipyard.clocking.WithPassthroughClockGenerator ++ + // reset + + // power + // ================================== // Base Settings // ================================== From 1718e11a52a80405751e16de0767e852afe1cc4d Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 2 Jan 2024 10:15:07 -0800 Subject: [PATCH 04/17] Reorganize AbstractConfig further --- .../main/scala/config/AbstractConfig.scala | 94 ++++++++++--------- 1 file changed, 48 insertions(+), 46 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 34151f86..7d75206d 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -15,24 +15,24 @@ class AbstractConfig extends Config( // Set up TestHarness // ================================================ // The HarnessBinders control generation of hardware in the TestHarness - new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present - new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled - new chipyard.harness.WithSimTSIOverSerialTL ++ // add external serial-adapter and RAM - new chipyard.harness.WithSimJTAGDebug ++ // add SimJTAG if JTAG for debug exposed - new chipyard.harness.WithSimDMI ++ // add SimJTAG if DMI exposed - new chipyard.harness.WithGPIOTiedOff ++ // tie-off chiptop GPIOs, if GPIOs are present - new chipyard.harness.WithSimSPIFlashModel ++ // add simulated SPI flash memory, if SPI is enabled - new chipyard.harness.WithSimAXIMMIO ++ // add SimAXIMem for axi4 mmio port, if enabled - new chipyard.harness.WithTieOffInterrupts ++ // tie-off interrupt ports, if present - new chipyard.harness.WithTieOffL2FBusAXI ++ // tie-off external AXI4 master, if present - new chipyard.harness.WithCustomBootPinPlusArg ++ // drive custom-boot pin with a plusarg, if custom-boot-pin is present - new chipyard.harness.WithSimUARTToUARTTSI ++ // connect a SimUART to the UART-TSI port - new chipyard.harness.WithClockFromHarness ++ // all Clock I/O in ChipTop should be driven by harnessClockInstantiator - new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness - new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz + new chipyard.harness.WithUARTAdapter ++ /** add UART adapter to display UART on stdout, if uart is present */ + new chipyard.harness.WithBlackBoxSimMem ++ /** add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled */ + new chipyard.harness.WithSimTSIOverSerialTL ++ /** add external serial-adapter and RAM */ + new chipyard.harness.WithSimJTAGDebug ++ /** add SimJTAG if JTAG for debug exposed */ + new chipyard.harness.WithSimDMI ++ /** add SimJTAG if DMI exposed */ + new chipyard.harness.WithGPIOTiedOff ++ /** tie-off chiptop GPIOs, if GPIOs are present */ + new chipyard.harness.WithSimSPIFlashModel ++ /** add simulated SPI flash memory, if SPI is enabled */ + new chipyard.harness.WithSimAXIMMIO ++ /** add SimAXIMem for axi4 mmio port, if enabled */ + new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */ + new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */ + new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */ + new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */ + new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */ + new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */ + new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */ // ================================================ - // Set up I/O harness + // Set up I/O cells + punch I/Os in ChipTop // ================================================ // The IOBinders instantiate ChipTop IOs to match desired digital IOs // IOCells are generated for "Chip-like" IOs @@ -61,66 +61,71 @@ class AbstractConfig extends Config( // Set up External Memory and IO Devices // ================================================ // External memory section - new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ + new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */ testchipip.serdes.SerialTLParams( client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */ - width = 32 /** serial-tilelink interface with 32 lanes */ + width = 32 /** serial-tilelink interface with 32 lanes */ ) )) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 AXI-4 memory channels */ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ + + // MMIO device section - new chipyard.config.WithUART ++ /** add a UART */ - + new chipyard.config.WithUART ++ /** add a UART */ + // ================================================ - // Set up Debugging + // Set up Debug/Bringup/Testing Features // ================================================ // JTAG - new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */ - // new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++ - // new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++ + new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data word capacity */ new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */ // Boot Select Pins new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ - + // ================================================ // Set up Interrupts // ================================================ // CLINT and PLIC related settings goes here new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ - + // ================================================ // Set up Tiles // ================================================ - // core settings goes here - + // tile-local settings goes here // ================================================ // Set up Memory system // ================================================ // On-chip memory section - new chipyard.config.WithBootROM ++ /** use default bootrom */ - new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */ + new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS (embedded in BootROM) */ + new chipyard.config.WithBootROM ++ /** use default bootrom */ + new testchipip.soc.WithMbusScratchpad(base = 0x08000000, /** add 64 KiB on-chip scratchpad */ size = 64 * 1024) ++ - - // Cache settings - new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */ - new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */ - - // Memory Bus settings - new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */ + + // Coherency settings + new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence*/ + + // Bus/interconnect settings new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ // ================================================ // Set up power, reset and clocking // ================================================ - // clocking + + // ChipTop clock IO/PLL/Divider/Mux settings + new chipyard.clocking.WithPassthroughClockGenerator ++ + + // DigitalTop-internal clocking settings new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */ - new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ + new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */ + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", /** create a "uncore" clock group tieing all the bus clocks together */ + Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), + Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */ new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */ @@ -129,10 +134,8 @@ class AbstractConfig extends Config( new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */ new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */ new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */ - new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */ - new chipyard.clocking.WithPassthroughClockGenerator ++ - + // reset // power @@ -140,6 +143,5 @@ class AbstractConfig extends Config( // ================================== // Base Settings // ================================== - new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS */ new freechips.rocketchip.system.BaseConfig /** "base" rocketchip system */ ) From 4f3dd6067087b8bdeadc213bb4bf20320e53b5b9 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 25 Jan 2024 16:30:46 -0800 Subject: [PATCH 05/17] Enable debug SBA on all default designs --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 8a328daf..110be6e4 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -83,6 +83,7 @@ class AbstractConfig extends Config( new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model + new freechips.rocketchip.subsystem.WithDebugSBA ++ // enable the SBA (system-bus-access) feature of the debug module new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) From 74998229fbc12f79dbf878f5eeabe7fddd422ae1 Mon Sep 17 00:00:00 2001 From: "joonho.whangbo" Date: Mon, 5 Feb 2024 23:17:26 -0800 Subject: [PATCH 06/17] Add large boom cospike config --- generators/firechip/src/main/scala/TargetConfigs.scala | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 04bb26a4..6b41733d 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -360,3 +360,10 @@ class FireSimLeanGemminiRocketMMIOOnlyConfig extends Config( new WithDefaultMemModel ++ new WithFireSimConfigTweaks ++ new chipyard.LeanGemminiRocketConfig) + +class FireSimLargeBoomCospikeConfig extends Config( + new firesim.firesim.WithCospikeBridge ++ + new WithDefaultFireSimBridges ++ + new WithDefaultMemModel ++ + new WithFireSimConfigTweaks++ + new chipyard.LargeBoomConfig) From e33f9d8c5b115014b33a1c065ec53a416fd03fdc Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 7 Feb 2024 01:27:04 -0500 Subject: [PATCH 07/17] Switch update-circt action to v1 Change the version of the update-circt action from v1.0.0 to v1. This pulls in a change from v1.0.1 which fixes a bug where the staging branch was not updated. (I have no idea if this is being used.) However, this generally future-proofs the action by having it pull from v1 which is manually updated to match the latest v1 release (pulling in minor and patch changes). Signed-off-by: Schuyler Eldridge --- .github/workflows/update-circt.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/update-circt.yml b/.github/workflows/update-circt.yml index 2d52a155..f0c3158b 100644 --- a/.github/workflows/update-circt.yml +++ b/.github/workflows/update-circt.yml @@ -16,7 +16,7 @@ jobs: runs-on: ubuntu-latest steps: - name: Update CIRCT - uses: circt/update-circt@v1.0.0 + uses: circt/update-circt@v1 with: user: 'bartender' email: 'firesimchipyard@gmail.com' From b79590bb698a230c24e62ee320622ee36c3a7455 Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Sat, 10 Feb 2024 22:38:59 -0800 Subject: [PATCH 08/17] REFACTOR: fix spacing --- .../src/main/scala/config/AbstractConfig.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 9b10458c..751915e2 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -31,6 +31,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */ new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ /** generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz */ + // ================================================ // Set up I/O cells + punch I/Os in ChipTop // ================================================ @@ -58,6 +59,7 @@ class AbstractConfig extends Config( new chipyard.iobinders.WithUARTTSIPunchthrough ++ new chipyard.iobinders.WithNMITiedOff ++ + // ================================================ // Set up External Memory and IO Devices // ================================================ @@ -75,6 +77,7 @@ class AbstractConfig extends Config( // MMIO device section new chipyard.config.WithUART ++ /** add a UART */ + // ================================================ // Set up Debug/Bringup/Testing Features // ================================================ @@ -86,17 +89,20 @@ class AbstractConfig extends Config( new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */ new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */ + // ================================================ // Set up Interrupts // ================================================ // CLINT and PLIC related settings goes here new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */ + // ================================================ // Set up Tiles // ================================================ // tile-local settings goes here + // ================================================ // Set up Memory system // ================================================ @@ -107,11 +113,12 @@ class AbstractConfig extends Config( size = 64 * 1024) ++ // Coherency settings - new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence*/ + new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive LLC cache as root of coherence */ // Bus/interconnect settings new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */ + // ================================================ // Set up power, reset and clocking // ================================================ @@ -140,6 +147,7 @@ class AbstractConfig extends Config( // power + // ================================== // Base Settings // ================================== From 4642bffae7d0a384d03f937e764780a5eab8f4bd Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Sat, 10 Feb 2024 23:03:19 -0800 Subject: [PATCH 09/17] FIX: add missing chipid harness --- generators/chipyard/src/main/scala/config/AbstractConfig.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 751915e2..96d252f7 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -26,6 +26,7 @@ class AbstractConfig extends Config( new chipyard.harness.WithTieOffInterrupts ++ /** tie-off interrupt ports, if present */ new chipyard.harness.WithTieOffL2FBusAXI ++ /** tie-off external AXI4 master, if present */ new chipyard.harness.WithCustomBootPinPlusArg ++ /** drive custom-boot pin with a plusarg, if custom-boot-pin is present */ + new chipyard.harness.WithDriveChipIdPin ++ /** drive chip id pin from harness binder, if chip id pin is present */ new chipyard.harness.WithSimUARTToUARTTSI ++ /** connect a SimUART to the UART-TSI port */ new chipyard.harness.WithClockFromHarness ++ /** all Clock I/O in ChipTop should be driven by harnessClockInstantiator */ new chipyard.harness.WithResetFromHarness ++ /** reset controlled by harness */ @@ -147,7 +148,7 @@ class AbstractConfig extends Config( // power - + // ================================== // Base Settings // ================================== From 55e6dd67fd2d9b090ca97a21f2bb465efcf4382c Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Feb 2024 17:20:41 -0800 Subject: [PATCH 10/17] Add BINARY_ARGS to run-binary targets --- common.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index 26b488f5..a2c01046 100644 --- a/common.mk +++ b/common.mk @@ -371,14 +371,14 @@ run-binary: check-binary $(BINARY).run run-binaries: check-binaries $(addsuffix .run,$(BINARIES)) %.run: %.check-exists $(SIM_PREREQ) | $(output_dir) - (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) + (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* $(BINARY_ARGS) >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) # run simulator as fast as possible (no insn disassembly) run-binary-fast: check-binary $(BINARY).run.fast run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES)) %.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir) - (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* $(call get_sim_out_name,$*).dump ; fi - (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) + (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* $(BINARY_ARGS) >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) run-fast: run-asm-tests-fast run-bmark-tests-fast From f3c221ddfa5f6db10557cb06999182695067af0f Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Feb 2024 17:24:59 -0800 Subject: [PATCH 11/17] Split run-binary targets to be easier to read --- common.mk | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/common.mk b/common.mk index a2c01046..a0acba03 100644 --- a/common.mk +++ b/common.mk @@ -371,14 +371,27 @@ run-binary: check-binary $(BINARY).run run-binaries: check-binaries $(addsuffix .run,$(BINARIES)) %.run: %.check-exists $(SIM_PREREQ) | $(output_dir) - (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $* $(BINARY_ARGS) >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) + (set -o pipefail && $(NUMA_PREFIX) $(sim) \ + $(PERMISSIVE_ON) \ + $(call get_common_sim_flags,$*) \ + $(VERBOSE_FLAGS) \ + $(PERMISSIVE_OFF) \ + $* \ + $(BINARY_ARGS) \ + >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) # run simulator as fast as possible (no insn disassembly) run-binary-fast: check-binary $(BINARY).run.fast run-binaries-fast: check-binaries $(addsuffix .run.fast,$(BINARIES)) %.run.fast: %.check-exists $(SIM_PREREQ) | $(output_dir) - (set -o pipefail && $(NUMA_PREFIX) $(sim) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(PERMISSIVE_OFF) $* $(BINARY_ARGS) $(call get_sim_out_name,$*).dump ; fi - (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* $(BINARY_ARGS) >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) + (set -o pipefail && $(NUMA_PREFIX) $(sim_debug) \ + $(PERMISSIVE_ON) \ + $(call get_common_sim_flags,$*) \ + $(VERBOSE_FLAGS) \ + $(call get_waveform_flag,$(call get_sim_out_name,$*)) \ + $(PERMISSIVE_OFF) \ + $* \ + $(BINARY_ARGS) \ + >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log) run-fast: run-asm-tests-fast run-bmark-tests-fast From 66a0610c5a905ee57cf6476c119e90c6e2589809 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 13 Feb 2024 17:26:02 -0800 Subject: [PATCH 12/17] Add BINARY_ARGS help text --- variables.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/variables.mk b/variables.mk index 63519983..20154c24 100644 --- a/variables.mk +++ b/variables.mk @@ -27,6 +27,7 @@ HELP_SIMULATION_VARIABLES = \ " BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \ " BINARIES = list of riscv elf binary that the simulator will run when using the run-binaries* targets" \ " BINARIES_DIR = directory of riscv elf binaries that the simulator will run when using the run-binaries* targets" \ +" BINARY_ARGS = arguments to pass to each binary in run-binary targets (primarily meant for pk arguments)" \ " LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \ " LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \ " VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \ @@ -275,6 +276,7 @@ PERMISSIVE_ON=+permissive PERMISSIVE_OFF=+permissive-off BINARY ?= BINARIES ?= +BINARY_ARGS ?= override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES) VERBOSE_FLAGS ?= +verbose # get_out_name is a function, 1st argument is the binary From d1344d46b4b89581fb5ae580cf57d9fcf1c42e98 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 14 Feb 2024 00:52:02 -0800 Subject: [PATCH 13/17] Add example rocket-chip-blocks timer integration --- generators/chipyard/src/main/scala/DigitalTop.scala | 1 + .../src/main/scala/config/PeripheralDeviceConfigs.scala | 1 + .../main/scala/config/fragments/PeripheralFragments.scala | 5 +++++ generators/rocket-chip-blocks | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala index ec8ffd99..bd82585b 100644 --- a/generators/chipyard/src/main/scala/DigitalTop.scala +++ b/generators/chipyard/src/main/scala/DigitalTop.scala @@ -22,6 +22,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C + with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs diff --git a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala index 99400743..fa74d9b8 100644 --- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala +++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala @@ -75,6 +75,7 @@ class ManyPeripheralsRocketConfig extends Config( new testchipip.serdes.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only) new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice + new chipyard.config.WithPeripheryTimer ++ // add the pwm timer device new chipyard.config.WithSPIFlash ++ // add the SPI flash controller new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 51d31094..627e4a58 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -16,6 +16,7 @@ import sifive.blocks.devices.gpio._ import sifive.blocks.devices.uart._ import sifive.blocks.devices.spi._ import sifive.blocks.devices.i2c._ +import sifive.blocks.devices.timer._ import testchipip._ @@ -168,3 +169,7 @@ class WithNoBusErrorDevices extends Config((site, here, up) => { case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None) case FrontBusKey => up(FrontBusKey).copy(errorDevice = None) }) + +class WithPeripheryTimer(timerParams: TimerParams = TimerParams(0x4000)) extends Config((site, here, up) => { + case PeripheryTimerKey => Seq(timerParams) +}) diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index 3dddfe9f..340b7815 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit 3dddfe9f5bcacf28aebcadb71d5b57f4f6df7e07 +Subproject commit 340b78158c6aa022461f9a3bf5d838ec158b64c8 From 262469eeda71f587703bff8d5bdcb02f7bf470a7 Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Sun, 7 Jan 2024 16:03:12 -0800 Subject: [PATCH 14/17] Ensure all GPIO signals are tied off Resolves ucb-bar/chipyard#1731. --- generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 1 + generators/rocket-chip-blocks | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 64b1296e..80723b61 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -174,6 +174,7 @@ class WithGPIOCells extends OverrideIOBinder({ iocell.io.oe := pin.o.oe iocell.io.ie := pin.o.ie pin.i.ival := iocell.io.i + pin.i.po.foreach(_ := DontCare) iocell.io.pad <> g (GPIOPort(() => g, i, j), iocell) }).unzip diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks index 340b7815..f9263535 160000 --- a/generators/rocket-chip-blocks +++ b/generators/rocket-chip-blocks @@ -1 +1 @@ -Subproject commit 340b78158c6aa022461f9a3bf5d838ec158b64c8 +Subproject commit f9263535be1988778f1baf98c18221dee1db1a47 From 80609c97c9b40d6aeb38550bc67d1c025428dfa3 Mon Sep 17 00:00:00 2001 From: Lucheng Zhang Date: Thu, 22 Feb 2024 14:16:57 -0800 Subject: [PATCH 15/17] doc: Update FireSim docs --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 4 ++-- docs/Simulation/FPGA-Accelerated-Simulation.rst | 10 +++++++--- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 948b7e2e..1f348189 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -15,8 +15,8 @@ Running on AWS EC2 with FireSim ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ If you plan on using Chipyard alongside FireSim on AWS EC2 instances, you should refer to the :fsim_doc:`FireSim documentation <>`. -Specifically, you should follow the :fsim_doc:`Initial Setup/Installation ` -section of the docs up until :fsim_doc:`Setting up the FireSim Repo `. +Specifically, you should follow the :fsim_doc:`Initial Setup/Installation ` +section of the docs up until :fsim_doc:`Setting up the FireSim Repo `. At that point, instead of cloning FireSim you can clone Chipyard by following :ref:`Chipyard-Basics/Initial-Repo-Setup:Setting up the Chipyard Repo`. Default Requirements Installation diff --git a/docs/Simulation/FPGA-Accelerated-Simulation.rst b/docs/Simulation/FPGA-Accelerated-Simulation.rst index 0e126252..01585c59 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulation.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulation.rst @@ -26,12 +26,14 @@ Finally, source the following environment at the root of the FireSim directory: cd sims/firesim # (Recommended) The default manager environment (includes env.sh) - source sourceme-manager.sh + source sourceme-manager.sh` + # Completing setup using the manager + firesim managerinit --platform f1 .. Note:: Every time you want to use FireSim with a fresh shell, you must source ``sourceme-manager.sh`` At this point you're ready to use FireSim with Chipyard. If you're not already -familiar with FireSim, please return to the :fsim_doc:`FireSim Docs `, +familiar with FireSim, please return to the :fsim_doc:`FireSim Docs `, and proceed with the rest of the tutorial. Running your Design in FireSim @@ -47,7 +49,7 @@ A FireSim simulation requires 3 additional config fragments: The simplest method to add this config fragments to your custom Chipyard config is through FireSim's build recipe scheme. -After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/deploy/config_build_recipes.ini``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. +After your FireSim environment is setup, you will define your custom build recipe in ``sims/firesim/deploy/config_build_recipes.yaml``. By prepending the FireSim config fragments (separated by ``_``) to your Chipyard configuration, these config fragments will be added to your custom configuration as if they were listed in a custom Chisel config class definition. For example, if you would like to convert the Chipyard ``LargeBoomConfig`` to a FireSim simulation with a DDR3 memory model, the appropriate FireSim ``TARGET_CONFIG`` would be ``DDR3FRFCFSLLC4MB_WithDefaultFireSimBridges_WithFireSimConfigTweaks_chipyard.LargeBoomConfig``. Note that the FireSim config fragments are part of the ``firesim.firesim`` scala package and therefore there do not need to be prefixed with the full package name as opposed to the Chipyard config fragments which need to be prefixed with the chipyard package name. An alternative method to prepending the FireSim config fragments in the FireSim build recipe is to create a new "permanent" FireChip custom configuration, which includes the FireSim config fragments. We are using the same target (top) RTL, and only need to specify a new set of connection behaviors for the IOs of that module. Simply create a matching config within ``generators/firechip/src/main/scala/TargetConfigs`` that inherits your config defined in ``chipyard``. @@ -59,3 +61,5 @@ We are using the same target (top) RTL, and only need to specify a new set of co :end-before: DOC include end: firesimconfig While this option seems to require the maintenance of additional configuration code, it has the benefit of allowing for the inclusion of more complex config fragments which also accept custom arguments (for example, ``WithDefaultMemModel`` can take an optional argument``) + +For more information on how to build your own hardware design on FireSim, please refer to :fsim_doc:`FireSim Docs `. From 4c9bcfc123a132e768a251f344aa8cb6ff4229bf Mon Sep 17 00:00:00 2001 From: Sungkeun Kim Date: Fri, 23 Feb 2024 16:04:28 +0900 Subject: [PATCH 16/17] Enabling JTAG Debuging in VCU118 FPGA --- fpga/src/main/scala/vcu118/Configs.scala | 2 +- fpga/src/main/scala/vcu118/HarnessBinders.scala | 14 ++++++++++++++ fpga/src/main/scala/vcu118/TestHarness.scala | 3 +++ 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index ff46deee..49355284 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -54,11 +54,11 @@ class WithVCU118Tweaks extends Config( new WithUART ++ new WithSPISDCard ++ new WithDDRMem ++ + new WithJTAG ++ // other configuration new WithDefaultPeripherals ++ new chipyard.config.WithTLBackingMemory ++ // use TL backing memory new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size - new chipyard.config.WithNoDebug ++ // remove debug module new freechips.rocketchip.subsystem.WithoutTLMonitors ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ) diff --git a/fpga/src/main/scala/vcu118/HarnessBinders.scala b/fpga/src/main/scala/vcu118/HarnessBinders.scala index c03f551f..a4b52c63 100644 --- a/fpga/src/main/scala/vcu118/HarnessBinders.scala +++ b/fpga/src/main/scala/vcu118/HarnessBinders.scala @@ -36,3 +36,17 @@ class WithDDRMem extends HarnessBinder({ ddrClientBundle <> port.io } }) + +class WithJTAG extends HarnessBinder({ + case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => { + val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue + port.io.TCK := jtag_io.TCK + port.io.TMS := jtag_io.TMS + port.io.TDI := jtag_io.TDI + jtag_io.TDO.data := port.io.TDO + jtag_io.TDO.driven := true.B + // ignore srst_n + jtag_io.srst_n := DontCare + + } +}) diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 78dee3e6..b707d144 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -85,6 +85,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S ))))) ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient + /*** JTAG ***/ + val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput()) + // module implementation override lazy val module = new VCU118FPGATestHarnessImp(this) } From b260078ae49460f341146be4872838cf797b3a13 Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Fri, 23 Feb 2024 15:30:15 -0800 Subject: [PATCH 17/17] Fix invalid escape sequences In Python 3.12, these show up as SyntaxWarning messages. --- scripts/uniquify-module-names.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py index 0ddea49f..d2131c33 100755 --- a/scripts/uniquify-module-names.py +++ b/scripts/uniquify-module-names.py @@ -110,7 +110,7 @@ def generate_copy(c, sfx): new_file = os.path.join(args.gcpath, new_file) shutil.copy(cur_file, new_file) - bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}") + bash(rf"{SED} -i 's/module\( \+\){cur_name}/module\1{new_name}/' {new_file}") return new_file def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename): @@ -137,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename): new_file = generate_copy(cur_file, MODEL_SFX) if parent is not None and ((parent, mod) not in updated_submodule): parent_file = os.path.join(args.gcpath, verilog_module_filename[parent]) - bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}") + bash(rf"{SED} -i 's/\( \*\){mod}\( \+\)/\1{mod}_{MODEL_SFX}\2/' {parent_file}") updated_submodule.add((parent, mod)) # add the uniquified module to the verilog_modul_filename dict