From 477456bc0b2dd4342a51808448cfc5837aebc4da Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Tue, 14 Mar 2023 20:25:28 -0700
Subject: [PATCH] Add custom chiptop+iocell example

---
 .../src/main/scala/config/RocketConfigs.scala |  6 ++
 .../main/scala/example/CustomChipTop.scala    | 64 +++++++++++++++++++
 2 files changed, 70 insertions(+)
 create mode 100644 generators/chipyard/src/main/scala/example/CustomChipTop.scala

diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index b6677cb1..dcd15b46 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -126,3 +126,9 @@ class MulticlockAXIOverSerialConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(2) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: MulticlockAXIOverSerialConfig
+
+class CustomIOChipTopRocketConfig extends Config(
+  new chipyard.example.WithCustomChipTop ++
+  new chipyard.example.WithCustomIOCells ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/example/CustomChipTop.scala b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
new file mode 100644
index 00000000..19be7d5b
--- /dev/null
+++ b/generators/chipyard/src/main/scala/example/CustomChipTop.scala
@@ -0,0 +1,64 @@
+package chipyard.example
+
+import chisel3._
+import chipyard.iobinders._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy.{InModuleBody}
+import barstools.iocell.chisel._
+import chipyard._
+
+// A "custom" IOCell with additional I/O
+// The IO don't do anything here in this example
+class CustomDigitalInIOCellBundle extends DigitalInIOCellBundle {
+  val custom_out = Output(Bool())
+  val custom_in = Input(Bool())
+}
+
+// Using a custom digital in iocell instead of the default one
+class CustomDigitalInIOCell extends RawModule with DigitalInIOCell {
+  val io = IO(new CustomDigitalInIOCellBundle)
+  io.i := io.pad
+  io.custom_out := io.pad
+}
+
+case class CustomIOCellParams() extends IOCellTypeParams {
+  def analog() = Module(new GenericAnalogIOCell)
+  def gpio() = Module(new GenericDigitalGPIOCell)
+  def input() = Module(new CustomDigitalInIOCell)
+  def output() = Module(new GenericDigitalOutIOCell)
+}
+
+class CustomChipTop(implicit p: Parameters) extends ChipTop {
+  // making the module name ChipTop instead of CustomChipTop means
+  // we don't have to set the TOP make variable to CustomChipTop
+  override lazy val desiredName = "ChipTop"
+
+  // InModuleBody blocks are executed within the LazyModuleImp of this block
+  InModuleBody {
+    iocellMap.foreach { case (interface, cells) => {
+      cells.foreach { _ match {
+        case c: CustomDigitalInIOCell => {
+          c.io.custom_in := false.B
+        }
+        case c: GenericDigitalOutIOCell => {
+          // do nothing
+        }
+        case c => {
+          require(false, "Unsupported iocell type ${c.getClass}")
+        }
+      }}
+    }}
+
+    // demonstrate accessing the iocellMap directly
+    val serialTLIOCells = iocellMap("interface testchipip.CanHavePeripheryTLSerial")
+  }
+}
+
+class WithCustomIOCells extends Config((site, here, up) => {
+  case IOCellKey => CustomIOCellParams()
+})
+
+class WithCustomChipTop extends Config((site, here, up) => {
+  case BuildTop => (p: Parameters) => new CustomChipTop()(p)
+})