diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala
index ac0f25d0..bac6862c 100644
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -3,6 +3,7 @@ package barstools.macros
 import firrtl.ir.{Circuit, NoInfo}
 import firrtl.passes.RemoveEmpty
 import firrtl.Parser.parse
+import firrtl.Utils.ceilLog2
 import java.io.{File, StringWriter}
 
 // TODO: we should think of a less brittle way to run these tests.
@@ -157,6 +158,107 @@ trait HasSRAMGenerator {
   }
 }
 
+// Generic "simple" test generator.
+// Set up scaffolding for generating memories, files, etc.
+// Override this generator to specify the expected FIRRTL output.
+trait HasSimpleTestGenerator {
+  this: MacroCompilerSpec with HasSRAMGenerator =>
+    // Override these with "override lazy val".
+    // Why lazy? These are used in the constructor here so overriding non-lazily
+    // would be too late.
+    def memWidth: Int
+    def libWidth: Int
+    def memDepth: Int
+    def libDepth: Int
+    def memMaskGran: Option[Int] = None
+    def libMaskGran: Option[Int] = None
+    def extraPorts: Seq[mdf.macrolib.MacroExtraPort] = List()
+    def extraTag: String = ""
+
+    // Override this in the sub-generator if you need a more specific name.
+    // Defaults to using reflection to pull the name of the test using this
+    // generator.
+    def generatorType: String = this.getClass.getSimpleName
+
+    require (memDepth >= libDepth)
+
+    override val memPrefix = testDir
+    override val libPrefix = testDir
+
+    // Convenience variables to check if a mask exists.
+    val memHasMask = memMaskGran != None
+    val libHasMask = libMaskGran != None
+    // We need to figure out how many mask bits there are in the mem.
+    val memMaskBits = if (memHasMask) memWidth / memMaskGran.get else 0
+    val libMaskBits = if (libHasMask) libWidth / libMaskGran.get else 0
+
+    val extraTagPrefixed = if (extraTag == "") "" else ("-" + extraTag)
+
+    val mem = s"mem-${generatorType}${extraTagPrefixed}.json"
+    val lib = s"lib-${generatorType}${extraTagPrefixed}.json"
+    val v = s"${generatorType}${extraTagPrefixed}.v"
+
+    val mem_name = "target_memory"
+    val mem_addr_width = ceilLog2(memDepth)
+
+    val lib_name = "awesome_lib_mem"
+    val lib_addr_width = ceilLog2(libDepth)
+
+    writeToLib(lib, Seq(generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts)))
+    writeToMem(mem, Seq(generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran)))
+
+    // Number of lib instances needed to hold the mem.
+    // Round up (e.g. 1.5 instances = effectively 2 instances)
+    val expectedInstances = math.ceil(memDepth.toFloat / libDepth).toInt
+    val selectBits = mem_addr_width - lib_addr_width
+
+    // Generate the header (contains the circuit statement and the target memory
+    // module.
+    def generateHeader(): String = {
+      val headerMask = if (memHasMask) s"input outer_mask : UInt<${memMaskBits}>" else ""
+      s"""
+circuit $mem_name :
+  module $mem_name :
+    input outer_clk : Clock
+    input outer_addr : UInt<$mem_addr_width>
+    input outer_din : UInt<$memWidth>
+    output outer_dout : UInt<$memWidth>
+    input outer_write_en : UInt<1>
+    ${headerMask}
+  """
+    }
+
+    // Generate the footer (contains the target memory extmodule).
+    def generateFooter(): String = {
+      val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else ""
+      s"""
+  extmodule $lib_name :
+    input lib_clk : Clock
+    input lib_addr : UInt<$lib_addr_width>
+    input lib_din : UInt<$libWidth>
+    output lib_dout : UInt<$libWidth>
+    input lib_write_en : UInt<1>
+    ${footerMask}
+
+    defname = $lib_name
+  """
+    }
+
+    // Abstract method to generate body; to be overridden by specific generator type.
+    def generateBody(): String
+
+    // Generate the entire output from header, body, and footer.
+    def generateOutput(): String = {
+      s"""
+${generateHeader}
+${generateBody}
+${generateFooter}
+      """
+    }
+
+    val output = generateOutput()
+}
+
 //~ class RocketChipTest extends MacroCompilerSpec {
   //~ val mem = new File(macroDir, "rocketchip.json")
   //~ val lib = new File(macroDir, "mylib.json")
diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala
index f633364a..03542104 100644
--- a/macros/src/test/scala/SimpleSplitDepth.scala
+++ b/macros/src/test/scala/SimpleSplitDepth.scala
@@ -1,118 +1,53 @@
 package barstools.macros
 
-import firrtl.Utils.ceilLog2
 import mdf.macrolib._
 
 // Test the depth splitting aspect of the memory compiler.
 // This file is for simple tests: one read-write port, powers of two sizes, etc.
 // For example, implementing a 4096x32 memory using four 1024x32 memories.
 
-trait HasSimpleDepthTestGenerator {
+trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
   this: MacroCompilerSpec with HasSRAMGenerator =>
-    // Override these with "override lazy val".
-    // Why lazy? These are used in the constructor here so overriding non-lazily
-    // would be too late.
     def width: Int
-    def mem_depth: Int
-    def lib_depth: Int
-    def mem_maskGran: Option[Int] = None
-    def lib_maskGran: Option[Int] = None
-    def extraPorts: Seq[mdf.macrolib.MacroExtraPort] = List()
-    def extraTag: String = ""
 
-    require (mem_depth >= lib_depth)
+    override lazy val memWidth = width
+    override lazy val libWidth = width
 
-    override val memPrefix = testDir
-    override val libPrefix = testDir
+    // Generate a depth-splitting body.
+    override def generateBody(): String = {
+      var output = ""
 
-    // Convenience variables to check if a mask exists.
-    val memHasMask = mem_maskGran != None
-    val libHasMask = lib_maskGran != None
-    // We need to figure out how many mask bits there are in the mem.
-    val memMaskBits = if (memHasMask) width / mem_maskGran.get else 0
-    val libMaskBits = if (libHasMask) width / lib_maskGran.get else 0
-    // Generate "mrw" vs "rw" tags.
-    val memTag = (if (memHasMask) "m" else "") + "rw" + (if (mem_maskGran.nonEmpty) s"_gran${mem_maskGran.get}" else "")
-    val libTag = (if (libHasMask) "m" else "") + "rw" + (if (lib_maskGran.nonEmpty) s"_gran${lib_maskGran.get}" else "")
-
-    val extraTagPrefixed = if (extraTag == "") "" else ("-" + extraTag)
-
-    val mem = s"mem-${mem_depth}x${width}-${memTag}${extraTagPrefixed}.json"
-    val lib = s"lib-${lib_depth}x${width}-${libTag}${extraTagPrefixed}.json"
-    val v = s"split_depth_${mem_depth}x${width}_${memTag}${extraTagPrefixed}.v"
-
-    val mem_name = "target_memory"
-    val mem_addr_width = ceilLog2(mem_depth)
-
-    val lib_name = "awesome_lib_mem"
-    val lib_addr_width = ceilLog2(lib_depth)
-
-    writeToLib(lib, Seq(generateSRAM(lib_name, "lib", width, lib_depth, lib_maskGran, extraPorts)))
-    writeToMem(mem, Seq(generateSRAM(mem_name, "outer", width, mem_depth, mem_maskGran)))
-
-    // Number of lib instances needed to hold the mem.
-    // Round up (e.g. 1.5 instances = effectively 2 instances)
-    val expectedInstances = math.ceil(mem_depth.toFloat / lib_depth).toInt
-    val selectBits = mem_addr_width - lib_addr_width
-
-    val headerMask = if (memHasMask) s"input outer_mask : UInt<${memMaskBits}>" else ""
-    val header = s"""
-circuit $mem_name :
-  module $mem_name :
-    input outer_clk : Clock
-    input outer_addr : UInt<$mem_addr_width>
-    input outer_din : UInt<$width>
-    output outer_dout : UInt<$width>
-    input outer_write_en : UInt<1>
-    ${headerMask}
-"""
-
-    val footerMask = if (libHasMask) s"input lib_mask : UInt<${libMaskBits}>" else ""
-    val footer = s"""
-  extmodule $lib_name :
-    input lib_clk : Clock
-    input lib_addr : UInt<$lib_addr_width>
-    input lib_din : UInt<$width>
-    output lib_dout : UInt<$width>
-    input lib_write_en : UInt<1>
-    ${footerMask}
-
-    defname = $lib_name
-"""
-
-    var output = header
-
-    if (selectBits > 0) {
-      output +=
-s"""
+      if (selectBits > 0) {
+        output +=
+  s"""
     node outer_addr_sel = bits(outer_addr, ${mem_addr_width - 1}, $lib_addr_width)
-"""
-    }
+  """
+      }
 
-    for (i <- 0 to expectedInstances - 1) {
-      // We only support simple masks for now (either libMask == memMask or libMask == 1)
-      val maskStatement = if (libHasMask) {
-        if (lib_maskGran.get == mem_maskGran.get) {
-          s"""mem_${i}_0.lib_mask <= bits(outer_mask, 0, 0)"""
-        } else if (lib_maskGran.get == 1) {
-          // Construct a mask string.
-          // Each bit gets the # of bits specified in maskGran.
-          // Specify in descending order (MSB first)
+      for (i <- 0 to expectedInstances - 1) {
+        // We only support simple masks for now (either libMask == memMask or libMask == 1)
+        val maskStatement = if (libHasMask) {
+          if (libMaskGran.get == memMaskGran.get) {
+            s"""mem_${i}_0.lib_mask <= bits(outer_mask, 0, 0)"""
+          } else if (libMaskGran.get == 1) {
+            // Construct a mask string.
+            // Each bit gets the # of bits specified in maskGran.
+            // Specify in descending order (MSB first)
 
-          // This builds an array like m[1], m[1], m[0], m[0]
-          val maskBitsArr: Seq[String] = ((memMaskBits - 1 to 0 by -1) flatMap (maskBit => {
-            ((0 to mem_maskGran.get - 1) map (_ => s"bits(outer_mask, ${maskBit}, ${maskBit})"))
-          }))
-          // Now build it into a recursive string like
-          // cat(m[1], cat(m[1], cat(m[0], m[0])))
-          val maskBitsStr: String = maskBitsArr.reverse.tail.foldLeft(maskBitsArr.reverse.head)((prev: String, next: String) => s"cat(${next}, ${prev})")
-          s"""mem_${i}_0.lib_mask <= ${maskBitsStr}"""
-        } else "" // TODO: implement when non-bitmasked memories are supported
-      } else "" // No mask
+            // This builds an array like m[1], m[1], m[0], m[0]
+            val maskBitsArr: Seq[String] = ((memMaskBits - 1 to 0 by -1) flatMap (maskBit => {
+              ((0 to memMaskGran.get - 1) map (_ => s"bits(outer_mask, ${maskBit}, ${maskBit})"))
+            }))
+            // Now build it into a recursive string like
+            // cat(m[1], cat(m[1], cat(m[0], m[0])))
+            val maskBitsStr: String = maskBitsArr.reverse.tail.foldLeft(maskBitsArr.reverse.head)((prev: String, next: String) => s"cat(${next}, ${prev})")
+            s"""mem_${i}_0.lib_mask <= ${maskBitsStr}"""
+          } else "" // TODO: implement when non-bitmasked memories are supported
+        } else "" // No mask
 
-      val enableIdentifier = if (selectBits > 0) s"""eq(outer_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))""" else "UInt<1>(\"h1\")"
-      output +=
-s"""
+        val enableIdentifier = if (selectBits > 0) s"""eq(outer_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))""" else "UInt<1>(\"h1\")"
+        output +=
+  s"""
     inst mem_${i}_0 of awesome_lib_mem
     mem_${i}_0.lib_clk <= outer_clk
     mem_${i}_0.lib_addr <= outer_addr
@@ -121,32 +56,33 @@ s"""
     ${maskStatement}
     mem_${i}_0.lib_write_en <= and(and(outer_write_en, UInt<1>("h1")), ${enableIdentifier})
     node outer_dout_${i} = outer_dout_${i}_0
-"""
-    }
-    def generate_outer_dout_tree(i:Int, expectedInstances: Int): String = {
-      if (i > expectedInstances - 1) {
-        "UInt<1>(\"h0\")"
-      } else {
-        "mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format(
-          selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, expectedInstances)
-        )
+  """
+      }
+      def generate_outer_dout_tree(i:Int, expectedInstances: Int): String = {
+        if (i > expectedInstances - 1) {
+          "UInt<1>(\"h0\")"
+        } else {
+          "mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format(
+            selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, expectedInstances)
+          )
+        }
+      }
+      output += "  outer_dout <= "
+      if (selectBits > 0) {
+        output += generate_outer_dout_tree(0, expectedInstances)
+      } else {
+        output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))"""
       }
-    }
-    output += "    outer_dout <= "
-    if (selectBits > 0) {
-      output += generate_outer_dout_tree(0, expectedInstances)
-    } else {
-      output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))"""
-    }
 
-    output += footer
+      return output
+    }
 }
 
 // Try different widths
 class SplitDepth4096x32_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 4096
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 4096
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -154,8 +90,8 @@ class SplitDepth4096x32_rw extends MacroCompilerSpec with HasSRAMGenerator with
 
 class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 16
-  override lazy val mem_depth = 4096
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 4096
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -163,8 +99,8 @@ class SplitDepth4096x16_rw extends MacroCompilerSpec with HasSRAMGenerator with
 
 class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 32768
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 32768
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -172,8 +108,8 @@ class SplitDepth32768x8_rw extends MacroCompilerSpec with HasSRAMGenerator with
 
 class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 4096
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 4096
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -181,8 +117,8 @@ class SplitDepth4096x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
 
 class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -190,8 +126,8 @@ class SplitDepth2048x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
 
 class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 1024
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 1024
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -200,8 +136,8 @@ class SplitDepth1024x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
 // Non power of two
 class SplitDepth2000x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 2000
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 2000
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -209,8 +145,8 @@ class SplitDepth2000x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
 
 class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 2049
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 2049
+  override lazy val libDepth = 1024
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -221,10 +157,10 @@ class SplitDepth2049x8_rw extends MacroCompilerSpec with HasSRAMGenerator with H
 // Test for mem mask == lib mask (i.e. mask is a write enable bit)
 class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(32)
-  override lazy val lib_maskGran = Some(32)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(32)
+  override lazy val libMaskGran = Some(32)
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -232,10 +168,10 @@ class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerato
 
 class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 8
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(8)
-  override lazy val lib_maskGran = Some(8)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(8)
+  override lazy val libMaskGran = Some(8)
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -244,10 +180,10 @@ class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator
 // Non-bit level mask
 class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 64
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(32)
-  override lazy val lib_maskGran = Some(8)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(32)
+  override lazy val libMaskGran = Some(8)
 
   it should "be enabled when non-bitmasked memories are supported" is (pending)
   //compile(mem, lib, v, false)
@@ -257,10 +193,10 @@ class SplitDepth2048x64_mrw_mem32_lib8 extends MacroCompilerSpec with HasSRAMGen
 // Bit level mask
 class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(16)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(16)
+  override lazy val libMaskGran = Some(1)
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -268,10 +204,10 @@ class SplitDepth2048x32_mrw_mem16_lib1 extends MacroCompilerSpec with HasSRAMGen
 
 class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(8)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(8)
+  override lazy val libMaskGran = Some(1)
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -279,10 +215,10 @@ class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGene
 
 class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(4)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(4)
+  override lazy val libMaskGran = Some(1)
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -290,10 +226,10 @@ class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGene
 
 class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(2)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(2)
+  override lazy val libMaskGran = Some(1)
 
   compile(mem, lib, v, false)
   execute(mem, lib, false, output)
@@ -302,10 +238,10 @@ class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGene
 // Non-powers of 2 mask sizes
 class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(3)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(3)
+  override lazy val libMaskGran = Some(1)
 
   it should "be enabled when non-power of two masks are supported" is (pending)
   //compile(mem, lib, v, false)
@@ -314,10 +250,10 @@ class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGene
 
 class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(7)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(7)
+  override lazy val libMaskGran = Some(1)
 
   it should "be enabled when non-power of two masks are supported" is (pending)
   //compile(mem, lib, v, false)
@@ -326,10 +262,10 @@ class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGene
 
 class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleDepthTestGenerator {
   override lazy val width = 32
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
-  override lazy val mem_maskGran = Some(9)
-  override lazy val lib_maskGran = Some(1)
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
+  override lazy val memMaskGran = Some(9)
+  override lazy val libMaskGran = Some(1)
 
   it should "be enabled when non-power of two masks are supported" is (pending)
   //compile(mem, lib, v, false)
@@ -341,14 +277,14 @@ class SplitDepth2048x8_extraPort extends MacroCompilerSpec with HasSRAMGenerator
   import mdf.macrolib._
 
   override lazy val width = 8
-  override lazy val mem_depth = 2048
-  override lazy val lib_depth = 1024
+  override lazy val memDepth = 2048
+  override lazy val libDepth = 1024
   override lazy val extraPorts = List(
     MacroExtraPort(name="extra_port", width=8, portType=Constant, value=0xff)
   )
   override lazy val extraTag = "extraPort"
 
-  val outputCustom =
+  override def generateOutput(): String =
 """
 circuit target_memory :
   module target_memory :
@@ -390,15 +326,16 @@ circuit target_memory :
 
     defname = awesome_lib_mem
   """
+
   compile(mem, lib, v, false)
-  execute(mem, lib, false, outputCustom)
+  execute(mem, lib, false, output)
 }
 
 // Split read and (non-masked) write ports (r+w).
 class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGenerator {
   lazy val width = 8
-  lazy val mem_depth = 2048
-  lazy val lib_depth = 1024
+  lazy val memDepth = 2048
+  lazy val libDepth = 1024
 
   override val memPrefix = testDir
   override val libPrefix = testDir
@@ -414,11 +351,11 @@ class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGener
       macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
-      depth=lib_depth,
+      depth=libDepth,
       family="1r1w",
       ports=Seq(
-        generateReadPort("innerA", width, lib_depth),
-        generateWritePort("innerB", width, lib_depth)
+        generateReadPort("innerA", width, libDepth),
+        generateWritePort("innerB", width, libDepth)
       )
     )
 
@@ -426,11 +363,11 @@ class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGener
       macroType=SRAM,
       name="target_memory",
       width=width,
-      depth=mem_depth,
+      depth=memDepth,
       family="1r1w",
       ports=Seq(
-        generateReadPort("outerB", width, mem_depth),
-        generateWritePort("outerA", width, mem_depth)
+        generateReadPort("outerB", width, memDepth),
+        generateWritePort("outerA", width, memDepth)
       )
     )
 
@@ -501,16 +438,16 @@ circuit target_memory :
       macroType=SRAM,
       name="target_memory",
       width=width,
-      depth=mem_depth,
+      depth=memDepth,
       family="1r1w",
       ports=Seq(
-        generateReadPort("outerB", width, mem_depth),
-        generateWritePort("outerA", width, mem_depth)
+        generateReadPort("outerB", width, memDepth),
+        generateWritePort("outerA", width, memDepth)
       )
     )
 
     writeToLib(mem, Seq(memMacro))
-    writeToLib(lib, Seq(generateSRAM("awesome_lib_mem", "lib", width, lib_depth)))
+    writeToLib(lib, Seq(generateSRAM("awesome_lib_mem", "lib", width, libDepth)))
 
     val output =
 """
@@ -536,15 +473,15 @@ TODO
       macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
-      depth=lib_depth,
+      depth=libDepth,
       family="1rw",
       ports=Seq(
-        generateReadPort("innerA", width, lib_depth),
-        generateWritePort("innerB", width, lib_depth)
+        generateReadPort("innerA", width, libDepth),
+        generateWritePort("innerB", width, libDepth)
       )
     )
 
-    writeToLib(mem, Seq(generateSRAM("target_memory", "outer", width, mem_depth)))
+    writeToLib(mem, Seq(generateSRAM("target_memory", "outer", width, memDepth)))
     writeToLib(lib, Seq(libMacro))
 
     val output =
@@ -560,10 +497,10 @@ TODO
 // Split read and (masked) write ports (r+mw).
 class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerator {
   lazy val width = 8
-  lazy val mem_depth = 2048
-  lazy val lib_depth = 1024
-  lazy val mem_maskGran = Some(8)
-  lazy val lib_maskGran = Some(1)
+  lazy val memDepth = 2048
+  lazy val libDepth = 1024
+  lazy val memMaskGran = Some(8)
+  lazy val libMaskGran = Some(1)
 
   override val memPrefix = testDir
   override val libPrefix = testDir
@@ -579,11 +516,11 @@ class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerato
       macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
-      depth=lib_depth,
+      depth=libDepth,
       family="1r1w",
       ports=Seq(
-        generateReadPort("innerA", width, lib_depth),
-        generateWritePort("innerB", width, lib_depth, lib_maskGran)
+        generateReadPort("innerA", width, libDepth),
+        generateWritePort("innerB", width, libDepth, libMaskGran)
       )
     )
 
@@ -591,11 +528,11 @@ class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerato
       macroType=SRAM,
       name="target_memory",
       width=width,
-      depth=mem_depth,
+      depth=memDepth,
       family="1r1w",
       ports=Seq(
-        generateReadPort("outerB", width, mem_depth),
-        generateWritePort("outerA", width, mem_depth, mem_maskGran)
+        generateReadPort("outerB", width, memDepth),
+        generateWritePort("outerA", width, memDepth, memMaskGran)
       )
     )
 
@@ -670,16 +607,16 @@ circuit target_memory :
       macroType=SRAM,
       name="target_memory",
       width=width,
-      depth=mem_depth,
+      depth=memDepth,
       family="1r1w",
       ports=Seq(
-        generateReadPort("outerB", width, mem_depth),
-        generateWritePort("outerA", width, mem_depth, mem_maskGran)
+        generateReadPort("outerB", width, memDepth),
+        generateWritePort("outerA", width, memDepth, memMaskGran)
       )
     )
 
     writeToLib(mem, Seq(memMacro))
-    writeToLib(lib, Seq(generateSRAM("awesome_lib_mem", "lib", width, lib_depth, lib_maskGran)))
+    writeToLib(lib, Seq(generateSRAM("awesome_lib_mem", "lib", width, libDepth, libMaskGran)))
 
     val output =
 """
@@ -705,15 +642,15 @@ TODO
       macroType=SRAM,
       name="awesome_lib_mem",
       width=width,
-      depth=lib_depth,
+      depth=libDepth,
       family="1rw",
       ports=Seq(
-        generateReadPort("innerA", width, lib_depth),
-        generateWritePort("innerB", width, lib_depth, lib_maskGran)
+        generateReadPort("innerA", width, libDepth),
+        generateWritePort("innerB", width, libDepth, libMaskGran)
       )
     )
 
-    writeToLib(mem, Seq(generateSRAM("target_memory", "outer", width, mem_depth, mem_maskGran)))
+    writeToLib(mem, Seq(generateSRAM("target_memory", "outer", width, memDepth, memMaskGran)))
     writeToLib(lib, Seq(libMacro))
 
     val output =