From 48539353b03441154d40ecd73e8c2a012f97434a Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 1 Feb 2023 23:19:43 -0800 Subject: [PATCH] Makefile fixes, but sim still doesn't work --- docs/Chipyard-Basics/Initial-Repo-Setup.rst | 4 ++ .../init-submodules-no-riscv-tools-nolog.sh | 1 - vlsi/Makefile | 53 ++++++------------- vlsi/example-tools.yml | 7 +-- vlsi/tutorial.mk | 2 +- 5 files changed, 23 insertions(+), 44 deletions(-) diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst index 6543afc2..87639f87 100644 --- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst +++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst @@ -49,6 +49,8 @@ This is done by the following: conda install -n base conda-lock conda activate base +.. Note:: We also recommended switching to `libmamba `__ for much faster dependency solving. + Setting up the Chipyard Repo ------------------------------------------- @@ -101,6 +103,8 @@ This file activates the conda environment created in ``build-setup.sh`` and sets Once the script is run, the ``PATH``, ``RISCV``, and ``LD_LIBRARY_PATH`` environment variables will be set properly for the toolchain requested. You can source this file in your ``.bashrc`` or equivalent environment setup file to get the proper variables, or directly include it in your current environment: +.. Note:: If you are on a Mac or a RHEL/CentOS-based Linux distribution, you must deactivate the base conda environment with ``conda deactivate`` first before proceeding. You may also choose to keep it deactivated by default with ``conda config --set auto_activate_base false``. See this `issue `__ for more details. + .. code-block:: shell source ./env.sh diff --git a/scripts/init-submodules-no-riscv-tools-nolog.sh b/scripts/init-submodules-no-riscv-tools-nolog.sh index 19eaeb8c..2635e059 100755 --- a/scripts/init-submodules-no-riscv-tools-nolog.sh +++ b/scripts/init-submodules-no-riscv-tools-nolog.sh @@ -150,6 +150,5 @@ fi cat << EOT >> env.sh # line auto-generated by init-submodules-no-riscv-tools.sh __DIR="$RDIR" -PATH=\$__DIR/bin:\$PATH PATH=\$__DIR/software/firemarshal:\$PATH EOT diff --git a/vlsi/Makefile b/vlsi/Makefile index 3e5637d4..1f7f82bb 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -8,6 +8,7 @@ base_dir=$(abspath ..) vlsi_dir=$(abspath .) sim_dir=$(abspath .) +site_packages_dir=$(shell python3 -c "import site; print(site.getsitepackages()[0])") ######################################################################################### # include shared variables @@ -21,7 +22,7 @@ include $(base_dir)/variables.mk sim_name ?= vcs # needed for GenerateSimFiles, but is unused tech_name ?= asap7 tech_dir ?= $(if $(filter $(tech_name),sky130 asap7 nangate45),\ - $(vlsi_dir)/hammer/hammer/technology/$(tech_name), \ + $(site_packages_dir)/hammer/technology/$(tech_name), \ $(vlsi_dir)/hammer-$(tech_name)-plugin/hammer/technology/$(tech_name)) SMEMS_COMP ?= $(tech_dir)/sram-compiler.json SMEMS_CACHE ?= $(tech_dir)/sram-cache.json @@ -42,7 +43,7 @@ HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ ./example-vlsi-sky130,\ ./example-vlsi) VLSI_TOP ?= $(TOP) -VLSI_HARNESS_DUT_NAME ?= chiptop +VLSI_MODEL_DUT_NAME ?= chiptop # If overriding, this should be relative to $(vlsi_dir) VLSI_OBJ_DIR ?= build ifneq ($(CUSTOM_VLOG),) @@ -54,23 +55,19 @@ endif ######################################################################################### # general rules ######################################################################################### -ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) -extra_v_includes = $(build_dir)/EICG_wrapper.v +# TODO: get all the top blackboxes only +extra_v_includes = $(build_dir)/EICG_wrapper.v $(build_dir)/gen-collateral/IOCell.v ifneq ($(CUSTOM_VLOG), ) VLSI_RTL = $(CUSTOM_VLOG) - VLSI_BB = /dev/null else - VLSI_RTL = $(ALL_RTL) $(extra_v_includes) - VLSI_BB = $(sim_top_blackboxes) + VLSI_RTL = $(shell cat $(TOP_MODS_FILELIST)) $(TOP_SMEMS_FILE) $(extra_v_includes) endif -.PHONY: default verilog +.PHONY: default default: all all: drc lvs -verilog: $(ALL_RTL) - ######################################################################################### # import other necessary rules and variables ######################################################################################### @@ -104,29 +101,17 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) ######################################################################################### include $(base_dir)/vcs.mk -SIM_FILE_REQS += \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v - -# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) -$(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) - $(foreach file,\ - $^,\ - $(if $(filter %.h,$(file)),\ - ,\ - echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) - SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk -$(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) +$(SIM_CONF): $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(MODEL_FILE) $(MODEL_SMEMS_FILE); do \ + for x in $(shell cat $(sim_common_files)); do \ echo ' - "'$$x'"' >> $@; \ done echo " input_files_meta: 'append'" >> $@ @@ -161,9 +146,9 @@ $(SIM_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) $ ifneq ($(BINARY), ) echo " benchmarks: ['$(BINARY)']" >> $@ endif - echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ + echo " tb_dut: 'TestDriver.testHarness.$(VLSI_MODEL_DUT_NAME)'" >> $@ -$(SIM_DEBUG_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) +$(SIM_DEBUG_CONF): $(sim_common_files) mkdir -p $(dir $@) mkdir -p $(output_dir) echo "sim.inputs:" > $@ @@ -186,7 +171,7 @@ else echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ endif -$(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) +$(SIM_TIMING_CONF): $(sim_common_files) mkdir -p $(dir $@) echo "sim.inputs:" > $@ echo " defines: ['NTC']" >> $@ @@ -195,10 +180,10 @@ $(SIM_TIMING_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_f POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk -$(POWER_CONF): $(VLSI_RTL) $(MODEL_FILE) $(MODEL_SMEMS_FILE) $(sim_common_files) +$(POWER_CONF): $(VLSI_RTL) mkdir -p $(dir $@) echo "power.inputs:" > $@ - echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ + echo " tb_dut: 'testHarness/$(VLSI_MODEL_DUT_NAME)'" >> $@ echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ ifneq ($(BINARY), ) echo " waveforms: [" >> $@ @@ -223,18 +208,12 @@ ifeq ($(CUSTOM_VLOG), ) GENERATED_CONFS += $(SRAM_CONF) endif -$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) +$(SYN_CONF): $(VLSI_RTL) mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " input_files:" >> $@ - for x in $(VLSI_RTL); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ echo "synthesis.inputs:" >> $@ echo " top_module: $(VLSI_TOP)" >> $@ echo " input_files:" >> $@ - for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ + for x in $(VLSI_RTL); do \ echo ' - "'$$x'"' >> $@; \ done diff --git a/vlsi/example-tools.yml b/vlsi/example-tools.yml index c174ef53..23744eaa 100644 --- a/vlsi/example-tools.yml +++ b/vlsi/example-tools.yml @@ -1,7 +1,5 @@ -# SRAM Compiler compiler options -vlsi.core.sram_generator_tool: "hammer.technology..sram_compiler" - # Tool options. Replace with your tool plugin of choice. +vlsi.core.build_system: make # Genus options vlsi.core.synthesis_tool: "hammer.synthesis.genus" synthesis.genus.version: "211" @@ -17,9 +15,8 @@ vlsi.core.lvs_tool: "hammer.lvs.calibre" lvs.calibre.version: "2022.2_24.16" # VCS options vlsi.core.sim_tool: "hammer.sim.vcs" -sim.vcs.version: "T-2022.06-SP2" +sim.vcs.version: "S-2021.09-SP1-1" # Voltus options vlsi.core.power_tool: "hammer.power.voltus" -vlsi.core.power_tool_path_meta: "append" power.voltus.version: "211_ISR3" # NOTE (about VCS+Voltus versions): if using FSDB, the VCS version should be approx 2 years older than the Voltus version for compatibility diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 222d6e18..a743184d 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -17,7 +17,7 @@ ifeq ($(tutorial),sky130-commercial) tech_name ?= sky130 CONFIG ?= TinyRocketConfig TOOLS_CONF ?= example-tools.yml - TECH_CONF ?= hammer/e2e/pdks/sky130-bwrc.yml + TECH_CONF ?= example-sky130.yml DESIGN_CONF ?= example-designs/sky130-commercial.yml EXTRA_CONFS ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, ) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)