From 486cde650af514610e2682c5942f2264f303f319 Mon Sep 17 00:00:00 2001
From: Hansung Kim <hansung_kim@berkeley.edu>
Date: Sun, 5 May 2024 20:06:45 -0700
Subject: [PATCH] common.mk: doc EXTRA_SIM_OUT_NAME

---
 common.mk | 1 +
 1 file changed, 1 insertion(+)

diff --git a/common.mk b/common.mk
index bd263b1d..8770683e 100644
--- a/common.mk
+++ b/common.mk
@@ -16,6 +16,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_LDFLAGS         = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
+"   EXTRA_SIM_OUT_NAME        = additional suffix appended to the simulation .out log filename" \
 "   ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \