diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml
index f570b349..e8cae39a 100644
--- a/vlsi/example-sky130.yml
+++ b/vlsi/example-sky130.yml
@@ -7,14 +7,10 @@ vlsi.core.max_threads: 12
 # Technology paths
 technology.sky130:
   sky130_pdk: "path-to-skywater-pdk/"
-  sky130_nda: "path-to-skywater-src-nda/"
   sky130A: "path-to-sky130A/"
+  sky130_nda: "path-to-skywater-src-nda/"
   openram_lib: "path-to-sky130_sram_macros/" 
 
-# Mentor environment variables
-mentor.extra_env_vars:
-  - PDK_HOME: "path-to-skywater-src-nda/s8/V2.0.1"
-
 # General Hammer Inputs
 
 # Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
@@ -23,7 +19,7 @@ vlsi.inputs.power_spec_type: "cpf"
 
 # Specify clock signals
 vlsi.inputs.clocks: [
-  {name: "clock_clock", period: "200ns", uncertainty: "10ns"}
+  {name: "clock_clock", period: "130ns", uncertainty: "1ns"}
 ]
 
 # Generate Make include to aid in flow 
@@ -33,21 +29,23 @@ vlsi.core.build_system: make
 par.power_straps_mode: generate
 par.generate_power_straps_method: by_tracks
 par.blockage_spacing: 2.0
+par.blockage_spacing_top_layer: met4
 par.generate_power_straps_options:
   by_tracks:
     strap_layers:
-      - met2
-      - met3
       - met4
       - met5
     pin_layers:
       - met5
+    blockage_spacing_met2: 4.0
     track_width: 6
     track_width_met5: 2
     track_spacing: 1
     track_start: 10
-    power_utilization: 0.2
-    power_utilization_met5: 1
+    track_start_met5: 1
+    power_utilization: 0.1
+    power_utilization_met4: 0.3
+    power_utilization_met5: 0.5
 
 # Placement Constraints
 vlsi.inputs.placement_constraints:
@@ -55,127 +53,113 @@ vlsi.inputs.placement_constraints:
     type: toplevel
     x: 0
     y: 0
-    width: 4000
-    height: 3000
+    width: 4500
+    height: 2500
     margins:
       left: 0
       right: 0
       top: 0
       bottom: 0
 
+  # Place data cache SRAM instances
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
     type: hardmacro
-    x: 30
-    y: 2190
+    x: 50
+    y: 100
     orientation: r0
-    top_layer: "met4"
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
     type: hardmacro
-    x: 30
-    y: 1530
-    orientation: mx
-    top_layer: "met4"
+    x: 50
+    y: 700
+    orientation: r0
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
     type: hardmacro
-    x: 30
-    y: 1030
-    orientation: mx
-    top_layer: "met4"
+    x: 50
+    y: 1300
+    orientation: r0
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
     type: hardmacro
-    x: 30 
-    y: 530
-    orientation: mx
-    top_layer: "met4"
+    x: 50
+    y: 1900
+    orientation: r0
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
     type: hardmacro
-    x: 30 
-    y: 30
-    orientation: mx
-    top_layer: "met4"
+    x: 1000
+    y: 1900
+    orientation: r0
+
     
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
     type: hardmacro
-    x: 1110 
-    y: 30
-    orientation: mx
-    top_layer: "met4"
+    x: 1000 
+    y: 1300
+    orientation: r0
     
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
     type: hardmacro
-    x: 2150 
-    y: 30
-    orientation: mx
-    top_layer: "met4"
-    
+    x: 1000 
+    y: 700
+    orientation: r0
+
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
     type: hardmacro
-    x: 2150 
-    y: 530
-    orientation: mx
-    top_layer: "met4"
-    
-
+    x: 1000 
+    y: 100
+    orientation: r0
 
+  # Place instruction cache SRAM instances
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
-    x: 2150
-    y: 1550
-    orientation: mx
-    top_layer: "met4"
-    
+    x: 3700
+    y: 100
+    orientation: r0
+
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
     type: hardmacro
-    x: 2150
-    y: 1030
+    x: 3700
+    y: 700
     orientation: r0
-    top_layer: "met4"
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
     type: hardmacro
-    x: 2350
-    y: 2200
+    x: 3000
+    y: 100
     orientation: r0
-    top_layer: "met4"
-    
+
+  # Place L2 TLB SRAM instances
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
     type: hardmacro
-    x: 3100
-    y: 30
+    x: 1900
+    y: 1900
     orientation: "r0"
-    top_layer: "met4"
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
     type: hardmacro
-    x: 3100
-    y: 530
+    x: 2600
+    y: 1900
     orientation: "r0"
-    top_layer: "met4"
-
+ 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
     type: hardmacro
-    x: 3100
-    y: 1030
+    x: 3300
+    y: 1900
     orientation: "r0"
-    top_layer: "met4"
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
     type: hardmacro
-    x: 3100
-    y: 1530
+    x: 3950
+    y: 1900
     orientation: "r0"
-    top_layer: "met4"
 
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
     type: hardmacro
-    x: 3100
-    y: 2190
+    x: 3950
+    y: 1300
     orientation: "r0"
-    top_layer: "met4"
 
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated