From 48c8e0f571e973115fc52a6bbaeb34e7b59c91fa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 28 Sep 2019 18:17:42 -0700 Subject: [PATCH] [docs][ci skip] Address comments --- .../Debugging-RTL.rst | 12 ++++++++---- docs/Advanced-Concepts/index.rst | 1 + docs/Chipyard-Basics/index.rst | 1 - 3 files changed, 9 insertions(+), 5 deletions(-) rename docs/{Chipyard-Basics => Advanced-Concepts}/Debugging-RTL.rst (87%) diff --git a/docs/Chipyard-Basics/Debugging-RTL.rst b/docs/Advanced-Concepts/Debugging-RTL.rst similarity index 87% rename from docs/Chipyard-Basics/Debugging-RTL.rst rename to docs/Advanced-Concepts/Debugging-RTL.rst index 36e101ea..464c5571 100644 --- a/docs/Chipyard-Basics/Debugging-RTL.rst +++ b/docs/Advanced-Concepts/Debugging-RTL.rst @@ -7,13 +7,16 @@ IP, or by modifying existing Chisel generators. Such changes might introduce bugs. This section aims to run through a typical debugging flow using Chipyard. We assume the user has a custom SoC configuration, and is trying to verify functionality by running some software test. +We also assume the software has already been verified on a functional +simulator, such as Spike or QEMU. This section will focus on debugging +hardware. Waveforms --------------------------- -The default SW simulators do not dump waveforms during execution. To build -simulators with wave dump capabilities use must use the ``debug`` make target. -For example: +The default software RTL simulators do not dump waveforms during execution. +To build simulators with wave dump capabilities use must use the ``debug`` +make target. For example: .. code-block:: shell @@ -81,5 +84,6 @@ directory. Firesim Debugging --------------------------- Chisel printfs, asserts, and waveform generation are also available in FireSim -FPGA-accelerated simulation. See the FireSim docs for more detail. +FPGA-accelerated simulation. See the FireSim +`documentation `__ for more detail. diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index 2994899c..8194fe1f 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -10,4 +10,5 @@ They expect you to know about Chisel, Parameters, Configs, etc. Top-Testharness Chip-Communication + Debugging-RTL Resources diff --git a/docs/Chipyard-Basics/index.rst b/docs/Chipyard-Basics/index.rst index 4ca236c4..467f147a 100644 --- a/docs/Chipyard-Basics/index.rst +++ b/docs/Chipyard-Basics/index.rst @@ -18,6 +18,5 @@ Hit next to get started! Chipyard-Components Configs-Parameters-Mixins Initial-Repo-Setup - Debugging-RTL