From 4956a93c2711e553d47c7d52ec613dd7a58b3124 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 15 Feb 2022 16:56:05 -0800 Subject: [PATCH] changing clock to clock_clock [skip ci] --- vlsi/example-asap7.yml | 2 +- vlsi/example-design.yml | 2 +- vlsi/example-nangate45.yml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/vlsi/example-asap7.yml b/vlsi/example-asap7.yml index 683edaae..213f0b90 100644 --- a/vlsi/example-asap7.yml +++ b/vlsi/example-asap7.yml @@ -17,7 +17,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "1ns", uncertainty: "0.1ns"} + {name: "clock_clock", period: "1ns", uncertainty: "0.1ns"} ] # Generate Make include to aid in flow diff --git a/vlsi/example-design.yml b/vlsi/example-design.yml index 43f54997..3c11cd11 100644 --- a/vlsi/example-design.yml +++ b/vlsi/example-design.yml @@ -10,7 +10,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "2ns", uncertainty: "0.1ns"} + {name: "clock_clock", period: "2ns", uncertainty: "0.1ns"} ] # Specify pin properties diff --git a/vlsi/example-nangate45.yml b/vlsi/example-nangate45.yml index c1c3ba63..5b4a59ea 100644 --- a/vlsi/example-nangate45.yml +++ b/vlsi/example-nangate45.yml @@ -22,7 +22,7 @@ vlsi.inputs.power_spec_type: "cpf" # Specify clock signals vlsi.inputs.clocks: [ - {name: "clock", period: "5ns", uncertainty: "0.5ns"} + {name: "clock_clock", period: "5ns", uncertainty: "0.5ns"} ] # Generate Make include to aid in flow