From 4adb8d91c1382c58865e413a5a358703a7e95a8a Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 11 Apr 2023 17:44:24 -0700 Subject: [PATCH] Fix ChipLikeQuadRocketConfig crossing There needs to be a crossing between sbus/fbus when they are on separate clock domains --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 7f875584..fa08acf7 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -35,6 +35,7 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.clocking.WithClockGroupsCombinedByName("fbus", "fbus", "pbus") ++ // Set up the crossings + new chipyard.config.WithFbusToSbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between SBUS and FBUS new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS