From 4b9e9dacbcd4618926448f9787e4818df09bbbc0 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 18 Dec 2023 09:23:42 -0800 Subject: [PATCH] Move clock tap to its own async domain --- .../src/main/scala/clocking/CanHaveClockTap.scala | 13 ++++--------- .../src/main/scala/config/AbstractConfig.scala | 2 +- .../src/main/scala/config/RocketConfigs.scala | 2 +- .../scala/config/fragments/ClockingFragments.scala | 2 +- 4 files changed, 7 insertions(+), 12 deletions(-) diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala index 0bf7242b..5d0ce538 100644 --- a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala +++ b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala @@ -10,18 +10,13 @@ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ -case class ClockTapParams( - busWhere: TLBusWrapperLocation = SBUS, // by default, tap the sbus clock as a debug clock - divider: Int = 16, // a fixed clock division ratio for the clock tap -) - -case object ClockTapKey extends Field[Option[ClockTapParams]](Some(ClockTapParams())) +case object ClockTapKey extends Field[Boolean](true) trait CanHaveClockTap { this: BaseSubsystem => - val clockTapNode = p(ClockTapKey).map { tapParams => + require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven") + val clockTapNode = Option.when(p(ClockTapKey)) { val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) - val clockTapDivider = LazyModule(new ClockDivider(tapParams.divider)) - clockTap := clockTapDivider.node := locateTLBusWrapper(tapParams.busWhere).fixedClockNode + clockTap := ClockGroup() := asyncClockGroupsNode clockTap } val clockTapIO = clockTapNode.map { node => InModuleBody { diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala index 96794546..2e34f19c 100644 --- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala +++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala @@ -54,7 +54,7 @@ class AbstractConfig extends Config( new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks - Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++ + Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++ new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 929e8c59..3c0f66d7 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -60,7 +60,7 @@ class MulticlockRocketConfig extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Frequency specifications new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540 - new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil), + new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil), ("periphery", Seq("pbus", "fbus"), Nil)) ++ new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540 new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540 diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala index 8b061e5c..9869095f 100644 --- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala @@ -130,5 +130,5 @@ class WithNoResetSynchronizers extends Config((site, here, up) => { // Remove any ClockTap ports in this system class WithNoClockTap extends Config((site, here, up) => { - case ClockTapKey => None + case ClockTapKey => false })