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update make variable names | change hwacha to use its own generator

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abejgonzalez
2019-04-24 00:43:44 -07:00
parent 017a3c2350
commit 4c3dc0889c
4 changed files with 37 additions and 30 deletions
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4
sims/verisim/Makefile
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@@ -22,8 +22,8 @@ sim_name = verilator
# vcs simulator types and rules
#########################################################################################
sim_prefix = simulator
sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
.PHONY: default debug
default: $(sim)

4
sims/vsim/Makefile
View File

@@ -22,8 +22,8 @@ sim_name = vcs
# vcs simulator types and rules
#########################################################################################
sim_prefix = simv
sim = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(PROJECT)-$(CONFIG)-debug
sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
.PHONY: default debug
default: $(sim)