Enabling JTAG Debuging in VCU118 FPGA

fpga/src/main/scala/vcu118/Configs.scala

@@ -54,11 +54,11 @@ class WithVCU118Tweaks extends Config(
   new WithUART ++
   new WithSPISDCard ++
   new WithDDRMem ++
+  new WithJTAG ++
   // other configuration
   new WithDefaultPeripherals ++
   new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
   new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
-  new chipyard.config.WithNoDebug ++ // remove debug module
   new freechips.rocketchip.subsystem.WithoutTLMonitors ++
   new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
 )

fpga/src/main/scala/vcu118/HarnessBinders.scala

@@ -36,3 +36,17 @@ class WithDDRMem extends HarnessBinder({
     ddrClientBundle <> port.io
   }
 })
+
+class WithJTAG extends HarnessBinder({
+  case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
+    val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
+    port.io.TCK := jtag_io.TCK
+    port.io.TMS := jtag_io.TMS
+    port.io.TDI := jtag_io.TDI
+    jtag_io.TDO.data := port.io.TDO
+    jtag_io.TDO.driven := true.B
+    // ignore srst_n
+    jtag_io.srst_n := DontCare
+
+  }
+})

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -85,6 +85,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
   )))))
   ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
 
+  /*** JTAG ***/
+  val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())
+
   // module implementation
   override lazy val module = new VCU118FPGATestHarnessImp(this)
 }