From 5136b7e2ead148e58e6051c8355bb785b9132f8f Mon Sep 17 00:00:00 2001 From: Jordan Lees Date: Fri, 3 Nov 2023 23:56:51 -0400 Subject: [PATCH] Update docs/Simulation/Software-RTL-Simulation.rst Co-authored-by: Jerry Zhao --- docs/Simulation/Software-RTL-Simulation.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Simulation/Software-RTL-Simulation.rst b/docs/Simulation/Software-RTL-Simulation.rst index 68ebd541..8c87cc80 100644 --- a/docs/Simulation/Software-RTL-Simulation.rst +++ b/docs/Simulation/Software-RTL-Simulation.rst @@ -84,7 +84,7 @@ For example: Custom Benchmarks/Tests ------------------------------- -To compile your own code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. Then when you run ``make``, all of the programs inside ``tests`` will output a ``.riscv`` binary, which can be used with the simulator as described above. +To compile your own bare-metal code to run in a Verilator/VCS simulation, add it to Chipyard's ``tests`` directory then add its name to the list of ``PROGRAMS`` inside the ``Makefile``. These binaries are compiled with the libgloss-htif library, which implements a minimal set of useful syscalls for bare-metal binaries. Then when you run ``make``, all of the programs inside ``tests`` will be compiled into ``.riscv`` ELF binaries, which can be used with the simulator as described above. .. code-block:: shell