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Merge remote-tracking branch 'origin/dev' into addMarshal

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Nathan Pemberton
2019-10-06 18:44:41 -04:00
parent 151d3f16c3 b31a06b01d
commit 54d683114c
22 changed files with 492 additions and 503 deletions
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6
.circleci/defaults.sh
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@@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
mapping["rocketchip"]="SUB_PROJECT=rocketchip"
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha"
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig"
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig"
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig"
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"

10
.gitmodules vendored
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@@ -77,21 +77,21 @@
[submodule "tools/treadle"]
path = tools/treadle
url = https://github.com/freechipsproject/treadle.git
[submodule "generators/rocc-template"]
[submodule "generators/sha3"]
path = generators/sha3
url = https://github.com/ucb-bar/rocc-template.git
url = https://github.com/ucb-bar/sha3.git
[submodule "tools/firrtl-interpreter"]
path = tools/firrtl-interpreter
url = https://github.com/freechipsproject/firrtl-interpreter.git
[submodule "vlsi/hammer-cadence-plugins"]
path = vlsi/hammer-cadence-plugins
url = git@github.com:ucb-bar/hammer-cadence-plugins.git
url = https://github.com/ucb-bar/hammer-cadence-plugins.git
[submodule "vlsi/hammer-synopsys-plugins"]
path = vlsi/hammer-synopsys-plugins
url = git@github.com:ucb-bar/hammer-synopsys-plugins.git
url = https://github.com/ucb-bar/hammer-synopsys-plugins.git
[submodule "vlsi/hammer-mentor-plugins"]
path = vlsi/hammer-mentor-plugins
url = git@github.com:ucb-bar/hammer-mentor-plugins.git
url = https://github.com/ucb-bar/hammer-mentor-plugins.git
[submodule "toolchains/qemu"]
path = toolchains/qemu
url = https://github.com/qemu/qemu.git

3
build.sbt
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@@ -23,6 +23,7 @@ lazy val commonSettings = Seq(
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
unmanagedBase := (chipyardRoot / unmanagedBase).value,
allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"),
exportJars := true,
resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases"),
@@ -188,7 +189,7 @@ lazy val midas = ProjectRef(firesimDir, "midas")
lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
lazy val firechip = (project in file("generators/firechip"))
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
.settings(
commonSettings,
testGrouping in Test := isolateAllTests( (definedTests in Test).value )

6
docs/Quick-Start.rst
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@@ -5,8 +5,10 @@ Requirements
-------------------------------------------
Chipyard is developed and tested on Linux-based systems.
It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
Working under Windows is not recommended.
.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
.. Warning:: Working under Windows is not recommended.
Setting up the Chipyard Repo
-------------------------------------------

2
docs/Simulation/FPGA-Accelerated-Simulators.rst
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@@ -87,4 +87,4 @@ will look as follows:
You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG``
variables. Note that if your target machine has I/O not provided in the default
FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need
to write a custom endpoint.
to write a custom bridge.

7
docs/VLSI/Tutorial.rst
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@@ -54,8 +54,9 @@ Prerequisites
* Genus, Innovus, and Calibre licenses
* For ASAP7 specifically:
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you.
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion.
* Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded).
Initial Setup
-------------
@@ -83,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u
make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead.
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches).
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.
@@ -98,7 +99,7 @@ example-vlsi
^^^^^^^^^^^^
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4.
The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter, and should be inserted after ``write_design``. This hook is necessary because the ASAP7 PDK does place-and-route using 4x upscaled LEFs for Innovus licensing reasons, thereby requiring the cells created in the post-P&R GDS to be scaled down by a factor of 4.
example.yml
^^^^^^^^^^^

76
generators/firechip/src/main/scala/BridgeBinders.scala Normal file
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@@ -0,0 +1,76 @@
//See LICENSE for license details.
package firesim.firesim
import chisel3._
import freechips.rocketchip.config.{Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
import icenet.HasPeripheryIceNICModuleImpValidOnly
import junctions.{NastiKey, NastiParameters}
import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
import firesim.bridges._
import firesim.configs.MemModelKey
import firesim.util.RegisterBridgeBinder
class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
target.debug.clockeddmi.foreach({ cdmi =>
cdmi.dmi.req.valid := false.B
cdmi.dmi.req.bits := DontCare
cdmi.dmi.resp.ready := false.B
cdmi.dmiClock := false.B.asClock
cdmi.dmiReset := false.B
})
Seq()
})
class WithSerialBridge extends RegisterBridgeBinder({
case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p))
})
class WithNICBridge extends RegisterBridgeBinder({
case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p))
})
class WithUARTBridge extends RegisterBridgeBinder({
case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p))
})
class WithBlockDeviceBridge extends RegisterBridgeBinder({
case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p))
})
class WithFASEDBridge extends RegisterBridgeBinder({
case t: CanHaveMasterAXI4MemPortModuleImp =>
implicit val p = t.p
(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
axi4Bundle.ar.bits.addr.getWidth,
axi4Bundle.ar.bits.id.getWidth)
FASEDBridge(axi4Bundle, t.reset.toBool,
CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
})
}).toSeq
})
class WithTracerVBridge extends RegisterBridgeBinder({
case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
})
// Shorthand to register all of the provided bridges above
class WithDefaultFireSimBridges extends Config(
new WithTiedOffDebug ++
new WithSerialBridge ++
new WithNICBridge ++
new WithUARTBridge ++
new WithBlockDeviceBridge ++
new WithFASEDBridge ++
new WithTracerVBridge
)

80
generators/firechip/src/main/scala/EndpointBinders.scala
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@@ -1,80 +0,0 @@
//See LICENSE for license details.
package firesim.firesim
import chisel3._
import freechips.rocketchip.config.{Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
import icenet.HasPeripheryIceNICModuleImpValidOnly
import junctions.{NastiKey, NastiParameters}
import midas.widgets.{IsEndpoint}
import midas.models.{FASEDEndpoint, FasedAXI4Edge}
import firesim.endpoints._
import firesim.configs.MemModelKey
import firesim.util.RegisterEndpointBinder
class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp =>
target.debug.clockeddmi.foreach({ cdmi =>
cdmi.dmi.req.valid := false.B
cdmi.dmi.req.bits := DontCare
cdmi.dmi.resp.ready := false.B
cdmi.dmiClock := false.B.asClock
cdmi.dmiReset := false.B
})
Seq()
})
class WithSerialEndpoint extends RegisterEndpointBinder({
case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p))
})
class WithNICEndpoint extends RegisterEndpointBinder({
case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p))
})
class WithUARTEndpoint extends RegisterEndpointBinder({
case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p))
})
class WithBlockDeviceEndpoint extends RegisterEndpointBinder({
case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p))
})
class WithFASEDEndpoint extends RegisterEndpointBinder({
case t: CanHaveMasterAXI4MemPortModuleImp =>
implicit val p = t.p
(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
axi4Bundle.ar.bits.addr.getWidth,
axi4Bundle.ar.bits.id.getWidth)
val fasedP = p.alterPartial({
case NastiKey => nastiKey
case FasedAXI4Edge => Some(edge)
})
FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP)
})
}).toSeq
})
class WithTracerVEndpoint extends RegisterEndpointBinder({
case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p)
})
// Shorthand to register all of the provided endpoints above
class WithDefaultFireSimEndpoints extends Config(
new WithTiedOffDebug ++
new WithSerialEndpoint ++
new WithNICEndpoint ++
new WithUARTEndpoint ++
new WithBlockDeviceEndpoint ++
new WithFASEDEndpoint ++
new WithTracerVEndpoint
)

9
generators/firechip/src/main/scala/Generator.scala
View File

@@ -2,7 +2,7 @@
package firesim.firesim
import java.io.{File}
import java.io.{File, FileWriter}
import chisel3.experimental.RawModule
import chisel3.internal.firrtl.{Circuit, Port}
@@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
}
object FireSimGenerator extends App with IsFireSimGeneratorLike {
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
lazy val generatorArgs = GeneratorArgs(args)
lazy val genDir = new File(names.targetDir)
elaborateAndCompileWithMidas
// The only reason this is not generateFirrtl; generateAnno is that we need to use a different
// JsonProtocol to properly write out the annotations. Fix once the generated are unified
elaborate
generateTestSuiteMakefrags
generateHostVerilogHeader
generateArtefacts
generateTclEnvFile
}
// For now, provide a separate generator app when not specifically building for FireSim

42
generators/firechip/src/main/scala/SimConfigs.scala
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@@ -1,42 +0,0 @@
//See LICENSE for license details.
package firesim.firesim
import freechips.rocketchip.config.{Parameters, Config, Field}
import midas.models._
import firesim.endpoints._
import firesim.configs._
/*******************************************************************************
* Full PLATFORM_CONFIG Configurations. These set simulator parameters.
*
* In general, if you're adding or removing features from any of these, you
* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
* will store this name as part of the tags for the AGFI, so that later you can
* reconstruct what is in a particular AGFI. These tags are also used to
* determine which driver to build.
*******************************************************************************/
class FireSimConfig extends Config(new BasePlatformConfig)
class FireSimClockDivConfig extends Config(
new FireSimConfig)
class FireSimDDR3Config extends Config(
new FireSimConfig)
class FireSimDDR3LLC4MBConfig extends Config(
new FireSimConfig)
class FireSimDDR3FRFCFSConfig extends Config(
new FireSimConfig)
class FireSimDDR3FRFCFSLLC4MBConfig extends Config(
new FireSimConfig)
class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
new FireSimConfig)
class Midas2Config extends Config(
new WithMultiCycleRamModels ++
new FireSimConfig)

20
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -18,9 +18,9 @@ import scala.math.{min, max}
import tracegen.TraceGenKey
import icenet._
import firesim.endpoints._
import firesim.bridges._
import firesim.util.{WithNumNodes}
import firesim.configs.WithDefaultMemModel
import firesim.configs._
class WithBootROM extends Config((site, here, up) => {
case BootROMParams => {
@@ -86,6 +86,11 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
case PrintTracePort => true
})
// FASED Config Aliases. This to enable config generation via "_" concatenation
// which requires that all config classes be defined in the same package
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div
/*******************************************************************************
* Full TARGET_CONFIG configurations. These set parameters of the target being
* simulated.
@@ -108,7 +113,7 @@ class FireSimRocketChipConfig extends Config(
new WithPerfCounters ++
new WithoutClockGating ++
new WithDefaultMemModel ++
new WithDefaultFireSimEndpoints ++
new WithDefaultFireSimBridges ++
new freechips.rocketchip.system.DefaultConfig)
class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
@@ -138,6 +143,13 @@ class FireSimRocketChipOctaCoreConfig extends Config(
new WithNDuplicatedRocketCores(8) ++
new FireSimRocketChipSingleCoreConfig)
// SHA-3 accelerator config
class FireSimRocketChipSha3L2Config extends Config(
new WithInclusiveCache ++
new sha3.WithSha3Accel ++
new WithNBigCores(1) ++
new FireSimRocketChipConfig)
class FireSimBoomConfig extends Config(
new WithBootROM ++
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
@@ -151,7 +163,7 @@ class FireSimBoomConfig extends Config(
new WithDefaultMemModel ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new WithDefaultFireSimEndpoints ++
new WithDefaultFireSimBridges ++
new freechips.rocketchip.system.BaseConfig
)

4
generators/firechip/src/main/scala/TargetMixins.scala
View File

@@ -11,12 +11,12 @@ import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.TracedInstruction
import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
* TracerV endpoint can match on.
* TracerV bridge can match on.
*/
object PrintTracePort extends Field[Boolean](false)

15
generators/firechip/src/test/scala/ScalaTestSuite.scala
View File

@@ -23,6 +23,8 @@ abstract class FireSimTestSuite(
import scala.concurrent.duration._
import ExecutionContext.Implicits.global
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
lazy val generatorArgs = GeneratorArgs(
midasFlowKind = "midas",
targetDir = "generated-src",
@@ -42,7 +44,6 @@ abstract class FireSimTestSuite(
val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
override lazy val platform = hostParams(midas.Platform)
def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
@@ -122,7 +123,7 @@ abstract class FireSimTestSuite(
clean
mkdirs
elaborateAndCompileWithMidas
elaborate
generateTestSuiteMakefrags
runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0"""))
diffTracelog("rv64ui-p-simple.out")
@@ -130,10 +131,10 @@ abstract class FireSimTestSuite(
runSuite("verilator")(FastBlockdevTests)
}
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig")
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") {
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
runSuite("verilator")(NICLoopbackTests)
}
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config")
class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config")
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")

2
generators/sha3

Submodule generators/sha3 updated: 83dd1955a9...e6f5bab675

2
sims/firesim

Submodule sims/firesim updated: 3840b6e7bf...6d578eeb40

2
toolchains/esp-tools/riscv-isa-sim

Submodule toolchains/esp-tools/riscv-isa-sim updated: 92f2f467c0...0ffa02e5b4

21
vlsi/example-vlsi
View File

@@ -24,21 +24,25 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
x.append('''
# TODO
# Place custom TCL here
set_db route_design_bottom_routing_layer 2
set_db route_design_top_routing_layer 7
''')
return True
def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
"""
Scale the final GDS by a factor of 4
hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script
"""
x.append('''
# Write script out to a temporary file and execute it
set fp [open "{script_file}" "w"]
puts -nonewline $fp "{script_text}"
close $fp
if {{ [catch {{ exec python3 {script_file} }} msg] }} {{
puts "$::errorInfo"
}}
# Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python
set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"]
python3 {script_file}
'''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py")))
return True
@@ -50,16 +54,21 @@ class ExampleDriver(CLIDriver):
# Default set of steps can be found in the CAD tool plugin's __init__.py
# make_pre_insertion_hook will execute the custom hook before the specified step
hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
# hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
# make_post_insertion_hook will execute the custom hook after the specified step
hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
# make_replacement_hook will replace the specified step with a custom hook
hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
# make_removal_hook will remove the specified step from the flow
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
# The target step in any of the above calls may be a default step or another one of your custom hooks
# This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py)
# This is an example of a technology-supplied hook
hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds)
]
return extra_hooks

16
vlsi/example.yml
View File

@@ -34,8 +34,11 @@ par.generate_power_straps_options:
- M7
- M8
- M9
track_width: 5
pin_layers:
- M9
track_width: 7 # minimum allowed for M2 & M3
track_spacing: 0
track_spacing_M3: 1 # to avoid M2 shorts at higher density
track_start: 10
power_utilization: 0.05
power_utilization_M8: 1.0
@@ -54,7 +57,7 @@ vlsi.inputs.placement_constraints:
left: 0
right: 0
top: 0
bottom: 1.08 #must be at least this number
bottom: 0
- path: "Sha3AccelwBB/dco"
type: hardmacro
x: 108
@@ -63,6 +66,13 @@ vlsi.inputs.placement_constraints:
height: 128
orientation: r0
top_layer: M9
- path: "Sha3AccelwBB/place_obs_bottom"
type: obstruction
obs_types: ["place"]
x: 0
y: 0
width: 300
height: 1.08 # 1 core site tall, necessary to avoid shorts
# Pin placement constraints
vlsi.inputs.pin_mode: generated
@@ -124,7 +134,7 @@ synthesis.genus.version: "1813"
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "191"
par.innovus.version: "181"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options

BIN
vlsi/extra_libraries/example/ExampleDCO.gds
View File

Binary file not shown.

668
vlsi/extra_libraries/example/ExampleDCO.lef
View File

@@ -6,374 +6,372 @@ MACRO ExampleDCO
CLASS BLOCK ;
ORIGIN 0 0 ;
FOREIGN ExampleDCO 0 0 ;
SIZE 128.0 BY 128.0 ;
SIZE 123.936 BY 125.536 ;
SYMMETRY X Y ;
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M7 ;
RECT 32.96 124.0 33.6 128.0 ;
END
PORT
LAYER M5 ;
RECT 3.024 121.536 3.8 125.536 ;
END
END VDD
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
PORT
LAYER M5 ;
RECT 93.12 124.0 93.76 128.0 ;
END
RECT 1.728 121.536 2.5 125.536 ;
END
END VSS
PIN col_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 113.28 4.0 113.664 ;
END
END col_sel_b[13]
PIN col_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 107.648 4.0 108.032 ;
END
END col_sel_b[11]
PIN col_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 90.752 4.0 91.136 ;
END
END col_sel_b[5]
PIN col_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 110.464 4.0 110.848 ;
END
END col_sel_b[12]
PIN col_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 104.832 4.0 105.216 ;
END
END col_sel_b[10]
PIN col_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 102.016 4.0 102.4 ;
END
END col_sel_b[9]
PIN col_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 99.2 4.0 99.584 ;
END
END col_sel_b[8]
PIN col_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 96.384 4.0 96.768 ;
END
END col_sel_b[7]
PIN col_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 93.568 4.0 93.952 ;
END
END col_sel_b[6]
PIN col_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 87.936 4.0 88.32 ;
END
END col_sel_b[4]
PIN col_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 85.12 4.0 85.504 ;
END
END col_sel_b[3]
PIN col_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 82.304 4.0 82.688 ;
END
END col_sel_b[2]
PIN col_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 79.488 4.0 79.872 ;
END
END col_sel_b[1]
PIN col_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 76.672 4.0 77.056 ;
END
END col_sel_b[0]
PIN row_sel_b[14]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 71.04 4.0 71.424 ;
END
END row_sel_b[14]
PIN row_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 68.224 4.0 68.608 ;
END
END row_sel_b[13]
PIN row_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 65.408 4.0 65.792 ;
END
END row_sel_b[12]
PIN row_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 62.592 4.0 62.976 ;
END
END row_sel_b[11]
PIN row_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 59.776 4.0 60.16 ;
END
END row_sel_b[10]
PIN row_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 56.96 4.0 57.344 ;
END
END row_sel_b[9]
PIN row_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 54.144 4.0 54.528 ;
END
END row_sel_b[8]
PIN row_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 51.328 4.0 51.712 ;
END
END row_sel_b[7]
PIN row_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 48.512 4.0 48.896 ;
END
END row_sel_b[6]
PIN row_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 45.696 4.0 46.08 ;
END
END row_sel_b[5]
PIN row_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 42.88 4.0 43.264 ;
END
END row_sel_b[4]
PIN row_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 40.064 4.0 40.448 ;
END
END row_sel_b[3]
PIN row_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 37.248 4.0 37.632 ;
END
END row_sel_b[2]
PIN row_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 34.432 4.0 34.816 ;
END
END row_sel_b[1]
PIN row_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 31.616 4.0 32.0 ;
END
END row_sel_b[0]
PIN code_regulator[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 28.8 4.0 29.184 ;
END
END code_regulator[7]
PIN code_regulator[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 25.984 4.0 26.368 ;
END
END code_regulator[6]
PIN code_regulator[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 23.168 4.0 23.552 ;
END
END code_regulator[5]
PIN code_regulator[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 20.352 4.0 20.736 ;
END
END code_regulator[4]
PIN code_regulator[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 17.536 4.0 17.92 ;
END
END code_regulator[3]
PIN code_regulator[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 14.72 4.0 15.104 ;
END
END code_regulator[2]
PIN code_regulator[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 11.904 4.0 12.288 ;
END
END code_regulator[1]
PIN code_regulator[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 9.088 4.0 9.472 ;
END
END code_regulator[0]
PIN row_sel_b[15]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 73.856 4.0 74.24 ;
END
END row_sel_b[15]
PIN dither
DIRECTION INPUT ;
USE SIGNAL ;
PORT
PORT
LAYER M4 ;
RECT 0.0 6.272 4.0 6.656 ;
END
RECT 0.0 0.384 1.2 0.768 ;
END
END dither
PIN row_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 1.536 1.2 1.92 ;
END
END row_sel_b[0]
PIN row_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 2.688 1.2 3.072 ;
END
END row_sel_b[1]
PIN row_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 3.84 1.2 4.224 ;
END
END row_sel_b[2]
PIN row_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 4.992 1.2 5.376 ;
END
END row_sel_b[3]
PIN row_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 6.144 1.2 6.528 ;
END
END row_sel_b[4]
PIN row_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 7.296 1.2 7.68 ;
END
END row_sel_b[5]
PIN row_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 8.448 1.2 8.832 ;
END
END row_sel_b[6]
PIN row_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 9.6 1.2 9.984 ;
END
END row_sel_b[7]
PIN row_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 10.752 1.2 11.136 ;
END
END row_sel_b[8]
PIN row_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 11.904 1.2 12.288 ;
END
END row_sel_b[9]
PIN row_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 13.056 1.2 13.44 ;
END
END row_sel_b[10]
PIN row_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 14.208 1.2 14.592 ;
END
END row_sel_b[11]
PIN row_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 15.36 1.2 15.744 ;
END
END row_sel_b[12]
PIN row_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 16.512 1.2 16.896 ;
END
END row_sel_b[13]
PIN row_sel_b[14]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 17.664 1.2 18.048 ;
END
END row_sel_b[14]
PIN row_sel_b[15]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 18.816 1.2 19.2 ;
END
END row_sel_b[15]
PIN col_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 19.968 1.2 20.352 ;
END
END col_sel_b[0]
PIN col_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 21.12 1.2 21.504 ;
END
END col_sel_b[1]
PIN col_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 22.272 1.2 22.656 ;
END
END col_sel_b[2]
PIN col_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 23.424 1.2 23.808 ;
END
END col_sel_b[3]
PIN col_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 24.576 1.2 24.96 ;
END
END col_sel_b[4]
PIN col_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 25.728 1.2 26.112 ;
END
END col_sel_b[5]
PIN col_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 26.88 1.2 27.264 ;
END
END col_sel_b[6]
PIN col_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 28.032 1.2 28.416 ;
END
END col_sel_b[7]
PIN col_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 29.184 1.2 29.568 ;
END
END col_sel_b[8]
PIN col_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 30.336 1.2 30.72 ;
END
END col_sel_b[9]
PIN col_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 31.488 1.2 31.872 ;
END
END col_sel_b[10]
PIN col_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 32.64 1.2 33.024 ;
END
END col_sel_b[11]
PIN col_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 33.792 1.2 34.176 ;
END
END col_sel_b[12]
PIN col_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 34.944 1.2 35.328 ;
END
END col_sel_b[13]
PIN code_regulator[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 36.096 1.2 36.48 ;
END
END code_regulator[0]
PIN code_regulator[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 37.248 1.2 37.632 ;
END
END code_regulator[1]
PIN code_regulator[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 38.4 1.2 38.784 ;
END
END code_regulator[2]
PIN code_regulator[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 39.552 1.2 39.936 ;
END
END code_regulator[3]
PIN code_regulator[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 40.704 1.2 41.088 ;
END
END code_regulator[4]
PIN code_regulator[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 41.856 1.2 42.24 ;
END
END code_regulator[5]
PIN code_regulator[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 43.008 1.2 43.392 ;
END
END code_regulator[6]
PIN code_regulator[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 44.16 1.2 44.544 ;
END
END code_regulator[7]
PIN sleep_b
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M5 ;
RECT 9.792 0.0 10.176 4.0 ;
END
PORT
LAYER M4 ;
RECT 0.0 45.312 1.2 45.696 ;
END
END sleep_b
PIN clock
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
PORT
LAYER M4 ;
RECT 124.0 70.864 128.0 71.248 ;
END
RECT 122.736 0.384 123.936 0.768 ;
END
END clock
OBS
OBS
LAYER M1 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M2 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M3 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M4 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M5 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M6 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M7 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M8 ;
RECT 0.0 0.0 128.0 128.0 ;
RECT 1.2 0.0 122.736 121.536 ;
LAYER M9 ;
RECT 0.0 0.0 128.0 128.0 ;
LAYER Pad ;
RECT 0.0 0.0 128.0 128.0 ;
END
RECT 1.2 0.0 122.736 121.536 ;
END
END ExampleDCO
END LIBRARY

2
vlsi/hammer

Submodule vlsi/hammer updated: 1b07b9a378...5c0909ebd6

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: 06ce365b36...5f5d9d9e57