diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index 5b3fef0a..483afb7b 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -104,7 +104,10 @@ class WithFireSimDesignTweaks extends Config(
   // Optional: reduce the width of the Serial TL interface
   new testchipip.serdes.WithSerialTLWidth(4) ++
   // Required*: Scale default baud rate with periphery bus frequency
-  new chipyard.config.WithUARTInitBaudRate(BigInt(3686400L)) ++
+  new chipyard.config.WithUART(
+    baudrate=BigInt(3686400L), 
+    txEntries=256, rxEntries=256) ++        // FireSim requires a larger UART FIFO buffer, 
+  new chipyard.config.WithNoUART() ++       // so we overwrite the default one
   // Optional: Adds IO to attach tracerV bridges
   new chipyard.config.WithTraceIO ++
   // Optional: Request 16 GiB of target-DRAM by default (can safely request up to 64 GiB on F1)
@@ -136,9 +139,6 @@ class WithFireSimHighPerfClocking extends Config(
 
 // Tweaks that are generally applied to all firesim configs setting a single clock domain at 1000 MHz
 class WithFireSimConfigTweaks extends Config(
-  new chipyard.config.WithUART(txEntries=256, rxEntries=256) ++ // FireSim requires a larger UART FIFO buffer, 
-  new chipyard.config.WithNoUART() ++                           // so we overwrite the default one
-
   // 1 GHz matches the FASED default (DRAM modeli realistically configured for that frequency)
   // Using some other frequency will require runnings the FASED runtime configuration generator
   // to generate faithful DDR3 timing values.