NOT WORKING: VCU118 Commit

fpga/Makefile

@@ -19,11 +19,11 @@ include $(base_dir)/variables.mk
 # default variables to build the arty example
 SUB_PROJECT       := fpga
 SBT_PROJECT       := fpga_platforms
-MODEL             := ArtyFPGATestHarness
-VLOG_MODEL        := ArtyFPGATestHarness
-MODEL_PACKAGE     := chipyard.fpga.arty
-CONFIG            := E300ArtyDevKitConfig
-CONFIG_PACKAGE    := chipyard.fpga.arty.e300
+MODEL             := VCU118FPGATestHarness
+VLOG_MODEL        := VCU118FPGATestHarness
+MODEL_PACKAGE     := chipyard.fpga.vcu118
+CONFIG            := FakeBringupConfig
+CONFIG_PACKAGE    := chipyard.fpga.vcu118
 GENERATOR_PACKAGE := chipyard
 TB                := none # unused
 TOP               := ChipTop

fpga/src/main/scala/vcu118/Configs.scala

@@ -0,0 +1,51 @@
+// See LICENSE for license details.
+package chipyard.fpga.vcu118
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.mockaon._
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.i2c._
+
+import sifive.fpgashells.shell.{DesignKey}
+
+import chipyard.{BuildTop}
+
+class WithChipyardBuildTop extends Config((site, here, up) => {
+  //case DesignKey => { (p:Parameters) => p(BuildTop)(p) }
+  case DesignKey => {(p: Parameters) => new chipyard.ChipTop()(p) }
+})
+
+class WithBringupUARTs extends Config((site, here, up) => {
+  case PeripheryUARTKey => List(
+    UARTParams(address = BigInt(0x64000000L)),
+    UARTParams(address = BigInt(0x64003000L)))
+})
+
+class FakeBringupConfig extends Config(
+  new WithUARTConnection1 ++
+  new WithBringupUARTs ++
+  new WithChipyardBuildTop ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.With1TinyCore ++
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+  new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
+  new freechips.rocketchip.subsystem.WithJtagDTM ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
+  new freechips.rocketchip.system.BaseConfig)

fpga/src/main/scala/vcu118/IOBinders.scala

@@ -0,0 +1,69 @@
+package chipyard.fpga.vcu118
+
+import chisel3._
+import chisel3.experimental.{attach, IO}
+
+import freechips.rocketchip.util._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.subsystem.{NExtTopInterrupts}
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.i2c._
+import sifive.blocks.devices.mockaon._
+import sifive.blocks.devices.jtag._
+import sifive.blocks.devices.pinctrl._
+
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
+
+import chipsalliance.rocketchip.config._
+import sifive.fpgashells.shell._
+
+import chipyard.iobinders.{OverrideIOBinder, GetSystemParameters}
+import chipyard.{HasHarnessSignalReferences}
+import freechips.rocketchip.diplomacy._
+
+class WithUARTConnection1 extends OverrideIOBinder({
+  (system: HasPeripheryUARTModuleImp) => {
+
+    implicit val p: Parameters = GetSystemParameters(system)
+
+    val io_uart_pins = p(PeripheryUARTKey).zipWithIndex map { case (c, i) => IO(new UARTPortIO(c)).suggestName(s"uart_$i") }
+    (io_uart_pins zip system.uart) map { case (p, r) => p <> r }
+
+    val harnessFn = (th: HasHarnessSignalReferences) => {
+      println(th)
+      println("Got here - --  - - - ")
+      Nil
+    }
+    //val harnessFn = (baseTh: HasHarnessSignalReferences) => {
+    //  println("DEBUG: ---------------------- 0")
+    //  baseTh match { case th: VCU118Shell =>
+    //    println("DEBUG: ---------------------- 1")
+
+    //    val io_uart_pins_bb = p(PeripheryUARTKey) map { c => BundleBridgeSource(() => (new UARTPortIO(c))) }
+
+    //    InModuleBody {
+    //      (io_uart_pins_bb zip io_uart_pins) map { case (p, r) => p.bundle <> r }
+    //    }
+
+    //    require(p(PeripheryUARTKey).size >= 1)
+
+    //    println("DEBUG: ---------------------- 2")
+
+    //    th.designParameters(UARTOverlayKey).foreach { uok =>
+    //      println("DEBUG: ---------------------- 3")
+    //      uok.place(UARTDesignInput(io_uart_pins_bb(0))).overlayOutput
+    //    }
+
+    //    Nil
+    //  }
+    //}
+
+    Seq((Nil, Nil, Some(harnessFn)))
+  }
+})
+

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -0,0 +1,36 @@
+package chipyard.fpga.vcu118
+
+import chisel3._
+import chisel3.experimental.{Analog, IO}
+
+import freechips.rocketchip.diplomacy.{LazyModule, LazyRawModuleImp}
+import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.diplomacy.{InModuleBody}
+
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell._
+import sifive.fpgashells.clocks._
+
+import chipyard.{BuildTop, HasHarnessSignalReferences, HasTestHarnessFunctions}
+
+class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118Shell with HasHarnessSignalReferences {
+  val pllResetAsReset = InModuleBody{ Wire(Reset()) }
+
+  InModuleBody {
+    pllResetAsReset := pllReset
+  }
+
+  lazy val harnessClock = this.module.sysclk
+  lazy val harnessReset = pllResetAsReset.getWrappedValue
+  val success = false.B
+  lazy val dutReset = pllResetAsReset.getWrappedValue
+
+  // must be after HasHarnessSignalReferences assignments
+  println(s"DEBUG: ----- sz:${topDesign.harnessFunctions.size}")
+  topDesign match { case d: HasTestHarnessFunctions =>
+    println(s"DEBUG: ----- sz:${d.harnessFunctions.size}")
+    d.harnessFunctions.foreach(_(this))
+  }
+}
+